1
November 1997
ACS257MS
Radiation Hardened
Quad 2-Input Multiplexer with Three-State Outputs
Features
QML Qualified Per MIL-PRF-38535 Requirements
1.25Micron Radiation Hardened SOS CMOS
Radiation Environment
- Latch-up Free Under any Conditions
- Total Dose . . . . . . . . . . . . . . . . . . . . . . 3 x 10
5
RAD(Si)
- SEU Immunity . . . . . . . . . . . <1 x 10
-10
Errors/Bit/Day
- SEU LET Threshold . . . . . . . . . . . >100MeV/(mg/cm
2
)
Input Logic Levels . . .V
IL
= (0.3)(V
CC
), V
IH
= (0.7)(V
CC
)
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8mA
Quiescent Supply Current. . . . . . . . . . . . . . . . . . .400
A
Propagation Delay
- Enable to Output . . . . . . . . . . . . . . . . . . . . . . . . . 13ns
- Input or Address to Output . . . . . . . . . . . . . . . . . 14ns
Applications
4-Bit Source Selection
Data Routing
High Frequency Switching
Description
The Radiation Hardened ACS257MS is a Quad 2-Channel
multiplexer which selects four bits of data from one of two
sources under the control of a single select pin. The Output
Enable input is active LOW and controls all outputs. When OE
is set HIGH, all outputs are configured into a high impedance
state, regardless of all other input conditions. All inputs are buff-
ered and the outputs are designed for balanced propagation
delay and transition times.
The ACS257MS is fabricated on a CMOS Silicon on Sapphire
(SOS) process, which provides an immunity to Single Event
Latch-up and the capability of highly reliable performance in
any radiation environment. These devices offer significant
power reduction and faster performance when compared to
ALSTTL types.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed below must be used when ordering.
Detailed Electrical Specifications for the ACS257 are
contained in SMD 5962-98008. A "hot-link" is provided
on our homepage with instructions for downloading.
http://www.intersil.com/data/sm/index.htm
Ordering Information
SMD PART NUMBER
INTERSIL PART NUMBER
TEMP. RANGE (
o
C)
PACKAGE
CASE OUTLINE
5962F9800801VEC
ACS257DMSR-02
-55 to 125
16 Ld SBDIP
CDIP2-T16
N/A
ACS257D/Sample-02
25
16 Ld SBDIP
CDIP2-T16
5962F9800801VXC
ACS257KMSR-02
-55 to 125
16 Ld Flatpack
CDFP4-F16
N/A
ACS257K/Sample-02
25
16 Ld Flatpack
CDFP4-F16
N/A
ACS257HMSR-02
25
Die
N/A
Pinouts
ACS257 (SBDIP)
TOP VIEW
ACS257 (FLATPACK)
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
S
1I
0
1I
1
1Y
2I
0
2I
1
GND
2Y
V
CC
4I
0
4I
1
4Y
3I
0
3I
1
3Y
OE
S
1I
0
1I
1
1Y
2I
0
2I
1
2Y
GND
2
3
4
5
6
7
8
1
16
15
14
13
12
11
10
9
V
CC
OE
4I
0
4I
1
4Y
3I
0
3I
1
3Y
File Number
4429
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
2
Die Characteristics
DIE DIMENSIONS:
Size: 2390
m x 2390
m (94 mils x 94 mils)
Thickness: 525
m
25
m (20.6 mils
1 mil)
Bond Pad: 110
m x 110
m (4.3 x 4.3 mils)
METALLIZATION: Al
Metal 1 Thickness: 0.7
m
0.1
m
Metal 2 Thickness: 1.0
m
0.1
m
SUBSTRATE POTENTIAL:
Unbiased Insulator
PASSIVATION
Type: Phosphorous Silicon Glass (PSG)
Thickness: 1.30
m
0.15
m
SPECIAL INSTRUCTIONS:
Bond V
CC
First
ADDITIONAL INFORMATION:
Worst Case Density: <2.0 x 10
5
A/cm
2
Transistor Count: 212
Metallization Mask Layout
ACS257MS
1I
0
S
V
CC
OE
1I
1
1Y
2I
0
2I
1
4I
0
4I
1
4Y
3I
0
2Y
GND
3Y
3I
1
ACS257MS
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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