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Электронный компонент: 5962R9572701TXC

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1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
Satellite Applications FlowTM (SAF) is a trademark of Intersil Corporation.
HCS138T
Radiation Hardened Inverting 3-to-8 Line
Decoder/Demultiplexer
Intersil`s Satellite Applications Flow
TM
(SAF) devices are
fully tested and guaranteed to 100kRAD total dose. These
QML Class T devices are processed to a standard flow
intended to meet the cost and shorter lead-time needs of
large volume satellite manufacturers, while maintaining a
high level of reliability.
The Intersil HCS138T is a Radiation Hardened 3-to-8 Line
Decoder/Demultiplexer. The outputs are active in the low
state. Two active low and one active high enables (E1, E2,
E3) are provided. If the device is enabled, the binary inputs
(A0, A1, A2) determine which one of the eight normally high
outputs will go to a low logic level.
Specifications
Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
Detailed Electrical Specifications for the HCS138T are
contained in SMD 5962-95727. A "hot-link" is provided from
our website for downloading.
www.intersil.com/spacedefense/newsafclasst.asp
Intersil`s Quality Management Plan (QM Plan), listing all
Class T screening operations, is also available on our
website.
www.intersil.com/spacedefense/newsafclasst.asp
Features
QML Class T, Per MIL-PRF-38535
Radiation Performance
- Gamma Dose (
) 1 x 10
5
RAD(Si)
- Latch-Up Free Under Any Conditions
- SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
- Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/Bit-Day (Typ)
3 Micron Radiation Hardened SOS CMOS
Fanout (Over Temperature Range)
- Standard Outputs - 10 LSTTL Loads
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
Input Logic Levels
- V
IL
= 0.3 V
CC
Max
- V
IH
= 0.7 V
CC
Min
Input Current Levels Ii
5mA at V
OL
, V
OH
Pinouts
HCS138DTR (SBDIP), CDIP2-T16
TOP VIEW
HCS138KTR (FLATPACK), CDFP4-F16
TOP VIEW
Ordering Information
ORDERING
NUMBER
PART
NUMBER
TEMP.
RANGE
(
o
C)
5962R9572701TEC
HCS138DTR
-55 to 125
5962R9572701TXC
HCS138KTR
-55 to 125
NOTE:
Minimum order quantity for -T is 150 units through
distribution, or 450 units direct.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
A0
A1
A2
E1
E2
E3
GND
Y7
V
CC
Y1
Y2
Y3
Y4
Y5
Y6
Y0
A0
A1
A2
E1
E2
E3
Y7
GND
V
CC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
2
3
4
5
6
7
8
1
16
15
14
13
12
11
10
9
Data Sheet
July 1999
File Number
4614.1
2
Functional Diagram
TRUTH TABLE
INPUTS
OUTPUTS
ENABLE
E3
E2
E1
A2
A1
A0
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
X
X
H
X
X
X
H
H
H
H
H
H
H
H
L
X
X
X
X
X
H
H
H
H
H
H
H
H
X
H
X
X
X
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
L
H
H
H
H
H
H
H
L
L
L
H
L
H
H
L
H
H
H
H
H
H
L
L
L
H
H
H
H
H
L
H
H
H
H
H
L
L
H
L
L
H
H
H
H
L
H
H
H
H
L
L
H
L
H
H
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
L
H = High Level, L = Low Level, X = Don't Care
A1
A2
E3
E2
E1
A0
4
5
6
3
2
1
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
15
14
13
12
11
10
9
7
HCS138T
3
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Die Characteristics
DIE DIMENSIONS:
(2159
m x 2565
m x 533
m
51
m)
85 x 101 x 21mils
2mil
METALLIZATION:
Type: Al Si
Thickness: 11.0k
1k
SUBSTRATE POTENTIAL:
Unbiased Silicon on Sapphire
BACKSIDE FINISH:
Sapphire
PASSIVATION:
Type: Silox (S
i
O
2
)
Thickness: 13.0k
2.6k
WORST CASE CURRENT DENSITY:
< 2.0e5 A/cm
2
TRANSISTOR COUNT:
264
PROCESS:
CMOS SOS
Metallization Mask Layout
HCS138T
A1
A0
V
CC
A2 (3)
E1 (4)
E2 (5)
E3 (6)
(8)
(9)
(10)
(11) Y4
(12) Y3
(13) Y2
(14) Y1
(2)
(1)
(16)
GND
Y6
Y5
(7)
Y0
(15)
NC
NC
Y7
NC
NC
NOTE:
The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location. The
mask series for the HCS138 is TA14361A.
HCS138T