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Электронный компонент: 8501501XA

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5-1
March 1997
82C52
CMOS Serial Controller Interface
Features
Single Chip UART/BRG
DC to 16MHz (1M Baud) Operation
Crystal or External Clock Input
On-Chip Baud Rate Generator - 72 Selectable Baud
Rates
Interrupt Mode with Mask Capability
Microprocessor Bus Oriented Interface
80C86 Compatible
Single +5V Power Supply
Low Power Operation . . . . . . . . . . . . . . . 1mA/MHz Typ
Modem Interface
Line Break Generation and Detection
Operating Temperature Range:
- C82C52 . . . . . . . . . . . . . . . . . . . . . . . . . .0
o
C to +70
o
C
- I82C52 . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
- M82C52 . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Description
The Intersil 82C52 is a high performance programmable
Universal Asynchronous Receiver/Transmitter (UART) and
Baud Rate Generator (BRG) on a single chip. Utilizing the
Intersil advanced Scaled SAJI IV CMOS process, the 82C52
will support data rates up to 1M baud asynchronously with a
16X clock (16MHz clock frequency).
The on-chip Baud Rate Generator can be programmed for
any one of 72 different baud rates using a single industry
standard crystal or external frequency source. A unique pre-
scale divide circuit has been designed to provide standard
RS-232-C baud rates when using any one of three industry
standard crystals (1.8432MHz, 2.4576MHz, or 3.072MHz).
A programmable buffered clock output (CO) is available and
can be programmed to provide either a buffered oscillator or
16X baud rate clock for general purpose system usage.
Pinouts
Ordering Information
PACKAGE
TEMPERATURE
RANGE
1M BAUD
PKG. NO.
PDIP
0
o
C to +70
o
C
CP82C52
E28.6
-40
o
C to +85
o
C
IP82C52
E28.6
PLCC
0
o
C to +70
o
C
CS82C52
N28.45
-40
o
C to +85
o
C
IS82C52
N28.45
CERDIP
0
o
C to +70
o
C
CD82C52
F28.6
-40
o
C to +85
o
C
ID82C52
F28.6
-55
o
C to +125
o
C
MD82C52/B
F28.6
SMD#
8501501XA
F28.6
CLCC
-55
o
C to +125
o
C
MR82C52/B
J28.A
SMD#
85015013A
J28.A
82C52 (PDIP, CERDIP)
TOP VIEW
82C52 (PLCC, CLCC)
TOP VIEW
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RD
WR
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
IX
OX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CSO
DR
SDI
INTR
RST
CO
DTR
DSR
CTS
GND
SDO
VCC
TBRE
RTS
23
24
25
22
21
20
19
11
3
2
1
4
14
15
16
17
18
12
13
28
27
26
10
5
6
7
8
9
D2
D3
D4
D5
D6
D7
A0
SDI
INTR
RST
TBRE
CO
RTS
DTR
A1
IX
OX
SDO
GND
DSR
CTS
D1
D0
WR
RD
CSO
DR
VCC
File Number
2950.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
5-2
Block Diagram
Pin Description
SYMBOL
PIN
NO.
TYPE
ACTIVE
LEVEL
DESCRIPTION
RD
1
I
Low
READ: The RD input causes the 82C52 to output data to the data bus (D0-D7). The data
output depends upon the state of the address inputs (A0-A1). CS0 enables the RD input.
WR
2
I
Low
WRITE: The WR input causes data from the data bus (D0-D7) to be input to the 82C52.
Addressing and chip select action is the same as for read operations.
D0-D7
3-10
I/O
High
DATA BITS 0-7: The Data Bus provides eight, three-state input/output lines for the transfer of
data, control and status information between the 82C52 and the CPU. For character formats
of less than 8 bits, the corresponding D7, D6 and D5 are considered "don't cares" for data
WRITE operations and are 0 for data READ operations. These lines are normally in a high
impedance state except during read operations. D0 is the Least Significant Bit (LSB) and is the
first serial data bit to be received or transmitted.
A0, A1
11, 12
I
High
ADDRESS INPUTS: The address lines select the various internal registers during CPU bus
operations.
IX, OX
13, 14
I/O
CRYSTAL/CLOCK: Crystal connections for the internal Baud Rate Generator. IX can also be
used as an external clock input in which case OX should be left open.
SDO
15
O
High
SERIAL DATA OUTPUT: Serial data output from the 82C52 transmitter circuitry. A Mark (1) is
a logic one (high) and Space (0) is logic zero (low). SD0 is held in the Mark condition when
CTS is false, when RST is true, when the Transmitter Register is empty, or when in the Loop
Mode.
GND
16
Low
GROUND: Power supply ground connection.
CTS
17
I
Low
CLEAR TO SEND: The logical state of the CTS line is reflected in the CTS bit of the Modem
Status Register. Any change of state in CTS causes INTR to be set true when INTEN and
MIEN are true. A false level on CTS will inhibit transmission of data on the SD0 output and will
hold SD0 in the Mark (high) state. If CTS goes false during transmission, the current character
being transmitted will be completed. CTS does not affect Loop Mode operation.
READ/WRITE
CONTROL
LOGIC
DATA
BUS
BUFFER
PROGRAM-
MABLE
BOUD RATE
CONTROL
LOGIC
3 - 10
1
2
11
12
RD
WR
A0
A1
28
CSO
14
21
OX
CO
23
24
RST
INTR
13
IX
GENERATOR
INTERNAL D
A
T
A
B
U
S
TRANSMITTER
BUFFER
REGISTER
UART
CONTROL AND
STATUS
RECEIVER
BUFFER
REGISTER
MODEM
CONTROL AND
REGISTERS
STATUS
REGISTERS
18
DSR
17
CTS
19
DTR
20
RTS
TRANSMITTER
REGISTER
P
RECEIVER
REGISTER
P
S
15
25
SDO
SDI
22
26
TBRE
DR
S
D0-D7
82C52
5-3
DSR
18
I
Low
DATA SET READY: The logical state of the DSR line is reflected in the Modem Status Register.
Any change of state of DSR will cause INTR to be set if INTEN and MIEN are true. The state
of this signal does not affect any other circuitry within the 82C52.
DTR
19
O
Low
DATA TERMINAL READY: The DTR signal can be set (low) by writing a logic 1 to the appro-
priate bit in the Modem Control Register (MCR). This signal is cleared (high) by writing a logic
0 in the DTR bit in the MCR or whenever a reset (RST = high) is applied to the 82C52.
RTS
20
O
Low
REQUEST TO SEND: The RTS signal can be set (low) by writing a logic 1 to the appropriate
bit in the MCR. This signal is cleared (high) by writing a logic 0 to the RTS bit in the MCR or
whenever a reset (RST = high) is applied to the 82C52.
CO
21
O
CLOCK OUT: This output is user programmable to provide either a buffered IX output or a
buffered Baud Rate Generator (16X) clock output. The buffered IX (Crystal or external clock
source) output is provided when the Baud Rate Select Register (BRSR) bit 7 is set to a zero.
Writing a logic one to BRSR bit 7 causes the CO output to provide a buffered version of the
internal Baud Rate Generator clock which operates at sixteen times the programmed baud
rate. On reset D7 (CO select) is reset to 0.
TBRE
22
O
High
TRANSMITTER BUFFER REGISTER EMPTY: The TBRE output is set (high) whenever the
Transmitter Buffer Register (TBR) has transferred its data to the Transmit Register. Application
of a reset (RST) to the 82C52 will also set the TBRE output. TBRE is cleared (low) whenever
data is written to the TBR.
RST
23
I
High
RESET: The RST input forces the 82C52 into an "Idle" mode in which all serial data activities
are suspended. The Modem Control Register (MCR) along with its associated outputs are
cleared. The UART Status Register (USR) is cleared except for the TBRE and TC bits, which
are set. The 82C52 remains in an "Idle" state until programmed to resume serial data activities.
The RST input is a Schmitt triggered input.
INTR
24
O
High
INTERRUPT REQUEST: The INTR output is enabled by the INTEN bit in the Modem Control
Register (MCR). The MIEN bit selectively enables modem status changes to provide an input
to the INTR logic. Figure 9 in Design Information shows the overall relationship of these inter-
rupt control signals.
SDI
25
I
High
SERIAL DATA INPUT: Serial data input to the 82C52 receiver circuits. A Mark (1) is high, and
a Space (0) is low. Data inputs on SDI are disabled when operating in the loop mode or when
RST is true.
DR
26
O
High
DATA READY: A true level indicates that a character has been received, transferred to the
RBR, and is ready for transfer to the CPU. DR is reset on a data READ of the Receiver Buffer
Register (RBR) or when RST is true.
V
CC
27
High
V
CC
: +5V positive power supply pin. A 0.1
F decoupling capacitor from V
CC
(Pin 27) to GND
(Pin 16) is recommended.
CS0
28
I
Low
CHIP SELECT: The chip select input acts as an enable signal for the RD and WR input
signals.
Pin Description
(Continued)
SYMBOL
PIN
NO.
TYPE
ACTIVE
LEVEL
DESCRIPTION
82C52
5-4
Reset
During and after power-up, the 82C52 Reset Input (RST)
must be held high for at least two IX clock cycles in order to
initialize and drive the 82C52 circuits to an idle mode until
proper programming can be done. A high on RST causes
the following events to occur
Resets the internal Baud Rate Generator (BRG) circuit
clock counters and bit counters. The Baud Rate Select
Register (BRSR) is not affected (except for bit 7 which is
reset to 0).
Clears the UART Status Register (USR) except for
Transmission Complete (TC) and Transmit Buffer Register
Empty (TBRE) which are set. The Modem Control
Register (MCR) is also cleared. All of the discrete lines,
memory elements and miscellaneous logic associated
with these register bits are also cleared or turned off. Note
that the UART Control Register (UCR) is not affected.
Following removal of the reset condition (RST = low), the
82C52 remains in the idle mode until programmed to its
desired system configuration.
Programming The 82C52
The complete functional definition of the 82C52 is
programmed by the systems software. A set of control words
(UCR, BRSR and MCR) must be sent out by the CPU to
initialize the 82C52 to support the desired communication
format. These control words will program the character
length, number of stop bits, even/odd/no parity, baud rate,
etc. Once programmed, the 82C52 is ready to perform its
communication functions.
The control registers can be written to in any order. However,
the MCR should be written to last because it controls the
interrupt enables, modem control outputs and the receiver
enable bit. Once the 82C52 is programmed and operational,
these registers can be updated any time the 82C52 is not
immediately transmitting or receiving data.
Table 1. Shows the control signals required to access 82C52
internal registers.
UART Control Register (UCR)
The UCR is a write only register which configures the UART
transmitter and receiver circuits. Data bits D7 and D6 are not
used but should always be set to a logic zero (0) in order to
insure software compatibility with future product upgrades.
During the Echo Mode, the transmitter always repeats the
received word and parity, even when the UCR is
programmed with different or no parity. See Figure 1.
TABLE 1.
CS0
A1
A0
WR
RD
OPERATION
0
0
0
0
1
Data Bus
Transmitter Buffer
Register (TBR)
0
0
0
1
0
Receiver Buffer Register
(RBR)
Data Bus
0
0
1
0
1
Data Bus
UART Control
Register (UCR)
0
0
1
1
0
UART Status Register
(USR)
Data Bus
0
1
0
0
1
Data Bus
Modem Control
Register (MCR)
0
1
0
1
0
MCR
Data Bus
0
1
1
0
1
Data Bus
Bit Rate Select
Register (BRSR)
0
1
1
1
0
Modem Status Register
(MSR)
Data Bus
D7 D6 D5 D4 D3 D2 D1 D0
Stop Bit
Select
0 = 1 Stop Bits
1 = 1.5 Stop Bits (Tx)
and 1 Stop Bit (Rx)
If 5 Data Bits Selected
1 = 2 Stop Bits for 6, 7
or 8 Data Bits Selected
Parity
Control
000 = Tx and Rx Even
001 = Tx and Rx Odd
010 = Tx Even, Rx
Odd
011 = Tx Odd, Rx
Even
100 = Tx Even, Rx
Check Disabled
101 = Tx Odd, Rx
Check Disabled
11X = Generation and
Check Disabled
Word
Length
Select
00 = 5 Bits
01 = 6 Bits
10 = 7 Bits
11 = 8 Bits
Reserved Set to 00 for Future
Product Upgrade
Compatibility
FIGURE 1. UCR
82C52
5-5
Baud Rate Select Register (BRSR)
The 82C52 is designed to operate with a single crystal or
external clock driving the IX input pin. The Baud Rate Select
Register is used to select the divide ratio (one of 72) for the
internal Baud Rate Generator circuitry. The internal circuitry
is separated into two separate counters, a Prescaler and a
Divisor Select. The Prescaler can be set to any one of four
division rates,
1,
3,
4, or
5.
The Prescaler design has been optimized to provide
standard baud rates using any one of three popular crystal
frequencies. By using one of these common system clock
frequencies, 1.8432MHz, 2.4576MHz or 3.072MHz and
Prescaler divide ratios of
3,
4, or
5 respectively, the
Prescaler output will provide a constant 614.4KHz. When
this frequency is further divided by the Divisor Select
counter, any of the standard baud rates from 50 Baud to
38.4Kbaud can be selected (see Table 2). Non-standard
baud rates up to 1Mbaud can be selected by using different
input frequencies (crystal or an external frequency input up
to 16MHz) and/or different Prescaler and Divisor Select
ratios.
Regardless of the baud rate, the baud rate generator
provides a clock which is 16 times the desired baud rate. For
example, in order to operate at a 1Mbaud data rate, a
16MHz crystal, a Prescale rate of
1, and a Divisor Select
rate of "external" would be used. This would provide a
16MHz clock as the output of the Baud Rate Generator to
the Transmitter and Receiver circuits.
The CO select bit in the BRSR selects whether a buffered
version of the external frequency input (IX input) or the Baud
Rate Generator output (16x baud rate clock) will be output
on the CO output (pin 21). The Baud Rate Generator output
will always be a 50% nominal duty cycle except when "exter-
nal" is selected and the Prescaler is set to
3 or
5.
NOTE: These baud rates are based upon the following input
frequency/ Prescale divisor combinations.
1.8432MHz and Prescale =
3
2.4576MHz and Prescale =
4
3.072MHZ and Prescale =
5
All baud rates are exact except for:
Modem Control Register
The MCR is a general purpose control register which can be
written to and read from. The RTS and DTR outputs are
directly controlled by their associated bits in this register.
Note that a logic one asserts a true logic level (low) at these
output pins. The Interrupt Enable (INTEN) bit is the overall
control for the INTR output pin. When INTEN is false, INTR
is held false (low).
The Operating Mode bits configure the 82C52 into one of
four possible modes. "Normal" configures the 82C52 for nor-
mal full or half duplex communications. "Transmit Break"'
enables the transmitter to only transmit break characters
(Start, Data and Stop bits all are logic zero). The Echo Mode
causes any data that is received on the SDI input pin to be
retransmitted on the SDO output pin. Note that this output is
a buffered version of the data seen on the SDI input and is
not a resynchronized output. Also note that normal UART
transmission via the Transmitter Register is disabled when
operating in the Echo mode (see Figure 4). The Loop Test
Mode internally routes transmitted data to the receiver
circuitry for the purpose of self test. The transmit data is
D7 D6 D5 D4 D3 D2 D1 D0
Prescaler
Select
00 =
1
01 =
3
10 =
4
11 =
5
Divisor
Select
00000 =
2
00001 =
4
00010 =
16/3
00011 =
8
00100 =
32/3
00101 =
16
00110 =
58/3
00111 =
22
01000 =
32
01001 =
64
01010 =
128
01011 =
192
01100 =
256
01101 =
288
01110 =
352
01111 =
512
10000 =
768
11111 = External (
1)
CO
Select
0 = IX Output
1 = Brg Output (On
Reset, D7 (CO Select)
is Reset to 0)
FIGURE 2. BRSR
TABLE 2.
BAUD RATE
DIVISOR
38.4K
External
19.2K
2
9600
4
7200
16/3
4800
8
3600
32/3
2400
16
2000
58/3
1800
22
1200
32
600
64
300
128
200
192
150
256
134.5
288
110
352
75
512
50
768
BAUD RATE
ACTUAL
PERCENT ERROR
1800
1745.45
3.03%
2000
1986.2
0.69%
134.5
133.33
0.87%
110
109.09
0.83%
82C52