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Электронный компонент: CA0555E

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1
Semiconductor
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Copyright
Harris Corporation 1999
CA555, CA555C, LM555C
Timers for Timing Delays and Oscillator
Applications in Commercial, Industrial
and Military Equipment
The CA555 and CA555C are highly stable timers for use in
precision timing and oscillator applications. As timers, these
monolithic integrated circuits are capable of producing
accurate time delays for periods ranging from microseconds
through hours. These devices are also useful for astable
oscillator operation and can maintain an accurately
controlled free running frequency and duty cycle with only
two external resistors and one capacitor.
The circuits of the CA555 and CA555C may be triggered by
the falling edge of the waveform signal, and the output of
these circuits can source or sink up to a 200mA current or
drive TTL circuits.
These types are direct replacements for industry types in
packages with similar terminal arrangements e.g. SE555
and NE555, MC1555 and MC1455, respectively. The CA555
type circuits are intended for applications requiring premium
electrical performance. The CA555C type circuits are
intended for applications requiring less stringent electrical
characteristics.
Pinout
CA555, CA555C, LM555C, (PDIP)
TOP VIEW
Features
Accurate Timing From Microseconds Through Hours
Astable and Monostable Operation
Adjustable Duty Cycle
Output Capable of Sourcing or Sinking up to 200mA
Output Capable of Driving TTL Devices
Normally ON and OFF Outputs
High Temperature Stability . . . . . . . . . . . . . . . . 0.005%/
o
C
Directly Interchangeable with SE555, NE555, MC1555,
and MC1455
Applications
Precision Timing
Sequential Timing
Time Delay Generation
Pulse Generation
Pulse Detector
Pulse Width and Position Modulation
Functional Block Diagram
Part Number Information
PART NUMBER
(BRAND)
TEMP.
RANGE (
o
C)
PACKAGE
PKG.
NO.
CA0555E
-55 to 125
8 Ld PDIP
E8.3
CA0555CE
0 to 70
8 Ld PDIP
E8.3
LM555CN
0 to 70
8 Ld PDIP
E8.3
GND
TRIGGER
OUTPUT
RESET
1
2
3
4
8
7
6
5
V+
DISCHARGE
THRESHOLD
CONTROL
VOLTAGE
THRESHOLD
COMPAR
6
THRESHOLD
8
V+
5
TRIGGER
COMPAR
2
CONTROL
VOLTAGE
TRIGGER
FLIP-FLOP
OUTPUT
3
OUTPUT
7
DISCHARGE
4
RESET
1
GND
December 1999
File Number
834.6
[ /Title
(CA55
5,
CA555
C,
LM555
C)
/Sub-
ject
(Tim-
ers for
Timing
Delays
and
Oscilla-
tor
Appli-
cations
in
Com-
mer-
cial,
Indus-
trial
and
Mili-
tary
Equip-
ment)
/Author
()
/Key-
words
(Harris
Semi-
con-
ductor,
single,
timer,
OBSOLETE PR
ODUCT
POSSIBLE SUBSTITUTE PR
ODUCT
ICM7555
2
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V
Operating Conditions
Temperature Range
CA555 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
CA555C, LM555C . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
JC
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
100
N/A
Maximum Junction Temperature (Plastic Package) . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
o
C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
T
A
= 25
o
C, V+ = 5V to 15V Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
CA555
CA555C, LM555C
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
DC Supply Voltage
V+
4.5
-
18
4.5
-
16
V
DC Supply Current (Low State)
(Note 2)
I+
V+ = 5V, R
L
=
-
3
5
-
3
6
mA
V+ = 15V, R
L
=
-
10
12
-
10
15
mA
Threshold Voltage
V
TH
-
(
2
/
3
)V+
-
-
(
2
/
3
)V+
-
V
Trigger Voltage
V+ = 5V
1.45
1.67
1.9
-
1.67
-
V
V+ = 15V
4.8
5
5.2
-
5
-
V
Trigger Current
-
0.5
-
-
0.5
-
A
Threshold Current (Note 3)
I
TH
-
0.1
0.25
-
0.1
0.25
A
Reset Voltage
0.4
0.7
1.0
0.4
0.7
1.0
V
Reset Current
-
0.1
-
-
0.1
-
mA
Control Voltage Level
V+ = 5V
2.9
3.33
3.8
2.6
3.33
4
V
V+ = 15V
9.6
10
10.4
9
10
11
V
Output Voltage
V
OL
V+ = 5V, I
SINK
= 5mA
-
-
-
-
0.25
0.35
V
Low State
I
SINK
= 8mA
-
0.1
0.25
-
-
-
V
V+ = 15V, I
SINK
= 10mA
-
0.1
0.15
-
0.1
0.25
V
I
SINK
= 50mA
-
0.4
0.5
-
0.4
0.75
V
I
SINK
= 100mA
-
2.0
2.2
-
2.0
2.5
V
I
SINK
= 200mA
-
2.5
-
-
2.5
-
V
Output Voltage
V
OH
V+ = 5V, I
SOURCE
= 100mA
3.0
3.3
-
2.75
3.3
-
V
High State
V+ = 15V, I
SOURCE
= 100mA
13.0
13.3
-
12.75
13.3
-
V
I
SOURCE
= 200mA
-
12.5
-
-
12.5
-
V
Timing Error (Monostable)
R
1
, R
2
= 1k
to 100k
,
C = 0.1
F
Tested at V+ = 5V, V+ = 15V
-
0.5
2
-
1
-
%
Frequency Drift with Temperature
-
30
100
-
50
-
ppm/
o
C
Drift with Supply Voltage
-
0.05
0.2
-
0.1
-
%/V
Output Rise Time
t
R
-
100
-
-
100
-
ns
Output Fall Time
t
F
-
100
-
-
100
-
ns
NOTES:
2. When the output is in a high state, the DC supply current is typically 1mA less than the low state value.
3. The threshold current will determine the sum of the values of R
1
and R
2
to be used in Figure 4 (astable operation); the maximum total
R
1
+ R
2
= 20M
.
CA555, CA555C, LM555C
3
Schematic Diagram
Typical Applications
Reset Timer (Monostable Operation)
Figure 1 shows the CA555 connected as a reset timer. In this
mode of operation capacitor C
T
is initially held discharged by
a transistor on the integrated circuit. Upon closing the "start"
switch, or applying a negative trigger pulse to terminal 2, the
integral timer flip-flop is "set" and releases the short circuit
across C
T
which drives the output voltage "high" (relay
energized). The action allows the voltage across the capacitor
to increase exponentially with the constant t = R
1
C
T
. When
the voltage across the capacitor equals 2/3 V+, the
comparator resets the flip-flop which in turn discharges the
capacitor rapidly and drives the output to its low state.
Since the charge rate and threshold level of the comparator
are both directly proportional to V+, the timing interval is
relatively independent of supply voltage variations. Typically,
the timing varies only 0.05% for a 1V change in V+.
Applying a negative pulse simultaneously to the reset
terminal (4) and the trigger terminal (2) during the timing
cycle discharges C
T
and causes the timing cycle to restart.
Momentarily closing only the reset switch during the timing
interval discharges C
T
, but the timing cycle does not restart.
6
THRESHOLD
7
RESET
DISCHARGE
V-
RESET
DISCHARGE
3
OUTPUT
OUTPUT
FLIP-FLOP
TRIGGER
COMPARATOR
THRESHOLD
COMPARATOR
4.7K
830
4.7K
D
2
D
1
Q
3
Q
4
Q
7
Q
5
Q
2
Q
1
10K
Q
8
Q
6
100
100K
Q
9
Q
11
Q
12
1K
Q
10
5K
Q
13
Q
16
7K
D
3
Q
14
Q
15
Q
17
3.9K
Q
19
Q
20
Q
21
Q
18
8
V+
CONTROL
VOLTAGE
5K
6.8K
5K
4.7K
220
4.7K
5
2
4
1
TRIGGER
D
4
NOTE: Resistance values are in ohms.
1
CA555
EO
8
5
2
6
7
3
4
680
RESET
R
1
C
T
4.7K
680
10K
0.01
F
RELAY
COIL
1N4001
V+
5V
S
1
START
NOTE: All resistance values are in ohms.
FIGURE 1. RESET TIMER (MONOSTABLE OPERATION)
CA555, CA555C, LM555C
4
Figure 2 shows the typical waveforms generated during this
mode of operation, and Figure 3 gives the family of time
delay curves with variations in R
1
and C
T
.
Repeat Cycle Timer (Astable Operation)
Figure 4 shows the CA555 connected as a repeat cycle
timer. In this mode of operation, the total period is a function
of both R
1
and R
2.
T = 0.693 (R
1
+ 2R
2
) C
T
= t
1
+ t
2
where t
1
= 0.693 (R
1
+ R
2
) C
T
and t
2
= 0.693 (R
2
) C
T
the duty cycle is:
Typical waveforms generated during this mode of operation
are shown in Figure 5. Figure 6 gives the family of curves of
free running frequency with variations in the value of
(R
1
+ 2R
2
) and C
T
.
t
D
3V
3.3V
5V
0
0
0
SWITCH S
1
"OPEN"
SWITCH S
1
"CLOSED"
INPUT
VOLTAGE (TERMINAL 2)
CAPACITOR
VOLTAGE (TERMINALS 6, 7)
OUTPUT
VOLTAGE
(TERMINAL 3)
FIGURE 2. TYPICAL WAVEFORMS FOR RESET TIMER
TIME DELAY(s)
10
1
10
-1
0.1
0.01
0.001
T
A
= 25
o
C
R
1
= 1k
10k
CAP
A
CIT
ANCE (
F)
1
10
100
V+ = 5V
100k
1M
10M
10
-2
10
-3
10
-4
10
-5
FIGURE 3. TIME DELAY vs RESISTANCE AND CAPACITANCE
1
CA555
EO
8
5
2
6
7
3
4
R
1
C
T
0.01
F
RELAY
COIL
R
2
V+
5V
FIGURE 4. REPEAT CYCLE TIMER (ASTABLE OPERATION)
t
1
t
1
t
2
+
----------------
=
R
1
R
2
+
R
1
2R
2
+
------------------------
CA555, CA555C, LM555C
5
Top Trace: Output voltage (2V/Div. and 0.5ms/Div.)
Bottom Trace: Capacitor voltage (1V/Div. and 0.5ms/Div.)
FIGURE 5. TYPICAL WAVEFORMS FOR REPEAT CYCLE TIMER
FIGURE 6. FREE RUNNING FREQUENCY OF REPEAT CYCLE
TIMER WITH VARIATION IN CAPACITANCE AND
RESISTANCE
Typical Performance Curves
NOTE: Where x is the decimal multiplier of the supply voltage.
FIGURE 7. MINIMUM PULSE WIDTH vs MINIMUM TRIGGER
VOLTAGE
FIGURE 8. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 9. OUTPUT VOLTAGE DROP (HIGH STATE) vs
SOURCE CURRENT
FIGURE 10. OUTPUT VOLTAGE LOW STATE vs SINK
CURRENT
5V
0
3.3V
1.7V
0
t
2
t
1
100
10
0.1
0.01
0.001
CAP
A
CIT
ANCE (
F)
FREQUENCY (Hz)
10
-1
1
10
10
2
10
3
10
4
10
5
T
A
= 25
o
C, V+ = 5V
R
1
+ 2R
2
= 1k
10k
100k
1M
10M
1
MINIMUM TRIGGER (PULSE) VOLTAGE (x V+) (NOTE)
0.4
0.3
0.2
0.1
0
150
100
50
T
A
= -55
o
C
25
o
C
125
o
C
70
o
C
0
o
C
MINIMUM PULSE WIDTH (ns)
SUPPLY VOLTAGE (V)
SUPPL
Y CURRENT (mA)
15
12.5
10
7.5
5
2.5
0
10
9
8
7
6
5
4
3
2
1
T
A
= 125
o
C
25
o
C
50
o
C
SOURCE CURRENT (mA)
SUPPL
Y V
O
L
T
A
GE - OUTPUT V
O
L
T
A
GE (V)
100
10
1
2.0
1.6
1.2
0.8
0.4
0
25
o
C
T
A
= -55
o
C
125
o
C
5V
V+
15V
SINK CURRENT (mA)
OUTPUT V
O
L
T
A
GE - LO
W ST
A
TE (V)
100
10
1
10.0
1.0
0.1
0.01
25
o
C
T
A
= -55
o
C
125
o
C
V+ = 5V
CA555, CA555C, LM555C