ChipFind - документация

Электронный компонент: CD4021

Скачать:  PDF   ZIP
1
File Number
3284.6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright Intersil Corporation 1999
DG401, DG403, DG405
Monolithic CMOS Analog Switches
The DG401, DG403 and DG405 monolithic CMOS analog
switches have TTL and CMOS compatible digital inputs.
These switches feature low analog ON resistance (<45
)
and fast switch time (t
ON
< 150ns). Low charge injection
simplifies sample and hold applications.
The improvements in the DG401/403/405 series are made
possible by using a high voltage silicon-gate process. An
epitaxial layer prevents the latch-up associated with older
CMOS technologies. The 44V maximum voltage range
permits controlling 30V
P-P
signals. Power supplies may be
single-ended from +5V to +34V, or split from
5V to
17V.
The analog switches are bilateral, equally matched for AC or
bidirectional signals. The ON resistance variation with analog
signals is quite low over a
15V analog input range. The three
different devices provide the equivalent of two SPST (DG401),
two SPDT (DG403) or two DPST (DG405) relay switch
contacts with CMOS or TTL level activation. The pinout is
similar, permitting a standard layout to be used, choosing the
switch function as needed.
Pinouts
DG401 (PDIP, SOIC)
TOP VIEW
DG403, DG405 (SOIC)
TOP VIEW
NOTE: (NC) No Connection.
Features
ON Resistance (Max) . . . . . . . . . . . . . . . . . . . . . . . . . 45
Low Power Consumption (P
D
) . . . . . . . . . . . . . . . . . . <35
W
Fast Switching Action
- t
ON
(Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150ns
- t
OFF
(Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ns
Low Charge Injection
DG401 Dual SPST; Same Pinout as HI-5041
DG403 Dual SPDT; DG190, IH5043, IH5151, HI-5051
DG405 Dual DPST; DG184, HI-5045, IH5145
TTL, CMOS Compatible
Single or Split Supply Operation
Applications
Audio Switching
Battery Operated Systems
Data Acquisition
Hi-Rel Systems
Sample and Hold Circuits
Communication Systems
Automatic Test Equipment
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
D
1
NC
NC
NC
NC
NC
D
2
NC
S
1
V-
GND
V
L
V+
IN
2
S
2
IN
1
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
D
1
NC
D
3
S
3
S
4
D
4
D
2
NC
S
1
V-
GND
V
L
V+
IN
2
S
2
IN
1
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
PKG. NO.
DG401DJ
-40 to 85
16 Ld PDIP
E16.3
DG401DY
-40 to 85
16 Ld SOIC
M16.15
DG403DJ
-40 to 85
16 Ld PDIP
E16.3
DG403DY
-40 to 85
16 Ld SOIC
M16.15
DG405DY
-40 to 85
16 Ld SOIC
M16.15
TRUTH TABLE
LOGIC
DG401
DG403
DG405
SWITCH
SWITCH 1, 2 SWITCH 3, 4
SWITCH
0
OFF
OFF
ON
OFF
1
ON
ON
OFF
ON
NOTE:
Logic "0"
0.8V. Logic "1"
2.4V.
Data Sheet
June 1999
2
Schematic Diagram
Functional Diagrams
DG401
DG403
DG405
SWITCHES SHOWN FOR LOGIC "1" INPUT
15
10
9
16
8
1
S
1
IN
1
IN
2
S
2
D
1
D
2
V
L
V+
GND
V-
12
11
13
14
15
10
9
4
16
5
8
3
1
6
S
1
S
3
IN
1
IN
2
S
2
S
4
D
1
D
3
D
2
D
4
V
L
V+
GND
V-
12
11
13
14
15
10
9
4
16
5
8
3
1
6
S
1
S
3
IN
1
IN
2
S
2
S
4
D
1
D
3
D
2
D
4
V
L
V+
GND
V-
12
11
13
14
V-
V+
V+
V
L
V
IN
GND
V-
DRAIN
SOURCE
DG401, DG403, DG405
3
Absolute Maximum Ratings
Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0V
GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
V
L
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to (V+) +0.3V
Digital Inputs V
S
, V
D
(Note 1) . . . . . (V-) -2V to (V+) + 2V or 30mA,
Whichever Occurs First
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA
Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle, Max) . . 100mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20V (Max)
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V (Max)
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V (Min)
Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20ns
Thermal Resistance (Typical, Note 2)
JA
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
115
Maximum Junction Temperature (Plastic Package) . . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Signals on S
X
, D
X
, or IN
X
exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
2.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Test Conditions: V+ = +15V, V- = -15V, V
IN
= 2.4V, 0.8V (Note 3), V
L
= 5V,
Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
TEMP
(
o
C)
(NOTE 4)
MIN
(NOTE 5)
TYP
(NOTE 4)
MAX
UNITS
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
ON
R
L
= 300
, C
L
= 35pF
25
-
100
150
ns
Turn-OFF Time, t
OFF
25
-
60
100
ns
Break-Before-Make Time Delay (DG403), t
D
R
L
= 300
, C
L
= 35pF
25
5
12
-
ns
Charge Injection, Q (Figure 3)
C
L
= 10nF, V
G
= 0V, R
G
= 0
25
-
60
-
pC
OFF Isolation (Figure 4)
R
L
= 100
, C
L
= 5pF, f = 1MHz
25
-
72
-
dB
Crosstalk (Channel-to-Channel) (Figure 6)
25
-
-90
-
dB
Source OFF Capacitance, C
S(OFF)
f = 1MHz, V
S
= V
D
= 0V (Figure 7)
25
-
12
-
pF
Drain OFF Capacitance, C
D(OFF)
25
-
12
-
pF
Channel ON Capacitance, C
D(ON)
+ C
S(ON)
25
-
39
-
pF
DIGITAL INPUT CHARACTERISTICS
Input Current with V
IN
Low, I
IL
V
IN
Under Test = 0.8V, All Others = 2.4V
Full
-1
0.005
1
A
Input Current with V
IN
High, I
IH
V
IN
Under Test = 2.4V, All Others = 0.8V
Full
-1
0.005
1
A
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
-15
-
15
V
Drain-Source ON Resistance, r
DS(ON)
V+ = 13.5V, V- = -13.5V,
I
S
=
10mA, V
D
=
10V
25
-
20
45
Full
-
-
55
r
DS(ON)
Matching Between Channels,
r
DS(ON)
V+ = 16.5V, V- = -16.5V,
I
S
= -10mA, V
D
= 5, 0, -5V
25
-
3
3
Full
-
-
5
Source OFF Leakage Current, I
S(OFF)
V+ = 16.5V, V- = -16.5
V
D
=
15.5V, V
S
=
15.5V
25
-0.5
-0.01
0.5
nA
Full
-5
-
5
nA
Drain OFF Leakage Current, I
D(OFF)
25
-0.5
-0.01
0.5
nA
Full
-5
-
5
nA
Channel ON Leakage Current, I
D(ON)
+ I
S(ON)
V
=
16.5V, V
D
= V
S
=
15.5V
25
-1
-0.04
1
nA
Full
-10
-
10
nA
DG401, DG403, DG405
4
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = 16.5V, V- = -16.5V,
V
IN
= 0V or 5V
25
-
0.01
1
A
Full
-
-
5
A
Negative Supply Current, I-
25
-1
-0.01
-
A
Full
-5
-
-
A
Logic Supply Current, I
L
25
-
0.01
1
A
Full
-
-
5
A
Ground Current, I
GND
25
-1
-0.01
-
A
Full
-5
-
-
A
NOTES:
3. V
IN
= input voltage to perform proper function.
4. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
5. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Electrical Specifications
Test Conditions: V+ = +15V, V- = -15V, V
IN
= 2.4V, 0.8V (Note 3), V
L
= 5V,
Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
TEMP
(
o
C)
(NOTE 4)
MIN
(NOTE 5)
TYP
(NOTE 4)
MAX
UNITS
Test Circuits and Waveforms
NOTES:
6. Logic input waveform is inverted for switches that have the
opposite logic sense.
7. V
S
= 10V for t
ON
, V
S
= -10V for t
OFF
.
FIGURE 1A. MEASUREMENT POINTS
Repeat test for IN
2
and S
2
.
For load conditions, see Specifications. C
L
includes fixture and stray
capacitance.
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
FIGURE 2A. MEASUREMENT POINTS
C
L
includes fixture and stray capacitance.
FIGURE 2B. TEST CIRCUIT
FIGURE 2. BREAK-BEFORE-MAKE TIME
50%
t
r
< 20ns
t
f
< 20ns
t
OFF
90%
3V
0V
V
S
0V
t
ON
V
O
LOGIC
INPUT
SWITCH
INPUT
SWITCH
OUTPUT
90%
-V
S
SWITCH
INPUT
10%
(NOTE 7)
V
O
V
S
R
L
R
L
r
DS ON
(
)
+
------------------------------------
=
SWITCH
INPUT
LOGIC
INPUT
S
1
IN
1
V+
D
1
R
L
C
L
V
O
GND
V-
V
L
0V
-15V
5V
+15V
R
L
= 300
C
L
= 35pF
90%
3V
0V
t
D
0V
LOGIC
INPUT
SWITCH
OUTPUT
SWITCH
OUTPUT
V
S1
V
S2
90%
t
D
0V
(V
O1
)
(V
O2
)
LOGIC
INPUT
V
S1
= 10V
IN
1
V+
D
1
R
L1
C
L1
V
O1
GND
V-
V
L
0V
-15V
5V
+15V
R
L
= 300
C
L
= 35pF
D
2
R
L2
C
L2
V
O2
V
S2
= 10V
DG401, DG403, DG405
5
FIGURE 3A. MEASUREMENT POINTS
FIGURE 3B. TEST CIRCUIT
FIGURE 3. CHARGE INJECTION
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. INSERTION LOSS TEST CIRCUIT
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCES TEST CIRCUIT
Test Circuits and Waveforms
(Continued)
V
O
V
O
IN
X
ON
OFF
ON
Q =
V
O
x C
L
SWITCH
OUTPUT
V+
D
1
C
L
V
O
V-
R
G
V
G
V
L
0V
-15V
5V
+15V
GND
ANALYZER
R
L
+15V
SIGNAL
GENERATOR
V+
C
V-
-15V
C
0V, 2.4V
V
S
V
D
IN
X
GND
+5V
V
L
C
ANALYZER
R
L
+15V
SIGNAL
GENERATOR
V+
C
V-
-15V
C
0V, 2.4V
V
S
V
D
IN
X
GND
+5V
V
L
C
0V, 2.4V
ANALYZER
+15V
V+
C
V
S1
SIGNAL
GENERATOR
R
L
GND
IN
1
V
D1
IN
2
50
0V, 2.4V
NC
V-
-15V
C
V
D2
+5V
V
L
C
V
S2
+15V
V+
C
GND
V
S
V
D
IN
X
V-
-15V
C
IMPEDANCE
ANALYZER
0V, 2.4V
+5V
V
L
C
AS REQUIRED
DG401, DG403, DG405