1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright
Intersil Corporation 1999
CDP6872
Low Power Crystal Oscillator
Description
The CDP6872 is a very low power crystal-controlled oscillators
that can be externally programmed to operate between 10kHz
and 10MHz. For normal operation it requires only the addition
of a crystal. The part exhibits very high stability over a wide
operating voltage and temperature range.
The CDP6872 also features a disable mode that switches
the output to a high impedance state. This feature is useful
for minimizing power dissipation during standby and when
multiple oscillator circuits are employed.
Ordering Information
PART
NUMBER
TEMPERATURE
RANGE
PACKAGE
CDP6872
E
-40
o
C to +85
o
C
8 Lead Plastic DIP
CDP6872
M
-40
o
C to +85
o
C
8 Lead Plastic SOIC (N)
CDP6872
H
-40
o
C to +85
o
C
DIE
Features
Single Supply Operation at 32kHz . . . . . . . 2.0V to 7.0V
Operating Frequency Range. . . . . . . . 10kHz to 10MHz
Supply Current at 32kHz . . . . . . . . . . . . . . . . . . . . . .5
A
Supply Current at 1MHz . . . . . . . . . . . . . . . . . . . .130
A
Drives 2 CMOS Loads
Only Requires an External Crystal for Operation
Applications
Battery Powered Circuits
Remote Metering
Embedded Microprocessors
Palm Top/Notebook PC
January 1996
Pinout
CDP6872 (PDIP, SOIC)
TOP VIEW
V
DD
OSC IN
OSC OUT
V
SS
1
2
3
4
8
7
6
5
ENABLE
FREQ 2
FREQ 1
OUTPUT
Typical Application Circuit
32.768kHz MICROPOWER CLOCK OSCILLATOR
V
DD
1
2
3
4
8
7
6
5
CDP6872
32.768kHz
CLOCK
32.768kHz
CRYSTAL
0.1
f
File Number
4069
2
CDP6872
Simplified Block Diagram
FREQUENCY SELECTION TRUTH TABLE
ENABLE
FREQ 1
FREQ 2
SWITCH
OUTPUT RANGE
1
1
1
S1a, b, c
10kHz - 100kHz
1
1
0
S2
100kHz - 1MHz
1
0
1
S3
1MHz - 5MHz
1
0
0
S4
5MHz - 10MHz+
0
X
X
X
High Impedance
NOTE:
1. Logic input pull-up resistors are constant current source of 0.4
A.
1 OF 4
DECODE
+
-
LEVEL
SHIFTER
BUFFER
BUFFER AMP
OSC IN 2
3 OSC OUT
EXTERNAL CRYSTAL
V
DD
V
DD
I
BIAS
V
DD
- 1.4V
V
DD
- 2.2V
V
DD
- 3.0V
V
DD
- 3.8V
FREQ 1
FREQ 2
7
6
ENABLE
8
V
DD
15pF
S1b
S1c
15pF
V
DD
R
F
V
DD
V
RN
V
RN
S1a
S2
S3
S4
V
DD
4
V
SS
5
OUTPUT
V
DD
1
N
P
V
DD
V
RN
P
IN
R
F
OUT
OSCILLATOR
(NOTE 1)
(NOTE 1)
(NOTE 1)
3
Specifications CDP6872
Absolute Maximum Ratings
Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.0V
Voltage (any pin). . . . . . . . . . . . . . . . . . . . . . .V
SS
-0.3V to V
DD
+0.3V
Junction Temperature (Plastic Package) . . . . . . . . . . . . . . . +150
o
C
ESD Rating (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4000V
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300
o
C
(SOIC - Lead Tip Only)
Operating Temperature (Note 3) . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
Storage Temperature Range. . . . . . . . . . . . . . . . . . -65
o
C to +150
o
C
Thermal Information
(Typical)
Thermal Resistance (
o
C/W)
JA
8 Lead Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . .
125
8 Lead Plastic SOIC . . . . . . . . . . . . . . . . . . . . . . . . . .
170
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
V
SS
= GND, T
A
= +25
o
C, Unless Otherwise Specified
PARAMETER
V
DD
= 5V
V
DD
= 3V
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
V
DD
Supply Range (f
OSC
= 32kHz)
2
5
7
-
-
-
V
I
DD
Supply Current
f
OSC
= 32kHz, EN = 0 Standby
-
5.0
9.0
-
-
-
A
f
OSC
= 32kHz, C
L
= 10pF (Note 1), EN = 1, Freq1 = 1, Freq2 = 1
-
5.2
10.2
-
3.6
6.1
A
f
OSC
= 32kHz, C
L
= 40pF, EN = 1, Freq1 = 1, Freq2 = 1
-
10
15
-
6.5
9
A
f
OSC
= 1MHz, C
L
= 10pF (Note 1), EN = 1, Freq1 = 0, Freq2 = 1
-
130
200
-
90
180
A
f
OSC
= 1MHz, C
L
= 40pF, EN = 1, Freq1 = 0, Freq2 = 1
-
270
350
-
180
270
A
V
OH
Output High Voltage (I
OUT
= -1mA)
4.0
4.9
-
-
2.8
-
V
V
OL
Output Low Voltage (I
OUT
= 1mA)
-
0.07
0.4
-
0.1
-
V
I
OH
Output High Current (V
OUT
4V)
-
-10
-5
-
-
-
mA
I
OL
Output Low Current (V
OUT
0.4V)
5.0
10.0
-
-
-
-
mA
Three-State Leakage Current
(V
OUT
= 0V, 5V, T
A
= 25
o
C, -40
o
C)
-
0.1
-
-
-
-
nA
(V
OUT
= 0V, 5V, T
A
= 85
o
C)
-
10
-
-
-
-
nA
I
IN
Enable, Freq1, Freq2 Input Current (V
IN
= V
SS
to V
DD
)
-
0.4
1.0
-
-
-
A
V
IH
Input High Voltage Enable, Freq1, Freq2
2.0
-
-
-
-
-
V
V
IL
Input Low Voltage Enable, Freq1, Freq2
-
-
0.8
-
-
-
V
Enable Time (C
L
= 18pF, R
L
= 1k
)
-
800
-
-
-
-
ns
Disable Time (C
L
= 18pF, R
L
= 1k
)
-
90
-
-
-
-
ns
t
R
Output Rise Time (10% - 90%, f
OSC
= 32kHz, C
L
= 40pF)
-
12
25
-
12
-
ns
t
F
Output Fall Time (10% - 90%, f
OSC
= 32kHz, C
L
= 40pF)
-
12
25
-
14
-
ns
Duty Cycle (C
L
= 40pF) f
OSC
= 1MHz, Packaged Part Only (Note 4)
40
54
60
-
-
-
%
Duty Cycle (C
L
= 40pF) f
OSC
= 32kHz, (See Typical Curves)
-
41
-
-
44
-
%
Frequency Stability vs. Supply Voltage (f
OSC
= 32kHz, V
DD
= 5V, C
L
=10pF)
-
1
-
-
-
-
ppm/V
Frequency Stability vs. Temperature (f
OSC
= 32kHz, V
DD
= 5V, C
L
=10pF)
-
0.1
-
-
-
-
ppm/
o
C
Frequency Stability vs. Load (f
OSC
= 32kHz, V
DD
= 5V, C
L
=10pF)
-
0.01
-
-
-
-
ppm/pF
NOTES:
1. Calculated using the equation I
DD
= I
DD
(No Load) + (V
DD
) (f
OSC
)(C
L
)
2. Human body model.
3. This product is production tested at +25
o
C only.
4. Duty cycle will vary with supply voltage, oscillation frequency, and parasitic capacitance on the crystal pins.
4
Test Circuits
FIGURE 1.
In production the CDP6872 is tested with a 32kHz and a
1MHz crystal. However for characterization purposes data
was taken using a sinewave generator as the frequency
determining element, as shown in Figure 1. The 1V
P-P
input
is a smaller amplitude than what a typical crystal would gen-
erate so the transitions are slower. In general the Generator
data will show a "worst case" number for I
DD
, duty cycle, and
rise/fall time. The Generator test method is useful for testing
a variety of frequencies quickly and provides curves which
can be used for understanding performance trends. Data for
the CDP6872 using crystals has also been taken. This data
has been overlaid onto the generator data to provide a refer-
ence for comparison.
Theory of Operation
The CDP6872 is a Pierce Oscillator optimized for low power
consumption, requiring no external components except for a
bypass capacitor and a Parallel Mode Crystal. The Simpli-
fied Block Diagram shows the Crystal attached to pins 2 and
3, the Oscillator input and output. The crystal drive circuitry
is detailed showing the simple CMOS inverter stage and the
P-channel device being used as biasing resistor R
F
. The
inverter will operate mostly in its linear region increasing the
amplitude of the oscillation until limited by its transconduc-
tance and voltage rails, V
DD
and V
RN
. The inverter is self
biasing using R
F
to center the oscillating waveform at the
input threshold. Do not interfere with this bias function with
external loads or excessive leakage on pin 2. Nominal value
for R
F
is 17M
in the lowest frequency range to 7M
in the
highest frequency range.
The CDP6872 optimizes its power for 4 frequency ranges
selected by digital inputs Freq1 and Freq2 as shown in the
Block Diagram. Internal pull up resistors (constant current
0.4
A) on Enable, Freq1 and Freq2 allow the user simply to
leave one or all digital inputs not connected for a corre-
sponding "1" state. All digital inputs may be left open for
10kHz to 100kHz operation.
A current source develops 4 selectable reference voltages
through series resistors. The selected voltage, V
RN
, is buff-
ered and used as the negative supply rail for the oscillator
1
2
3
4
8
7
6
5
CDP6872
V
OUT
C
L
+5V
18pF
0.1
F
1000pF
50
ENABLE
FREQ 2
FREQ 1
1V
P-P
CDP6872
section of the circuit. The use of a current source in the refer-
ence string allows for wide supply variation with minimal
effect on performance. The reduced operating voltage of the
oscillator section reduces power consumption and limits
transconductance and bandwidth to the frequency range
selected. For frequencies at the edge of a range, the higher
range may provide better performance.
The OSC OUT waveform on pin 3 is squared up through a
series of inverters to the output drive stage. The Enable
function is implemented with a NAND gate in the inverter
string, gating the signal to the level shifter and output stage.
Also during Disable the output is set to a high impedance
state useful for minimizing power during standby and when
multiple oscillators are OR'd to a single node.
Design Considerations
The low power CMOS transistors are designed to consume
power mostly during transitions. Keeping these transitions
short requires a good decoupling capacitor as close as pos-
sible to the supply pins 1 and 4. A ceramic 0.1
F is recom-
mended. Additional supply decoupling on the circuit board
with 1
F to 10
F will further reduce overshoot, ringing and
power consumption. The CDP6872, when compared to a
crystal and inverter alone, will speed clock transition times,
reducing power consumption of all CMOS circuitry run from
that clock.
Power consumption may be further reduced by minimizing
the capacitance on moving nodes. The majority of the power
will be used in the output stage driving the load. Minimizing
the load and parasitic capacitance on the output, pin 5, will
play the major role in minimizing supply current. A secondary
source of wasted supply current is parasitic or crystal load
capacitance on pins 2 and 3. The CDP6872 is designed to
work with most available crystals in its frequency range with
no external components required. Two 15pF capacitors are
internally switched onto crystal pins 2 and 3 to compensate
the oscillator in the 10kHz to 100kHz frequency range.
The supply current of the CDP6872 may be approximately
calculated from the equation:
I
DD
= I
DD
(Disabled) + V
DD
F
OSC
C
L
where:
I
DD
= Total supply current
V
DD
= Total voltage from V
DD
(pin1) to V
SS
(pin4)
F
OSC
= Frequency of Oscillation
C
L
= Output (pin5) load capacitance
Example #1:
V
DD
= 5V, F
OSC
= 100kHz, C
L
= 30pF
I
DD
(Disabled) = 4.5
A (Figure 10)
I
DD
= 4.5
A + (5V)(100kHz)(30pF) = 19.5
A
Measured I
DD
= 20.3
A
Example #2:
V
DD
= 5V, F
OSC
= 5MHz, C
L
= 30pF
I
DD
(Disabled) = 75
A (Figure 9)
I
DD
= 75
A + (5V)(5MHz)(30pF) = 825
A
Measured I
DD
= 809
A
5
CDP6872
Crystal Selection
For general purpose applications, a Parallel Mode Crystal is
a good choice for use with the CDP6872. However for
applications where a precision frequency is required, the
designer needs to consider other factors.
Crystals are available in two types or modes of oscillation,
Series and Parallel. Series Mode crystals are manufactured
to operate at a specified frequency with zero load capaci-
tance and appear as a near resistive impedance when oscil-
lating. Parallel Mode crystals are manufactured to operate
with a specific capacitive load in series, causing the crystal
to operate at a more inductive impedance to cancel the load
capacitor. Loading a crystal with a different capacitance will
"pull" the frequency off its value.
The CDP6872 has 4 operating frequency ranges. The higher
three ranges do not add any loading capacitance to the
oscillator circuit. The lowest range, 10kHz to 100kHz, auto-
matically switches in two 15pF capacitors onto OSC IN and
OSC OUT to eliminate potential start-up problems. These
capacitors create an effective crystal loading capacitor equal
to the series combination of these two capacitors. For the
CDP6872, in the lowest range, the effective loading capaci-
tance is 7.5pF. Therefore the choice for a crystal, in this
range, should be a Parallel Mode crystal that requires a
7.5pF load.
In the higher 3 frequency ranges, the capacitance on OSC
IN and OSC OUT will be determined by package and layout
parasitics, typically 4 to 5pF. Ideally the choice for crystal
should be a Parallel Mode set for 2.5pF load. A crystal man-
ufactured for a different load will be "pulled" from its nominal
frequency (see Crystal Pullability).
FIGURE 2.
CDP6872
+
-
+5V
VREG
C
1
C
2
XTAL
C
3
2
OSC IN
3
OSC OUT
1
V
DD
Frequency Fine Tuning
Two Methods will be discussed for fine adjustment of the
crystal frequency. The first and preferred method (Figure 2),
provides better frequency accuracy and oscillator stability
than method two (Figure 3). Method one also eliminates
start-up problems sometimes encountered with 32kHz tun-
ing fork crystals.
For best oscillator performance, two conditions must be met:
the capacitive load must be matched to both the inverter and
crystal to provide ideal conditions for oscillation, and the fre-
quency of the oscillator must be adjustable to the desired
frequency. In Method two these two goals can be at odds
with each other; either the oscillator is trimmed to frequency
by de-tuning the load circuit, or stability is increased at the
expense of absolute frequency accuracy.
Method one allows these two conditions to be met indepen-
dently. The two fixed capacitors, C
1
and C
2
, provide the opti-
mum load to the oscillator and crystal. C
3
adjusts the
frequency at which the circuit oscillates without appreciably
changing the load (and thus the stability) of the system.
Once a value for C
3
has been determined for the particular
type of crystal being used, it could be replaced with a fixed
capacitor. For the most precise control over oscillator fre-
quency, C
3
should remain adjustable.
This three capacitor tuning method will be more accurate
and stable than method two and is recommended for 32kHz
tuning fork crystals; without it they may leap into an overtone
mode when power is initially applied.
Method two has been used for many years and may be pre-
ferred in applications where cost or space is critical. Note
that in both cases the crystal loading capacitors are con-
nected between the oscillator and V
DD
; do not use V
SS
as an
AC ground. The Simplified Block Diagram shows that the
oscillating inverter does not directly connect to V
SS
but is ref-
erenced to V
DD
and V
RN
. Therefore V
DD
is the best AC
ground available.
FIGURE 3.
CDP6872
+
-
+5V
VREG
C
1
C
2
XTAL
2
OSC IN
3
OSC OUT
1
V
DD
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