1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright
Intersil Corporation 1999
July 1998
CDP68HC68A2
CMOS Serial 10-Bit A/D Converter
Features
10-Bit Resolution
8-Bit Mode for Single Data Byte Transfers
SPI (Serial Peripheral Interface) Compatible
Operates Ratiometrically Referencing V
DD
or an
External Source
14
s 10-Bit Conversion Time
8 Multiplexed Analog Input Channels
Independent Channel Select
Three Modes of Operation
On Chip Oscillator
Low Power CMOS Circuitry
Intrinsic Sample and Hold
16 Lead Dual-In-Line Plastic Package
20 Lead Dual-In-Line Small Outline Plastic Package
Evaluation Board available - CDP68HC05C16BEVAL
Description
The CDP68HC68A2 is a CMOS 8-bit or 10-bit successive
approximation analog to digital converter (A/D) with a
standard Serial Peripheral Interface (SPI) bus and eight mul-
tiplexed analog inputs. Voltage referencing is user selectable
to be relative to either V
DD
or analog channel 0 (AI0). The
analog inputs can range between V
SS
and V
DD
.
The
CDP68HC68A2
employs
a
switched
capacitor,
successive approximation A/D conversion technique which
provides an inherent sample-and-hold function. An onchip
Schmitt oscillator provides the internal timing for the A/D
converter. The Schmitt input can be externally clocked or
connected to a single, external capacitor to form an RC
oscillator with a period of approximately 10-30ns per
picofarad.
Conversion times are proportional to the oscillator period. At
the
maximum
specified
frequency
of
1MHz,
10-bit
conversions take 14
s per channel. At the same frequency,
8-bit conversions consume 12
s per channel.
The versatile modes of the CDP68HC68A2 allow any
combination of the eight input channels to be enabled and
any one of the selected channels to be specified as the
"starting"
channel.
Conversions
proceed
sequentially
beginning with the starting channel. Nonselected channels
are skipped. Modes can be selected to: sequence from
channel to channel on command; sequence through
channels automatically, converting each channel one time;
or sequence repeatedly through all channels.
The results of 10-bit conversions are stored in 8-bit register
pairs (one pair per channel). The two most significant bits
are stored in the first register of each pair and the eight least
significant bits are stored in the second register of the pair.
To allow faster access, in the 8-bit mode, the results of
conversions are stored in a single register per channel.
A read-only STATUS register facilitates monitoring the
status of conversions. The STATUS register can simply be
polled or the INT pin can be enabled for interrupt driven
communications.
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
PKG.
NO.
CDP68HC68A2E
-40 to 85
16 Ld PDIP
E16.3
CDP68HC68A2M
-40 to 85
20 Ld SOIC
M20.3
File Number
1963.3
2
Block Diagram
Pinouts
CDP68HC58A2E
(PDIP)
TOP VIEW
CDP68HC68A2M
(SOIC)
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
OSC
INT
MISO
MOSI
SCK
CE
V
SS
AI0 / EXT. REF
V
DD
AI2
AI3
AI4
AI5
AI6
AI7
AI1
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
OSC
INT
MISO
MOSI
NC
NC
CE
SCK
AI0 / EXT. REF
V
SS
V
DD
AI2
AI3
NC
AI1
NC
AI4
AI5
AI6
AI7
SCK
V
SS
STATUS REGISTER
V
DD
SUCCESSIVE APPROXIMATION
CONTROL LOGIC
MOSI
MISO
SHIFT REGISTER
8
DATA REGISTERS (READ ONLY)
8
A/D CONVERTER LATCH
10
10-BIT CAPACITOR ARRAY
CAPACITOR SWITCH ARRAY
ANALOG MULTIPLEXER
8
REFERENCE
OSCILLATOR
12
INTERRUPT
LOGIC
INT
3
8
ACC LATCH COMPARATOR
CONTROL REGISTER
CAR
4
4
4
4
CHOPPER
STABILIZED
COMPARATOR
ANALOG INPUTS
AI7
AI0
3
ADDRESS REGISTER
CONTROL LOGIC
CE
SPI CONTROL LOGIC
6
6
3
STATUS
ADDRESS CONTROL
LOGIC
REGISTERS
CONTROL
REGISTERS
USED AS VOLTAGE INPUT IN
EXTERNAL REFERENCE MODE.
8
OSC
CDP68HC68A2
3
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage Range, (V
DD
) . . . . . . . . . . . . . . . . -0.5V to +7V
(Voltage Referenced to V
SS
Terminal)
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V
DD
+0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . . .
10mA
Operating Conditions
(Note 1)
Temperature Ambient, T
A
. . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
DC Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . 3V Min, 6V Max
Thermal Resistance (Typical, Note 2)
JA
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
104
Maximum Power Dissipation Per Package (P
D
)
T
A
= -40
o
C to 60
o
C (Package Type E). . . . . . . . . . . . . . . . 500mW
T
A
= 60
o
C to 85
o
C (Package Type E)
Derate Linearly at . . . . . . . . . . . . . . . . . . .12mW/
o
C to 200mW
T
A
= -40
o
C to 70
o
C (Package Type M) (Note 3) . . . . . . . . 400mW
T
A
= -70
o
C to 85
o
C (Package Type M) (Note 3)
Derate Linearly at . . . . . . . . . . . . . . . . . . 6.0mW/
o
C to 310mW
Device Dissipation Per Output Transistor . . . . . . . . . . . . . . . . 40mW
T
A
= Full Package Temperate Range (All Package Types)
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range (T
STG
) . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (During Soldering) . . . . . . . . . . 265
o
C
At Distance 1/16
1/32 In. (1.59
0.79mm)
From Case for 10s Max (SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. For maximum reliability, nominal operating conditions should be selected so that operation is always within the ranges specified.
2.
JA
is measured with the component mounted on an evaluation PC board in free air.
3. Printed circuit board mount: 58mm x 57mm minimum area x 1.6mm thick G10 epoxy glass, or equivalent.
Electrical Specification
T
A
= 25
o
C, V
DD
= 5V, Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ACCURACY
Differential Linearity Error
10-Bit Mode
-
1.25
2
LSB
Integral Linear Error
10-Bit Mode
-
1.25
2
LSB
Offset Error
10-Bit Mode
-1
3
4
LSB
Gain Error
10-Bit Mode
-1
1
2
LSB
ANALOG INPUTS: AI0 THRU AI7
Input Resistance
In Series with Sample Caps
-
85
-
Sample Capacitance
During Sample State
-
400
-
pF
Input Capacitance
During Hold State
-
20
-
pF
Input Current
At V
IN
= V
REF
+ During Sample
During Hold or Standby State
-
+30
-
A
-
-
1
A
Input + Full Scale Range
From Input RC Time Constant
VR = 1
V
SS
-
V
DD
+0.3
V
Input Bandwidth (3dB)
-
4.68
-
MHz
Input Voltage Range: AI0
3.0
-
V
DD
V
DIGITAL INPUTS: MOSI, SCK, CE, T
A
= -40
o
C to 85
o
C
High Input Voltage
V
IH
V
DD
= 3 to 6V
70
-
-
% of
V
DD
Low Input Voltage
V
IL
V
DD
= 3 to 6V
-
-
30
% of
V
DD
Input Leakage
-
-
1
A
Input Capacitance
T
A
= 25
o
C
-
-
10
pF
CDP68HC68A2
4
DIGITAL OUTPUTS: MISO, INT, T
A
= -40
o
C to 85
o
C
High Level Output
V
OH
, MISO
I
SOURCE
6mA
4.25
-
-
V
Low Level Output
V
OL
, MISO, INT
I
SINK
= 6mA
-
-
0.4
V
Three-State Output Leakage
I
OUT
, MISO, INT
-
-
10
A
TIMING PARAMETERS T
A
= -40
o
C to 85
o
C
Oscillator Frequency
f
SAMPLE
10-Bit Mode
-
-
-1
MHz
Conversion Time
(Including Sample Time)
10-Bit Mode
14 Oscillator Cycles
8-Bit Mode
12 Oscillator Cycles
Sample Time (Pre-Encode)
8 Time Constants (8
) Required
First 1.5 Oscillator
8
Serial Clock (SCK) Frequency
-
-
1.5
MHz
SCK Pulse Width
T
P
Either SCK
A
or SCK
B
150
-
-
ns
MOSI Setup Time
T
DSU
Prior to Leading Edge of T
P
60
-
-
ns
MOSI Hold Time
T
DH
After Leading Edge of T
P
60
-
-
ns
MISO Rise and Fall Time
200pF Load
-
-
100
ns
MISO Propagation Delay
T
DOD
From Trailing SCK Edge
-
-
100
ns
I
DD
V
DD
= 5V, Continuous Operation
-
1.4
2
mA
I
DD
V
DD
= 3V, Continuous Operation
-
0.7
1.2
mA
Electrical Specification
T
A
= 25
o
C, V
DD
= 5V, Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
CDP68HC68A2
5
Through this specification the CDP68HC68A2 is referred to
simply as the A2.
Functional Pin Description
OSC - Oscillator (Input/Output)
This pin is user programmable. In the "external" mode, the
clock input for the successive approximation logic is applied
to OSC from an external clock source. The input is a Schmitt
trigger input which provides excellent noise immunity. In the
"internal" mode, a capacitor is connected between this pin
and a power supply to form a "one pin oscillator". The
frequency of the oscillator is inversely dependent on the
capacitor value. Differences in period, from one device to
another, should be anticipated. Systems utilizing the internal
oscillator must be tolerant of uncertainties in conversion
times or provide trimming capability on the OSC capacitor.
See Table 2 for typical frequencies versus capacitance.
INT - Interrupt (Open Drain Output)
INT is used to signal the completion of an A/D conversion.
This output is generally connected, in parallel with a pullup
resistor, to the interrupt input of the controlling microproces-
sor. The open drain feature allows wire-NOR'ing with other
interrupt inputs. The inactive state of INT is high impedance.
When active, INT is driven to a low level output voltage. The
state of INT is controlled and monitored by bits in the Mode
Select and Status Registers.
MISO - Master-In-Slave-Out (Output)
Serial data is shifted out on this pin. Data is provided most
significant bit first.
MOSI - Master-Out-Slave-In (Input)
Serial data is shifted in on this pin. Data must be supplied
most significant bit first. This is a CMOS input and must be
held high or low at all times to minimize device current.
SCK - Serial Clock (Input)
Serial data is shifted out on MISO, synchronously, with each
leading edge of SCK. Input data from the MOSI pin is
latched, synchronously, with each trailing edge of SCK.
CE - Chip Enable (Input)
An active HIGH device enable. CE is used to synchronize
communications on the SPI lines (MOSI, MISO, and SCK).
When CE is held in a low state, the SPI logic is placed in a
reset mode with MISO held in a high impedance state.
Following a transition from low to high on CE, the
CDP68HC68A2 interprets the first byte transferred on the
SPI lines as an address. If CE is maintained high,
subsequent transfers are interpreted as data reads or writes.
AIO/EXT REF - Analog Input 0/External Reference (Input)
This input is one of eight analog input channels. Its function
is selectable through the Mode Select Register (MSR). If VR
is set high in the MSR, AI0/EXT REF provides an external
voltage reference against which all other inputs are
measured. AI0/EXT REF must fall within the V
SS
and V
DD
supply rails. If VR is set low in the MSR, V
DD
is used as the
reference voltage and AI0/EXT REF is treated as any other
analog input (see AI1-AI7).
AI1-AI7 - Analog Inputs 1-7 (Inputs)
Together with AI0/EXT REF, these pins provide the eight
analog inputs (channels) which are multiplexed within the
CDP68HC68A2 to a single, high-speed, successive approxi-
mation, A/D converter. AI1-AI7 must fall within the V
SS
and
V
DD
supply rails.
V
SS
- Negative Power Supply
This pin provides the negative analog reference and the
negative power supply for the CDP68HC68A2.
V
DD
- Positive Power Supply
This pin provides the positive power supply and, depending
on the value of the VR bit in the MSR, the positive analog
reference for the CDP68HC68A2.
Overview
From the programmer's perspective, the A2 is comprised of
three control registers (Mode Select Register - MSR,
Channel Select Register - CSR, and Starting Address
Register - SAR), a status register (SR), an array of eight
pairs of Data Registers, and one non-addressable, internal
register (Channel Address Register). See Figure 1.
The
A2
contains
a
high
speed,
10-bit,
successive
approximation, analog to digital converter (A/D). The input to
the A/D can be any one of the A2's eight analog inputs (AI0
through AI7). The contents of the CAR determine which ana-
log input is connected to the A/D. The result of each analog
to digital conversion is written to the Data Register array. The
Data Register array is also addressed by the contents of the
CAR, providing a one to one correspondence between each
analog input and each Data Register pair.
The contents of the CAR are also used during Data Register
reads to address the Data Register array. The CAR is
automatically jammed with the correct address when an
Address/Control Byte is sent to the A2. A second means, to
initialize the CAR, is by writing to the SAR.
Normal procedure for programming the A2 is to first select
the desired hardware mode by writing to the MSR. The
"active" analog channels are then specified by writing to the
CSR (channels not selected in the CSR are skipped during
conversions and burst mode reads). Finally, a write to the
SAR initializes the CAR (designating the first channel to
convert) and initiates the A/D conversions.
Polling of the SR or hardware interrupts can be used to
determine the completion of conversions.
The converted data is read from the data registers. In eight
bit mode, a single register is read for each channel of inter-
est. In ten bit mode, two registers are read per channel.
CDP68HC68A2
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