CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

Intersil Corporation 1999

August 1997

CDP68HC68T1

CMOS Serial Real-Time Clock With

RAM and Power Sense/Control

Features

· SPI (Serial Peripheral Interface)

· Full Clock Features

- Seconds, Minutes, Hours (12/24, AM/PM), Day of

Week, Date, Month, Year (0-99), Automatic Leap Year

· 32 Word x 8-Bit RAM

· Seconds, Minutes, Hours Alarm

· Automatic Power Loss Detection

· Low Minimum Standby (Timekeeping) Voltage . . . 2.2V

· Selectable Crystal or 50/60Hz Line Input

· Buffered Clock Output

· Battery Input Pin that Powers Oscillator and also

Connects to V

Pin When Power Fails

· Three Independent Interrupt Modes

- Alarm

- Periodic

- Power-Down Sense

Description

The CDP68HC68T1 Real-Time Clock provides a
time/calendar function, a 32 byte static RAM, and a 3 wire
Serial Peripheral Interface (SPI Bus). The primary function of
the clock is to divide down a frequency input that can be
supplied by the on-board oscillator in conjunction with an
external crystal or by an external clock source. The internal
oscillator can operate with a 32KHz, 1MHz, 2MHz, or 4MHz
crystal. An external clock source with a 32KHz, 1MHz,
2MHz, 4MHz, 50Hz or 60Hz frequency can be used to drive
the CDP68HC68T1. The time registers hold seconds,
minutes, and hours, while the calendar registers hold day-of-
week, date, month, and year information. The data is stored
in BCD format. In addition, 12 or 24 hour operation can be
selected. In 12 hour mode, an AM/PM indicator is provided.
The T1 has a programmable output which can provide one
of seven outputs for use elsewhere in the system.

Computer handshaking is controlled with a "wired-OR"
interrupt output. The interrupt can be programmed to provide
a signal as the result of: 1) an alarm programmed to occur at
a predetermined combination of seconds, minutes, and
hours; 2) one of 15 periodic interrupts ranging from sub-
second to once per day frequency; 3) a power fail detect.
The PSE output and the V

SYS

input are used for external

power control. The CPUR output is available to reset the
processor under power-down conditions. CPUR is enabled
under software control and can also be activated via the
CDP68HC68T1's watchdog. If enabled, the watchdog
requires a periodic toggle of the CE pin without a serial
transfer.

Pinouts

CDP68HC68T1 (PDIP, SBDIP, SOIC)

TOP VIEW

CDP68HC68T1 (SOIC)

TOP VIEW

Ordering Information

PART NUMBER

TEMP.

RANGE (

PACKAGE

PKG.

NO.

CDP68HC68T1E

-40 to 85

16 Ld PDIP

E16.3

CDP68HC68T1D

-40 to 85

16 Ld SBDIP

D16.3

CDP68HC68T1M

-40 to 85

20 Ld SOIC

M20.3

CDP68HC68T1M2

-40 to 85

16 Ld SOIC

M16.3

CDP68HC68T1W

-40 to 85

DIE

NOTE: Pin number references throughout this specification refer to
the 16 lead PDIP/SBDIP/SOIC. See pinouts for cross reference.

CLKOUT

CPUR

INT

SCK

MOSI

MISO

XTAL IN

BATT

SYS

XTAL OUT

LINE

POR

PSE

CLK OUT

CPUR

INT

SCK

MOSI

MISO

PSE

VDD

XTAL IN

BATT

XTAL OUT

SYS

LINE

POR

File Number

1547.3

Absolute Maximum Ratings

Thermal Information

Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V

Input Voltage, V

. . . . . . . . . . . . . . . . . . . . V

-0.3V to V

+0.3V

Current Drain Per Input Pin Excluding V

and V

, I . . . . . . 10mA

Current Drain Per Output Pin, I. . . . . . . . . . . . . . . . . . . . . . . . . 40mA

Operating Conditions

Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.0V to +6.0V
Standby (Timekeeping) Voltage . . . . . . . . . . . . . . . . +2.2V to +6.0V
Temperature Range

CDP68HC68T1D (SBDIP Package) . . . . . . . . . . . -55

C to 125

CDP68HC68T1E (PDIP Package) . . . . . . . . . . . . . -40

C to 85

CDP68HC68T1M/M2 (SOIC Packages) . . . . . . . . . -40

C to 85

Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . (0.7 x V

) to V

Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .0V to (0.3 x V

)

Serial Clock Frequency (f

SCK

) . . . . . . . . . . . . . . . . . +3.0V to +6.0V

Thermal Resistance (Typical, Note 1)

(

C/W)

(

C/W)

16 Ld PDIP . . . . . . . . . . . . . . . . . . . . .

N/A

16 Ld SOIC . . . . . . . . . . . . . . . . . . . . .

100

N/A

20 Ld SOIC . . . . . . . . . . . . . . . . . . . . .

100

N/A

16 Ld SBDIP . . . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature (Hermetic) . . . . . . . . . . . . . . . 175

Maximum Junction Temperature (Plastic) . . . . . . . . . . . . . . . 150

Maximum Storage Temperature Range (T

STG

) . . . .-65

C to 150

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300

(SOIC, Lead Tips Only)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on an evaluation PC board in free air.

Static Electrical Specifications

At T

= -40

C to +85

C, V

= V

BATT

= 5V

5%, except as noted.

PARAMETER

CONDITIONS

LIMITS

UNITS

CDP68HC68T1

MIN

(NOTE 2)

TYP

MAX

Quiescent Device Current

Output Voltage High Level

= -1.6mA, V

= 4.5V

3.7

Output Voltage Low Level

= 1.6mA, V

= 4.5V

0.4

Output Voltage High Level

A, V

= 4.5V

4.4

Output Voltage Low Level

A, V

= 4.5V

0.1

Input Leakage Current

Three-State Output Leakage Current

OUT

Operating Current (Note 3)

+ I

) V

= V

= 5V

Crystal Operation

32kHz

0.08

0.01

1MHz

0.5

0.6

2MHz

0.7

0.84

4MHz

1.2

Pin 14

External Clock (Squarewave) (Note 3)
(I

+ I

) V

= V

= 5V

32kHz

0.02

0.024

1MHz

0.1

0.12

2MHz

0.2

0.24

4MHz

0.4

0.5

Standby Current (Note 3)

= 3V

Crystal Operation

32kHz

1MHz

200

250

2MHz

300

360

4MHz

500

600

CDP68HC68T1

TABLE 1. CLOCK/CALENDAR AND ALARM DATA MODES

ADDRESS LOCATION

(H)

FUNCTION

DECIMAL RANGE

BCD DATA RANGE

(NOTE 4)

BCD DATE EXAMPLE

Seconds

0-59

00-59

Minutes

0-59

00-59

Hours

12 Hour Mode

(Note 5)

1-12

81-92 (AM)

A1-B2 (PM)

Hours

24 Hour Mode

0-23

00-23

Day of the Week

(Sunday = 1)

1-7

01-07

Day of the Month

(Date)

1-31

01-31

Month

Jan = 1, Dec = 12

1-12

01-12

Years

0-99

00-99

Alarm Seconds

0-59

00-59

Alarm Minutes

0-59

00-59

Alarm Hours (Note 6)

12 Hour Mode

1-12

01-12 (AM)
21-32 (PM)

Alarm Hours

24 Hour Mode

0-23

00-23

NOTES:

4. Example: 3:49:18, Tuesday. Oct. 29,1985.

5. Most significant Bit, D7, is "0" for 24 hours, and "1" for 12 hour mode. Data Bit D5 is "1" for P.M. and `0" for A.M. in 12 hour mode.

6. Alarm hours. Data Bit D5 is "1" for P.M. and "0" for A.M. in 12 hour mode. Data Bits D7 and D6 are DON'T CARE.

SECONDS

MINUTES

HOURS

DAY OF WEEK

DATE

MONTH

YEARS

NOT USED

SEC ALARM

MIN ALARM

HRS ALARM

NOT USED

STATUS REGISTER

CONTROL REGISTER

INTERRUPT CONTROL REGISTER

$20

$21

$22

$23

$24

$25

$26

$27

$28

$29

$2A

$2B

$2C

$2D

$2E

$2F

$30

$31

$32

CLOCK/CALENDAR

13 BYTES UNUSED

TEST MODE

32 RAM LOCATIONS

$00

$1F

$20

$32

$33

$3F

$55

R = READABLE

W = WRITABLE

R, W

FIGURE 2. ADDRESS MAP

CDP68HC68T1

Programmers Model - Clock Registers

NAME

WRITE/READ REGISTERS

HEX ADDRESS

TENS 0-5

12
HR
24

PM/AM
TENS 0-2

DB7

TENS 0-3

TENS 0-1

TENS 0-9

UNITS 0-9

UNITS 1-7

UNITS 0-9

WRITE ONLY REGISTERS

TENS 0-5

UNITS 0-9

PM/AM

TENS 0-2

DB0

SECONDS (00-59)

MINUTES (00-59)

DB7, 1 = 12 HR., 0 = 24 HR.

DB = 1 PM, 0 = AM

HOURS (01-12 OR 00-23

DATE

DAY OF MONTH

MONTH (01-12) JAN = 1

DEC = 12

YEARS (00-99)

CONTROL

INTERRUPT

ALARM SECONDS (00-59)

ALARM MINUTES (00-59)

ALARM HOURS (01-12 OR 00-23)

PLUS AM/PM IN 12 HR. MODE

PM = 1, AM = 0

READ ONLY REGISTERS

STATUS

BIT

HEX ADDRESS 00-1F

RAM DATA BYTE

01-28

29
30
31

NOTE: X = Don't care writes, X = 0 when read.

DAY OF WK (01-07) SUNDAY = 1

CDP68HC68T1

Functional Description

The SPI real-time clock consists of a clock/calendar and a
32 x 8 RAM. Communications is established via the SPI
(Serial Peripheral Interface) bus. In addition to the clock/cal-
endar data from seconds to years, and system flexibility pro-
vided by the 32-byte RAM, the clock features computer
handshaking with an interrupt output and a separate square-
wave clock output that can be one of 7 different frequencies.
An alarm circuit is available that compares the alarm latches
with the seconds, minutes and hours time counters and acti-
vates the interrupt output when they are equal. The clock is
specifically designed to aid in power-down/up applications
and offers several pins to aid the designer of battery backup
systems.

Mode Select

The voltage level that is present at the V

SYS

input pin at the

end of power-on-reset selects the device to be in the single
supply or battery backup mode.

Single-Supply Mode

If V

SYS

is a logic high when power-on-reset is completed,

CLK OUT, PSE and CPUR will be enabled and the device
will be completely operational. CPUR will be placed low if the
logic level at the V

SYS

pin goes low. If the output signals

CLK OUT, PSE and CPUR are disabled due to a power-
down instruction, V

SYS

brought to a logic low and then to a

logic high will re-enable these outputs. An example of the
single-supply mode is where only one supply is available
and V

, V

BATT

and V

SYS

are tied together to the supply.

Battery Backup Mode

If V

SYS

is a logic low at the end of power-on-reset, CLK

OUT, PSE and CPUR will be disabled (CLK OUT, PSE and
CPUR low). This condition will be held until V

SYS

rises to a

threshold (about 0.7V) above V

BATT

. The outputs CLK OUT,

PSE and CPUR will then be enabled and the device will be
operational. If V

SYS

falls below a threshold above V

BATT

the

outputs CLK OUT, PSE and CPUR will be disabled. An
example of battery backup operation occurs if V

SYS

is tied to

and V

is not connected to a supply when a battery is

connected to the V

BATT

pin. (See Pin Functions, V

BATT

for

Battery Backup Operation.)

Clock/Calendar (See Figure 1 and Figure 2)

The clock/calendar portion of this device consists of a long
string of counters that is toggled by a 1Hz input. The 1Hz
input is generated by a prescaler driven by an on-board
oscillator that utilizes one of four possible external crystals or
that can be driven by an external clock source. The 1Hz trig-
ger to the counters can also be supplied by a 50Hz or 60Hz
input source that is connected to the LINE input pin.

The time counters offer seconds, minutes and hours data in
12 hour or 24 hour format. An AM/PM indicator is available
that once set, toggles every 12 hours. The calendar counters
consist of day (day of week), date (day of month), month and
years information. Data in the counters is in BCD format.
The hours counter utilizes BCD for hour data plus bits for
12/24 hour and AM/PM. The 7 time counters are accessed
serially at addresses 20H through 26H. (See Table 1).

RAM

The real-time clock also has a static 32 x 8 RAM that is
located at addresses 00-1FH. Transmitting the address/con-
trol word with bit-5 low selects RAM access. Bits 0 through 4
select the RAM location.

Alarm

The alarm is set by accessing the three alarm latches and
loading the required data. The alarm latches consist of sec-
onds, minutes and hours registers. When their outputs equal
the values in the seconds, minutes and hours time counters,
an interrupt is generated. The interrupt output will go low if
the alarm bit in the Interrupt Control Register is set high. The
alarm interrupt bit in the Status Register is set when the
interrupt occurs (see Pin Functions, INT Pin). To preclude a
false interrupt when loading the time counters, the alarm
interrupt bit should be set low in the Interrupt Control Regis-
ter. This procedure is not required when the alarm time is
set.

Watchdog Function (See Figure 6)

When bit 7 in the Interrupt Control Register is set high, the
Clock's CE (chip enable) pin must be toggled at a regular
interval without a serial data transfer. If the CE is not toggled,
the clock will supply a CPU reset pulse and bit 6 in the Sta-
tus Register will be set. Typical service and reset times are
listed below.

Clock Out

The value in the 3 least significant bits of the Clock Control
Register selects one of seven possible output frequencies.
(See Clock Control Register). This squarewave signal is
available at the CLK OUT pin. When Power-Down operation
is initiated, the output is set low.

Control Registers and Status Registers

The operation of the Real-Time Clock is controlled by the
Clock Control and Interrupt Control Registers. Both registers
are Read-Write Registers. Another register, the Status Reg-
ister, is available to indicate the operating conditions. The
Status Register is a Read only Register.

Power Control

Power control is composed of two operations, Power Sense
and Power Down/Up. Two pins are involved in power sens-
ing, the LINE input pin and the INT output pin. Two additional
pins are utilized during power-down/up operation. They are
the PSE (Power Supply Enable) output pin and V

SYS

input

pin.

50Hz

60Hz

XTAL

MIN

MAX

MIN

MAX

MIN

MAX

Service Time

10ms

8.3ms

7.8ms

Reset Time

40ms

16.7

33.3ms

15.6

31.3ms

CDP68HC68T1

Power Sensing (See Figure 3)

When Power Sensing is enabled (Bit 5 = 1 in Interrupt Con-
trol Register), AC transitions are sensed at the LINE input pin.
Threshold detectors determine when transitions cease. After
a delay of 2.68ms to 4.64ms, plus the external input circuit RC
time constant, an interrupt is generated and a bit is set in the
Status Register. This bit can then be sampled to see if system
power has turned back on. See PIN FUNCTIONS, LINE PIN.
The power-sense circuitry operates by sensing the level of the
voltage presented at the line input pin. This voltage is cen-
tered around V

and as long as it is either plus or minus a

threshold (about 1V) from V

a power-sense failure will not

be indicated. With an AC signal present, remaining in this
V

window longer than a minimum of 2.68ms will activate

the power-sense circuit. The larger the amplitude of the AC
signal, the less time it spends in the V

window, and the less

likely a power failure will be detected. A 60Hz, 10V

P-P

sine-

wave voltage is an applicable signal to present at the LINE
input pin to setup the power sense function.

Power Down (See Figure 4)

Power down is a processor-directed operation. A bit is set in
the Interrupt Control Register to initiate operation. 3 pins are
affected. The PSE (Power Supply Enable) output, normally
high, is placed low. The CLK OUT is placed low. The CPUR
output, connected to the processors reset input is also
placed low. In addition, the Serial Interface is disabled.

Power Up (See Figure 5 and Figure 6)

Two conditions will terminate the Power-Down mode. The
first condition (See Figure 5) requires an interrupt. The inter-
rupt can be generated by the alarm circuit, the programma-
ble periodic interrupt signal, or the power sense circuit.

The second condition that releases Power Down occurs
when the level on the V

SYS

pin rises about 0.7V above the

level at the V

BATT

input, after previously falling to the level of

BATT

(See Figure 6) in the Battery Backup Mode or V

SYS

falls to logic low and returns high in the Single Supply Mode.

FIGURE 3. POWER-SENSING FUNCTIONAL DIAGRAM

FIGURE 4. POWER-DOWN FUNCTIONAL DIAGRAM

FIGURE 5. POWER-UP FUNCTIONAL DIAGRAM (INITIATED

BY INTERRUPT SIGNAL

XTAL IN

XTAL OUT

LINE

REAL-TIME CLOCK

CDP68HC68T1

STATUS REGISTER

INT

CPU

CDP68HC05C16B

SYS

INTERRUPT
CONTROL
REGISTER

SERIAL

INTERFACE

CLK

OUT

CPUR

REAL-TIME CLOCK
CDP68HC68T1

PSE

OSC

RESET

CPU

CDP68HC05C4B

MISO

MOSI

FROM SYSTEM
POWER

TO SYSTEM
POWER CONTROL

POWER

SENSE

ALARM

CIRCUIT

SERIAL

INTERFACE

PERIODIC

INTERRUPT

SIGNAL

POWER

REAL-TIME CLOCK
CDP68HC68T1

PSE

CPUR

CLK
OUT

INT

MISO

MOSI

CDP68HC68T1

CLK OUT

Clock output pin. One of seven frequencies can be selected
(or this output can be set low) by the levels of the three
LSB's in the Clock-Control Register. If a frequency is
selected, it will toggle with a 50% duty cycle except 2Hz in
the 50Hz time base mode. (Ex, if 1Hz is selected, the output
will be high for 500ms and low for the same period). During
power-down operation (bit 6 in Interrupt Control Register set
to "1"), the clock-output pin will be set low.

CPUR

CPU reset output pin. This pin functions as an N-Channel
only, open-drain output and requires an external pull-up
resistor.

INT

Interrupt output pin. This output is driven from a single NFET
pulldown transistor and must be tied to an external pull-up
resistor. The output is activated to a low level when:

1. Power-sense operation is selected (B5 = 1 in Interrupt

Control Register) and a power failure occurs.

2. A previously set alarm time occurs. The alarm bit in the

Status Register and interrupt-out signal are delayed
30.5

s when 32kHz operation is selected and 15.3

s for

2MHz and 7.6

s for 4MHz.

3. A previously selected periodic interrupt signal activates.

The Status Register must be read to set the Interrupt output
high after the selected periodic interval occurs. This is also
true when conditions 1 and 2 activate the interrupt. If power
down had been previously selected, the interrupt will also
reset the power-down functions.

SCK, MOSI, MISO

See Serial Peripheral Interface (SPI) section in this data sheet.

A positive chip-enable input. A low level at this input holds the
serial interface logic in a reset state. This pin is also used for
the watchdog function.

The negative power-supply pin that is connected to ground.

PSE

Power-supply enable output pin. This pin is used to control
power to the system. The pin is set high when:

1. V

SYS

rises above the V

BATT

voltage after V

SYS

was

placed low by a system failure.

2. An interrupt occurs.

3. A power-on reset (if V

SYS

is a logic high).

The PSE pin is set low by writing a high into bit 6 (power-
down bit) in the Interrupt Control Register.

POR

Power-on reset. A Schmitt-trigger input that generates a
power-on internal reset signal using an external R-C net-
work. Both control registers and frequency dividers for the
oscillator and line input are reset. The Status Register is
reset except for the first time up bit (B4), which is set.
Single supply or battery backup operation is selected at the
end of POR.

LINE

This input is used for two functions. When not used it
should be connected to V

via a 10k

resistor. The first

function utilizes the input signal as the frequency source for
the timekeeping counters. This function is selected by
setting bit 6 in the Clock Control Register. The second
function enables the line input to sense a power failure.
Threshold detectors operating above and below V

sense

an AC voltage loss. Bit 5 must be set to "1" in the Interrupt
Control Register and crystal or external clock source
operation is required. Bit 6 in the Clock Control Register
must be low to select XTAL operation.

Oscillator Circuit

The CDP68HC68T1 has an on-board 150K resistor that is
switched in series with its internal inverter when 32kHz is
selected via the Clock Control Register. Note: When first
powered up the series resistor is not part of the oscillator
circuit. (The CDP68HC68T1 sets up for a 4MHz oscillator).

MISO

BATT

REAL-TIME CLOCK

PSE

CPUR

CLK

OUT

SERIAL

INTERFACE

SYS

CDP68HC68T1

MOSI

FIGURE 6. POWER-UP FUNCTIONAL DIAGRAM (INITIATED BY

A RISE IN VOLTAGE ON THE "V

SYS

" PIN)

CDP68HC68T1

SYS

This input is connected to the system voltage. After the CPU
initiates power down by setting bit 6 in the Interrupt Control
Register to "1", the level on this pin will terminate power
down if it rises about 0.7V above the level at the V

BATT

input

pin after previously falling below V

BATT

+0.7V. When power

down is terminated, the PSE pin will return high and the
Clock Output will be enabled. The CPUR output pin will also
return high. The logic level present at this pin at the end of
POR determines the CDP68HC68T1's operating mode.

BATT

The oscillator power source. The positive terminal of the bat-
tery should be connected to this pin. When the level on the
V

SYS

pin falls below V

BATT

+0.7V, the V

BATT

pin will be

internally connected to the V

pin. When the voltage on

SYS

rises a threshold above (0.7V) the voltage on V

BATT

the connection from V

BATT

to the V

pin is opened. When

the "LINE" input is used as the frequency source, V

BATT

may

be tied to V

or V

. The "XTAL IN" pin must be at V

BATT

is at V

. If V

BATT

is connected to V

, the "XTAL

IN" pin can be tied to V

or V

XTAL IN, XTAL OUT

These pins are connected to a 32,768Hz. 1.048576MHz,
2.097152MHz or 4.194304MHz crystal. If an external clock
is used, it should be connected to "XTAL IN" with `XTAL
OUT" left open.

The positive power-supply pin.

Clock Control Register

START-STOP

A high written into this bit will enable the counter stages of
the clock circuitry. A low will hold all bits reset in the divider
chain from 32Hz to 1Hz. A clock out selected by bits 0, 1 and
2 will not be affected by the stop function except the 1Hz and
2Hz outputs.

LlNE-XTAL

When this bit is set high, clock operation will use the 50 or
60-cycle input present at the LINE input pin. When the bit is
low, the crystal input will generate the 1Hz time update.

XTAL Select

One of 4 possible crystals is selected by value in these two
bits:

0 = 4.194304MHz

2 = 1.048576MHz

1 = 2.097152MHz

3 = 32,768Hz

50-60Hz

50Hz is selected as the line input frequency when this bit is
set high. A low will select 60Hz. The power-sense bit in the
Interrupt Control Register must be set low for line frequency
operation.

Clock Out

The three bits specify one of the 7 frequencies to be used as
the squarewave clock output:

0 = XTAL

4 = Disable (low output)

1 = XTAL/2

5 = 1Hz

2 = XTAL/4

6 = 2Hz

3 = XTAL/8

7 = 50Hz or 60Hz
XTAL Operation = 64Hz

All bits are reset by a power-on reset. Therefore, the XTAL is
selected as the clock output at this time.

Interrupt Control Register

Watchdog

When this bit is set high, the watchdog operation will be
enabled. This function requires the CPU to toggle the CE pin
periodically without a serial-transfer requirement. In the
event this does not occur, a CPU reset will be issued. Status
Register must be read before re-enabling watchdog.

Power Down

A high in this location will initiate a power down. A CPU reset
will occur, the CLK OUT and PSE output pins will be set low
and the serial interface will be disabled.

XTAL

22M

XTAL

OUT

R (NO

TE 8)

YST

10 - 40pF

5 - 30pF

NOTES:

7. All frequencies recommended oscillator circuit. C1, C2 values

crystal dependent.

8. R used for 32KHz operation only. 100K - 300K range as specified

by crystal manufacturer.

FIGURE 7. OSCILLATOR CIRCUIT

CLOCK CONTROL REGISTER (Write/Read) - Address 31H

START

LINE

XTAL

50Hz

CLK OUT

SEL

STOP

XTAL

60Hz

CDP68HC68T1

Power Sense

This bit is used to enable the line input pin to sense a power
failure. It is set high for this function. When power sense is
selected, the input to the 50Hz to 60Hz prescaler is discon-
nected. Therefore, crystal operation is required when power
sense is enabled. An interrupt is generated when a power
failure is sensed and the power sense and Interrupt True bit
in the Status Register are set. When power sense is acti-
vated, a "0" must be written to this location followed by a "1"
to re-enable power sense.

Alarm

The output of the alarm comparator is enabled when this bit
is set high. When a comparison occurs between the sec-
onds, minutes and hours time and alarm counters, the inter-
rupt output is activated. When loading the time counters, this
bit should be set low to avoid a false interrupt. This is not
required when loading the alarm counters. See Pin Func-
tions, INT for explanation of alarm delay.

Periodic Select

The value in these 4 bits will select the frequency of the peri-
odic output. (See Table 2).

INTERRUPT CONTROL REGISTER (Write/Read) - Address 32H

WATCHDOG

POWER

DOWN

POWER

SENSE

ALARM

PERIODIC SELECT

NOTE: All bits are reset by power-on reset.

TABLE 2. PERIODIC INTERRUPT OUTPUT

D0 - D3 VALUE

PERIODIC INTERRUPT

OUTPUT FREQUENCY

FREQUENCY TIME BASE

XTAL

LINE

Disable

2048Hz

1024Hz

512Hz

256Hz

128Hz

64Hz

50 or 60Hz

32Hz

16Hz

8Hz

4Hz

2Hz

1Hz

Minute

Hour

Day

CDP68HC68T1

WATCHDOG

If this bit is set high, the watchdog circuit has detected a
CPU failure.

TEST MODE

When this bit is set high, the device is in the TEST MODE.

FIRST-TIME UP

Power-on reset sets this bit high. This signifies that data in
the RAM and Clock is not valid and should be initialized.

INTERRUPT TRUE

A high in this bit signifies that one of the three interrupts
(Power Sense, Alarm, and Clock) is valid.

POWER-SENSE INTERRUPT

This bit set high signifies that the power-sense circuit has
generated an interrupt.

ALARM INTERRUPT

When the seconds, minutes and hours time and alarm
counter are equal, this bit will be set high. Status Register
must be read before loading Interrupt Control Register for
valid alarm indication after alarm activates.

CLOCK INTERRUPT

A periodic interrupt will set this bit high.

All bits are reset by a power-on reset except the "FIRST-
TIME UP" which is set. All bits except the power-sense bit
are reset after a read of this register.

Pin Signal Description

SCK (Serial Clock Input, Note 11)

This input causes serial data to be latched from the MOSI
input and shifted out on the MISO output.

MOSI (Master Out/Slave In, Note 11)

Data bytes are shifted in at this pin, most significant bit
(MSB) first.

MISO (Master In/Slave Out)

Data bytes are shifted out at this pin, most significant bit
(MSB) first.

CE (Chip Enable, Note 12)

A positive chip-enable input. A low level at this input holds
the serial interface logic in a reset state, and disables the
output driver at the MISO pin.

NOTES:

11. These inputs will retain their previous state if the line driving

them goes into a High-Z state.

12. The CE input has as internal pull down device, if the input is in a

low state before going to High Z, the input can be left in a High Z.

Functional Description

The Serial Peripheral Interface (SPI) utilized by the
CDP68HC68T1 is a serial synchronous bus for address and
data transfers. The clock, which is generated by the micro-
computer is active only during address and data transfers. In
systems using the CDP68HC05C4 or CDP68HC05D2, the

STATUS REGISTER (Read Only) - Address 30H

WATCHDOG

TEST

MODE

FIRST

TIME

INTERRUPT

TRUE

POWER

SENSE

INTERRUPT

ALARM

INTERRUPT

CLOCK

INTERRUPT

TRUTH TABLE

MODE

SIGNAL

SCK (Note 9)

MOSI

MISO

DISABLE

RESET

INPUT DISABLED

HIGH Z

WRITE

CPOL = 1

CPOL = 0

DATA BIT LATCH

HIGH Z

READ

CPOL = 1

CPOL = 0

NEXT DATA BIT

SHIFTED OUT

(Note 10)

NOTES:

9. When interfacing to CDP68HC05 microcontrollers, serial clock phase bit, CPHA, must be set = 1 in the microcomputer's Control Register.

10. MISO remains at a high Z until 8-bits of data are ready to be shifted out during a READ. It remains at a high Z during the entire WRITE

cycle.

CDP68HC68T1

inactive clock polarity is determined by the CPOL bit in the
microcomputer's Control Register. A unique feature of the
CDP68HC68T1 is that it automatically determines the level
of the inactive clock by sampling SCK when CE becomes
active (see Figure 8). Input data (MOSI) is latched internally
on the internal strobe edge and output data (MISO) is shifted
out on the shift edge, as defined by Figure 8. There is one
clock for each data bit transferred (address, as well as data
bits are transferred in groups of 8).

Address And Data Format

There are three types of serial transfer:

1. Address Control - Figure 9.

2. READ or WRITE Data - Figure 10.

3. Watchdog Reset (actually a non-transfer) Figure 11.

The Address/Control and Data bytes are shifted MSB first,
Into the serial data input (MOSI) and out of the serial data
output (MISO).

Any transfer of data requires an Address/Control byte to
specify a Write or Read operation and to select a Clock or
RAM location, followed by one or more bytes of data.

Data is transferred out of MISO for a Read and into MOSI for
a Write operation.

Address/Control Byte - Figure 9

It is always the first byte received after CE goes true. To
transmit a new address, CE must first go false and then true
again. Bit 5 is used to select between Clock and RAM loca-
tions.

SHIFT

INTERNAL

STROBE

INTERNAL

STROBE

SHIFT

SCK

CPOL = 1

SCK

CPOL = 0

MOSI

MSB

MSB -1

NOTE: "CPOL" is a bit that is set in the microcomputer's Control
Register.

FIGURE 8. SERIAL RAM CLOCK (SCK) AS A FUNCTION OF

MCU CLOCK POLARITY (CPOL)

BIT

W/R

CLK RAM

A0-A4

Selects 5-Bit HEX Address of RAM or specifies Clock Register. Most Significant Address
Bit. If equal to "1", A0 through A4 selects a Clock Register. If equal to "0", A0 through A4
selects one of 32 RAM locations. Must be set to "0" when not in Test Mode 7W/R W/R = "1"
initiates one or more WRITE cycles.W/R = "0", initiates one or more READ cycles.

CLK RAM

W/R

NOTE: SCK can be either polarity.

FIGURE 9. ADDRESS/CONTROL BYTE-TRANSFER WAVEFORMS

CLOCK

W/R

MOSI

RAM

SCK (NOTE)

CDP68HC68T1

Read/Write Data (See Figure 10)

Read/Write data follows the Address/Control byte.

Watchdog Reset - (See Figure 11)

When watchdog operation is selected, CE must be toggled
periodically or a CPU reset will be outputted.

Address And Data

Data transfers can occur one byte at a time (Figure 12) or in
a multibyte burst mode (Figure 13). After the Real-Time
Clock enabled, an Address/Control word is sent to set the
CLOCK or RAM and select the type of operation (i.e., Read
or Write). For a single-byte Read or Write, one byte is trans-
ferred to or from the Clock Register or RAM location speci-
fied in the Address/Control byte and the Real-Time Clock is
then disabled. Write cycle causes the latched Clock Register
or RAM address to automatically increment. Incrementing
continues after each transfer until the device is disabled.
After incrementing to 1FH the address will "wrap" to 00H and
continue. Therefore, when the RAM is selected the address
will "wrap" to 00H and when the clock is selected the
address will "wrap" 20H.

BIT

SCK (NOTE)

MOSI

MISO

NOTE: SCK can be either polarity.

FIGURE 10. READ/WRITE DATA TRANSFER WAVEFORMS

SERVICE

TIME

SERVICE

TIME

SCK

CPUR

FIGURE 11. WATCHDOG OPERATION WAVEFORMS

CDP68HC68T1

NOTE: Example of a system in which the power is controlled by an external source. The LINE input pin can sense when the switch opens by use
of the POWER-SENSE INTERRUPT. The CDP68HC68T1 crystal drives the clock input to the CPU using the CLK OUT pin. On power down when
V

SYS

< V

BATT

+ 0.7V. V

BATT

will power the CDP68HC68T1. A threshold detect activates a P-Channel switch, connecting V

BATT

to V

. V

BATT

always supplies power to the oscillator, keeping voltage frequency variation to a minimum.

FIGURE 17. EXTERNALLY CONTROLLED POWER SYSTEM DIAGRAM

A Procedure for Power-Down Operation might consist of the following:

1. Set power sense operation by writing bit 5 high in the Interrupt Control Register.

2. When an interrupt occurs, the CPU reads the Status Register to determine the interrupt source.

3. Sensing a power failure, the CPU does the necessary housekeeping to prepare for shutdown.

4. The CPU reads the Status Register again after several milliseconds to determine validity of power failure.

5. The CPU sets power-down bit 6 and disables all interrupts in the Interrupt Control Register when power down is verified. This

causes the CPU reset and clock out to be held low and disconnects the serial interface.

6. When power returns and V

SYS

rises above V

BATT

, power down is terminated. The CPU reset is released and serial communi-

cation is established.

System Diagrams

(Continued)

POR

SYS

LINE

CDP68HC68T1

CPUR

MISO

MOSI

SCK

BATT

CLK OUT

INT

CDP68HC05C8B

PORT (e.g., PCO)

RESET

MISO

MOSI

SCK

OSC 1

IRQ

BRIDGE

GENERATOR

LINE

CDP68HC68T1

Example of an automotive system. The V

SYS

and LINE inputs can be used to sense the ignition turning on and off. An external

switch is included to activate the system without turning on the ignition. Also, the CMOS CPU is not powered down with the system
V

, but is held in a low power reset mode during power down. When restoring power the CDP68HC68T1 will enable the CLK

OUT pin and set the PSE and CPUR high.

Important Application Note: Those units with a code of 6PG have delayed alarm interrupts of 8.3ms regardless of
CDP68HC68T1's operating frequency. (See Pin Functions, INT.) In addition, reading the Status Register before delayed alarm acti-
vates will disable alarm signal.

FIGURE 19. AUTOMOTIVE SYSTEM DIAGRAM

System Diagrams

(Continued)

XTAL

LINE

SYS

BATT

POR

2MHz

PSE

CPUR

CLK OUT

SPI

INT

RESET

OSC1

IRQ

SPI

PORT

CDP68HC05C4B

PORT

REG

12V

IGNITION

CLOCK BUTTON

ENABLED POWER

CDP68HC68T1

CDP68HC68T1

Dual-In-Line Plastic Packages (PDIP)

SEATING

BASE

PLANE

-C-

0.010 (0.25)

B S

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English and

Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of

Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in JE-

DEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions.

Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and

are measured with the leads constrained to be perpendic-

ular to datum

7. e

and e

are measured at the lead tips with the leads unconstrained.

must be zero or greater.

8. B1 maximum dimensions do not include dambar protrusions. Dambar

protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,

E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

-C-

E16.3

(JEDEC MS-001-BB ISSUE D)

16 LEAD DUAL-IN-LINE PLASTIC PACKAGE

SYMBOL

INCHES

MILLIMETERS

NOTES

MIN

MAX

MIN

MAX

0.210

5.33

0.015

0.39

0.115

0.195

2.93

4.95

0.014

0.022

0.356

0.558

0.045

0.070

1.15

1.77

8, 10

0.008

0.014

0.204

0.355

0.735

0.775

18.66

19.68

0.005

0.13

0.300

0.325

7.62

8.25

0.240

0.280

6.10

7.11

0.100 BSC

2.54 BSC

0.300 BSC

7.62 BSC

0.430

10.92

0.115

0.150

2.93

3.81

Rev. 0 12/93

CDP68HC68T1

Ceramic Dual-In-Line Metal Seal Packages (SBDIP)

NOTES:

1. Index area: A notch or a pin one identification mark shall be locat-

ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer's identification shall not be used
as a pin one identification mark.

2. The maximum limits of lead dimensions b and c or M shall be

measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.

3. Dimensions b1 and c1 apply to lead base metal only. Dimension

M applies to lead plating and finish thickness.

4. Corner leads (1, N, N/2, and N/2+1) may be configured with a

partial lead paddle. For this configuration dimension b3 replaces
dimension b2.

5. Dimension Q shall be measured from the seating plane to the

base plane.

6. Measure dimension S1 at all four corners.

7. Measure dimension S2 from the top of the ceramic body to the

nearest metallization or lead.

8. N is the maximum number of terminal positions.

9. Braze fillets shall be concave.

10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

11. Controlling dimension: INCH.

bbb

C A - B

SEATING

BASE

PLANE

-D-

-A-

-C-

-B-

aaa

C A - B

ccc

C A - B

(c)

(b)

SECTION A-A

BASE

LEAD FINISH

METAL

A/2

D16.3

MIL-STD-1835 CDIP2-T16 (D-2, CONFIGURATION C)

16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE

SYMBOL

INCHES

MILLIMETERS

NOTES

MIN

MAX

MIN

MAX

0.200

5.08

0.014

0.026

0.36

0.66

0.014

0.023

0.36

0.58

0.045

0.065

1.14

1.65

0.023

0.045

0.58

1.14

0.008

0.018

0.20

0.46

0.008

0.015

0.20

0.38

0.840

21.34

0.220

0.310

5.59

7.87

0.100 BSC

2.54 BSC

0.300 BSC

7.62 BSC

eA/2

0.150 BSC

3.81 BSC

0.125

0.200

3.18

5.08

0.015

0.060

0.38

1.52

0.005

0.13

0.005

0.13

105

aaa

0.015

0.38

bbb

0.030

0.76

ccc

0.010

0.25

0.0015

0.038

Rev. 0 4/94

CDP68HC68T1

Small Outline Plastic Packages (SOIC)

INDEX
AREA

-B-

0.25(0.010)

C A

B S

-A-

-C-

SEATING PLANE

0.10(0.004)

h x 45

0.25(0.010)

NOTES:

1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of

Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension "D" does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.

4. Dimension "E" does not include interlead flash or protrusions. Interlead

flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. "L" is the length of terminal for soldering to a substrate.

7. "N" is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above

the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions are

not necessarily exact.

M16.3

(JEDEC MS-013-AA ISSUE C)

16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

SYMBOL

INCHES

MILLIMETERS

NOTES

MIN

MAX

MIN

MAX

0.0926

0.1043

2.35

2.65

0.0040

0.0118

0.10

0.30

0.013

0.0200

0.33

0.51

0.0091

0.0125

0.23

0.32

0.3977

0.4133

10.10

10.50

0.2914

0.2992

7.40

7.60

0.050 BSC

1.27 BSC

0.394

0.419

10.00

10.65

0.010

0.029

0.25

0.75

0.016

0.050

0.40

1.27

Rev. 0 12/93

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

Sales Office Headquarters

NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240

EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05

ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029

CDP68HC68T1

Small Outline Plastic Packages (SOIC)

INDEX
AREA

-B-

0.25(0.010)

C A

B S

-A-

-C-

SEATING PLANE

0.10(0.004)

h x 45

0.25(0.010)

NOTES:

1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of

Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension "D" does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.

4. Dimension "E" does not include interlead flash or protrusions. Interlead

flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. "L" is the length of terminal for soldering to a substrate.

7. "N" is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width "B", as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

M20.3

(JEDEC MS-013-AC ISSUE C)

20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

SYMBOL

INCHES

MILLIMETERS

NOTES

MIN

MAX

MIN

MAX

0.0926

0.1043

2.35

2.65

0.0040

0.0118

0.10

0.30

0.013

0.0200

0.33

0.51

0.0091

0.0125

0.23

0.32

0.4961

0.5118

12.60

13.00

0.2914

0.2992

7.40

7.60

0.050 BSC

1.27 BSC

0.394

0.419

10.00

10.65

0.010

0.029

0.25

0.75

0.016

0.050

0.40

1.27

Rev. 0 12/93

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