1
File Number
3115.4
DG201
CMOS Quad SPST Analog Switch
The DG201 solid state analog switch is designed using an
improved, high voltage CMOS monolithic technology. It
provides ease-of-use and performance advantages not
previously available from solid state switches. Destructive
latch-up of solid state analog gates have been eliminated by
Intersil's CMOS technology.
The DG201 is completely specification and pinout
compatible with the industry standard devices.
Functional Diagram
Features
Switches Greater than 28V
P-P
Signals with
15V Supplies
Break-Before-Make Switching
- t
OFF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns
- t
ON
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700ns
TTL, DTL, CMOS, PMOS Compatible
Non-Latching with Supply Turn-Off
Complete Monolithic Construction
Industry Standard (DG201)
Applications
Data Acquisition
Sample and Hold Circuits
Operational Amplifier Gain Switching Networks
Pinout
DG201 (PDIP)
TOP VIEW
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
PKG.
NO.
DG201CJ
0 to 70
16 Ld PDIP
E16.3
TRUTH TABLE
LOGIC
DG201
0
ON
1
OFF
N
P
IN
S
D
DG201 SWITCH CELL
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
IN
1
D
1
S
1
V-
GND
S
4
IN
4
D
4
IN
2
S
2
V+(SUBSTRATE)
V
REF
S
3
D
3
IN
3
D
2
SWITCHES SHOWN FOR LOGIC "1" INPUT
Data Sheet
January 2000
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Copyright
Intersil Corporation 2000
2
Functional Diagram
(
1
/
4
DG201)
Q
3
V
REF
INPUT
GATE
PROTECTION
RESISTOR
Q
4
V-
Q
7
V+
Q
8
Q
5
Q
10
Q
12
V+
Q
13
Q
11
D
1
S
1
Q
14
Q
6
V-
Q
9
Q
15
Q
1
Q
2
Pin Descriptions
PIN
SYMBOL
DESCRIPTION
1
IN
1
Logic Control for Switch 1
2
D
1
Drain (Output) Terminal for Switch 1
3
S
1
Source (Input) Terminal for Switch 1
4
V-
Negative Power Supply Terminal
5
GND
Ground Terminal (Logic Common)
6
S
4
Source (Input) Terminal for Switch 4
7
D
4
Drain (Output) Terminal for Switch 4
8
IN
4
Logic Control for Switch 4
9
IN
3
Logic Control for Switch 3
10
D
3
Drain (Output) Terminal for Switch 3
11
S
3
Source (Input) Terminal for Switch 3
12
V
REF
Logic Reference Voltage
13
V+
Positive Power Supply Terminal (Substrate)
14
S
2
Source (Input) Terminal for Switch 2
15
D
2
Drain (Output) Terminal for Switch 2
16
IN
2
Logic Control for Switch 2
DG201
3
Absolute Maximum Ratings
Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V
V+ to V
D
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V
V
D
to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V
V
D
to V
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28V
V
REF
to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33V
V
REF
to V
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V
V
REF
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
V
IN
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
Current (Any Terminal). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Operating Conditions
Temperature Range
"C" Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
JC
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
90
N/A
Maximum Junction Temperature
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
o
C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
T
A
= 25
o
C, V+ = +15V, V- = -15V
PARAMETER
TEST CONDITIONS
"C" SUFFIX
UNITS
0
o
C
(NOTE 2)
25
o
C
70
o
C
DYNAMIC CHARACTERISTICS
Turn-ON Time (Note 3), t
ON
R
L
= 1k
, V
ANALOG
= -10V to +10V (Figure 1)
-
1.0
-
s
Turn-OFF Time (Note 3), t
OFF
R
L
= 1k
, V
ANALOG
= -10V to +10V (Figure 1)
-
0.5
-
s
Charge Injection, Q
Figure 2
-
20 (Typ)
-
mV
Off Isolation Rejection Ratio, OIRR
f = 1MHz, R
L
= 100
, C
L
5pF, (Figure 3)
-
50 (Typ)
-
dB
Crosstalk (Channel-to-Channel), CCRR
One Channel Off
-
-50 (Typ)
-
dB
DIGITAL INPUT CHARACTERISTICS
Input Logic Current, I
IN(ON)
V
IN
= 0.8V (Note 3)
1
1
10
A
Input Logic Current, I
N(OFF)
V
IN
= 2.4V (Note 3)
1
1
10
A
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
-
15 (Typ)
-
V
Drain-Source ON Resistance, r
DS(ON)
I
S
= 10mA, V
ANALOG
=
10V
100
100
125
Channel-to-Channel
r
DS(ON)
Match, r
DS(ON)
-
30 (Typ)
-
Drain OFF Leakage Current, I
D(OFF)
V
ANALOG
= -14V to +14V
-
5
100
nA
Source OFF Leakage Current, I
S(OFF)
V
ANALOG
= -14V to +14V
-
5
100
nA
Channel ON Leakage
Current, I
D(ON)
+ I
S(ON)
V
D
= V
S
= -14V to +14V
-
5
200
nA
POWER SUPPLY CHARACTERISTICS
Supply Current, I+ Positive
V
IN
= 0V or V
IN
= 5V
2000
1000
2000
A
Supply Current, I- Negative
2000
1000
2000
A
NOTES:
2. Typical values are for design aid only, not guaranteed and not subject to production testing.
3. All channels are turned off by high "1" logic inputs and all channels are turned on by low "0" inputs; however 0.8V to 2.4V describes the minimum
range for switching properly. Peak input current required for transition is typically -120
A.
DG201
4
Typical Applications
Using the V
REF
Terminal
The DG201 has an internal voltage divider setting the TTL
threshold on the input control lines for V+ equal to +15V. The
schematic shown in Figure 4 with nominal resistor values,
gives approximately 2.4V on the V
REF
pin. As the TTL input
signal goes from +0.8V to +2.4V, Q
1
and Q
2
switch states to
turn the switch ON and OFF. If the power supply voltage is
less than +15V, then a resistor (R
EXT
) must be added
between V+ and the V
REF
pin, to restore +2.4V at V
REF
.
The table shows the value of this resistor for various supply
voltages, to maintain TTL compatibility. If CMOS logic levels
with a +5V supply are being used, the threshold shifts are
less critical, but a separate column of suitable values is given
in the table. For logic swings of -5V to + 5V, no resistor is
needed.
In general, the "low" logic level should be <0.8V to prevent
Q
1
and Q
2
from both being ON together (this will cause
incorrect switch function).
Test Circuits
FIGURE 1. t
ON
AND t
OFF
TEST CIRCUIT
FIGURE 2. CHARGE INJECTION TEST CIRCUIT
FIGURE 3. OFF ISOLATION TEST CIRCUIT
0V
3V
LOGIC
INPUT
ANALOG
INPUT 10V
10pF
V
OUT
1k
0V
3V
LOGIC
INPUT
ANALOG
INPUT 10V
10nF
V
OUT
V
OUT
100
2V
P-P
AT 1MHz
LOGIC
INPUT
51
ANALOG INPUT
3V
TABLE 1.
V+ SUPPLY (V)
R
EXT
FOR TTL
LEVELS (k
)
R
EXT
FOR CMOS
LEVELS (k
)
+15
-
-
+12
420
-
+10
190
-
+9
136
136
+8
98
98
+7
70
70
V+
Q
1
118k
V
REF
23k
R
EXT
Q
2
GATE
PROTECTION
RESISTOR
INPUT
FIGURE 4.
DG201
5
Typical Performance Curves
FIGURE 5. r
DS(ON)
vs V
D
AND TEMPERATURE
FIGURE 6. r
DS(ON)
vs V
D
AND POWER SUPPLY VOLTAGE
FIGURE 7. I
D(ON)
vs TEMPERATURE
FIGURE 8. I
S(OFF)
OR I
D(OFF)
vs TEMPERATURE
100
50
0
-15
-10
-5
0
5
10
15
DRAIN-SOURCE ON RESIST
ANCE (
)
DRAIN VOLTAGE (V)
125
o
C
25
o
C
-55
o
C
V+ = +15V
V- = -15V
100
50
0
-15
-10
-5
0
5
10
15
DRAIN-SOURCE ON RESIST
ANCE (
)
DRAIN VOLTAGE (V)
A
B
C
D
A: V+ = +15V, V- = -15V
B: V+ = +12V, V- = -12V
C: V+ = +10V, V- = -10V
D: V+ = +8V, V- = -8V
10
1
0.1
0.01
CHANNEL ON LEAKA
GE CURRENT (nA)
25
45
65
85
105
125
TEMPERATURE (
o
C)
10
1
0.1
0.01
SOURCE OR DRAIN OFF LEAKA
GE
25
45
65
85
105
125
TEMPERATURE (
o
C)
CURRENT (nA)
DG201
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