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Электронный компонент: DG406DY

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1
File Number
3116.5
DG406, DG407
Single 16-Channel/Differential 8-Channel,
CMOS Analog Multiplexers
The DG406 and DG407 monolithic CMOS analog
multiplexers are drop-in replacements for the popular
DG506A and DG507A series devices. They each include an
array of sixteen analog switches, a TTL and CMOS
compatible digital decode circuit for channel selection, a
voltage reference for logic thresholds, and an ENABLE input
for device selection when several multiplexers are present.
These multiplexers feature lower signal ON resistance
(<100
) and faster transition time (t
TRANS
< 300ns)
compared to the DG506A and DG507A. Charge injection
has been reduced, simplifying sample and hold applications.
The improvements in the DG406 series are made possible
by using a high voltage silicon-gate process. An epitaxial
layer prevents the latch-up associated with older CMOS
technologies. The 44V maximum voltage range permits
controlling 30V
P-P
signals when operating with
15V power
supplies.
The sixteen switches are bilateral, equally matched for AC or
bidirectional signals. The ON resistance variation with
analog signals is quite low over a
5V analog input range.
Features
ON-Resistance (Max) . . . . . . . . . . . . . . . . . . . . . . . . 100
Low Power Consumption (P
D
) . . . . . . . . . . . . . . <1.2mW
Fast Transition Time (Max) . . . . . . . . . . . . . . . . . . . . 300ns
Low Charge Injection
TTL, CMOS Compatible
Single or Split Supply Operation
Applications
Battery Operated Systems
Data Acquisition
Medical Instrumentation
Hi-Rel Systems
Communication Systems
Automatic Test Equipment
Ordering Information
PART
NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG. NO.
DG406DJ
-40 to 85
28 Ld PDIP
E28.6
DG406DY
-40 to 85
28 Ld SOIC
M28.3
DG407DJ
-40 to 85
28 Ld PDIP
E28.6
DG407DY
-40 to 85
28 Ld SOIC
M28.3
DG407DN
-40 to 85
28 Ld PLCC
N28.45
Data Sheet
June 1999
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
2
Pinouts
DG406 (PDIP, SOIC)
TOP VIEW
DG407 (PDIP, SOIC)
TOP VIEW
DG407 (PLCC)
TOP VIEW
V+
NC
NC
S
16
S
15
S
14
S
13
S
12
S
11
S
10
S
9
GND
NC
A
3
D
S
8
S
7
S
6
S
5
S
3
S
1
EN
A
0
A
1
A
2
V-
S
4
S
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
V+
D
B
NC
S
8B
S
7B
S
6B
S
5B
S
4B
S
3B
S
2B
S
1B
GND
NC
NC
D
A
S
8A
S
7A
S
6A
S
5A
S
3A
S
1A
EN
A
0
A
1
A
2
V-
S
4A
S
2A
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
NC
A
2
A
1
A
0
ENABLE
GND
NC
D
B
+V
SUPPL
Y
D
A
-V
SUPPL
Y
S
8A
S
8B
NC
S
6A
S
5A
S
4A
S
3A
S
7A
S
1A
S
2A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
S
6B
S
5B
S
4B
S
3B
S
7B
S
1B
S
2B
DG406, DG407
3
Schematic Diagram
(Typical Channel)
Functional Diagrams
DG406
DG407
V+
GND
A
0
A
X
EN
V-
V
REF
LEVEL
SHIFT
DECODE/
DRIVE
V+
V+
V-
D
S
1
S
N
S
1
S
2
S
3
S
4
S
5
S
6
S
7
S
8
S
9
S
10
S
11
S
12
S
13
S
14
S
15
S
16
D
TO DECODER LOGIC
CONTROLLING BOTH
TIERS OF MUXING
ADDRESS DECODER
1 OF 16
ENABLE
A
0
A
1
A
2
A
3
EN
S
2A
S
3A
S
4A
S
5A
S
6A
S
7A
S
8A
S
1B
S
2B
S
3B
S
4B
S
5B
S
6B
S
7B
S
8B
D
A
TO DECODER LOGIC
CONTROLLING BOTH
TIERS OF MUXING
ADDRESS DECODER
1 OF 8
ENABLE
A
0
A
1
A
2
EN
S
1A
D
B
DG406, DG407
4
DG406 TRUTH TABLE
A
3
A
2
A
1
A
0
EN
ON SWITCH
X
X
X
X
0
None
0
0
0
0
1
1
0
0
0
1
1
2
0
0
1
0
1
3
0
0
1
1
1
4
0
1
0
0
1
5
0
1
0
1
1
6
0
1
1
0
1
7
0
1
1
1
1
8
1
0
0
0
1
9
1
0
0
1
1
10
1
0
1
0
1
11
1
0
1
1
1
12
1
1
0
0
1
13
1
1
0
1
1
14
1
1
1
0
1
15
1
1
1
1
1
16
DG407 TRUTH TABLE
A
2
A
1
A
0
EN
ON SWITCH PAIR
X
X
X
0
None
0
0
0
1
1
0
0
1
1
2
0
1
0
1
3
0
1
1
1
4
1
0
0
1
5
1
0
1
1
6
1
1
0
1
7
1
1
1
1
8
Logic "0" = V
AL
< 0.8V.
Logic "1" = V
AH
> 2.4V.
X = Don't Care.
DG406, DG407
5
Absolute Maximum Ratings
Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0V
GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
Digital Inputs, V
S
, V
D
(Note 1). . . . . . (V-) -2V to (V+) +2V or 20mA,
Whichever Occurs First
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA
Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . . . . 100mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Thermal Resistance (Typical, Note 2)
JA
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(PLCC and SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Signals on S
X
, D
X
, EN or A
X
exceeding V+ or V- are clamped by internal diodes. Limit diode current to maximum current ratings.
2.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Test Conditions: V+ = +15V, V- = -15V, V
AL
= 0.8V, V
AH
= 2.4V Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
TEMP (
o
C)
(NOTE 3)
MIN
(NOTE 4)
TYP
(NOTE 3)
MAX
UNITS
DYNAMIC CHARACTERISTICS
Transition Time, t
TRANS
(See Figure 1)
25
-
200
300
ns
Full
-
-
400
ns
Break-Before-Make Interval, t
OPEN
(See Figure 3)
25
25
50
-
ns
Full
10
-
-
ns
Enable Turn-ON Time, t
ON(EN)
(See Figure 2)
25
-
150
200
ns
Full
-
-
400
ns
Enable Turn-OFF Time, t
OFF(EN)
25
-
70
150
ns
Full
-
-
300
ns
Charge Injection, Q
C
L
= 1nF, V
S
= 0V, R
S
= 0
25
-
40
-
pC
OFF Isolation, OIRR
V
EN
= 0V, R
L
= 1k
,
f = 100kHz (Note 7)
25
-
-69
-
dB
Logic Input Capacitance, C
IN
f = 1MHz
25
-
7
-
pF
Source OFF Capacitance, C
S(OFF)
V
EN
= 0V, V
S
= 0V,
f = 1MHz
25
-
8
-
pF
Drain OFF Capacitance, C
D(OFF)
V
EN
= 0V, V
D
= 0V,
f = 1MHz
DG406
25
-
160
-
pF
DG407
25
-
80
-
pF
Drain ON Capacitance, C
D(ON)
V
EN
= 5V, V
D
= 0V,
f = 1MHz
DG406
25
-
180
-
pF
DG407
25
-
90
-
pF
DIGITAL INPUT CHARACTERISTICS
Logic High Input Voltage, V
INH
Full
2.4
-
-
V
Logic Low Input Voltage, V
INL
Full
-
-
0.8
V
Logic High Input Current, I
AH
V
A
= 2.4V, 15V
Full
-1
-
1
A
Logic Low Input Current, I
AL
V
EN
= 0V, 2.4V, V
A
= 0V
Full
-1
-
1
A
DG406, DG407