1
File Number
3281.5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright Intersil Corporation 1999
DG441, DG442
Monolithic, Quad SPST, CMOS Analog
Switches
The DG441 and DG442 monolithic CMOS analog switches
are drop-in replacements for the popular DG201A and
DG202 series devices. They include four independent single
pole single throw (SPST) analog switches, TTL and CMOS
compatible digital inputs, and a voltage reference for logic
thresholds.
These switches feature lower analog ON resistance (<85
)
and faster switch time (t
ON
< 250ns) compared to the
DG201A and DG202. Charge injection has been reduced,
simplifying sample and hold applications.
The improvements in the DG441 series are made possible by
using a high voltage silicon-gate process. An epitaxial layer
prevents the latch-up associated with older CMOS
technologies. The 44V maximum voltage range permits
controlling 40V
P-P
signals. Power supplies may be single-
ended from +5V to +34V, or split from
5V to
20V.
The four switches are bilateral, equally matched for AC or
bidirectional signals. The ON resistance variation with
analog signals is quite low over a
5V analog input range.
The switches in the DG441 and DG442 are identical,
differing only in the polarity of the selection logic.
Pinout
DG441, DG442
(PDIP, SOIC)
TOP VIEW
Features
ON Resistance (Max) . . . . . . . . . . . . . . . . . . . . . . . . . 85
Low Power Consumption (P
D
) . . . . . . . . . . . . . . . <1.6mW
Fast Switching Action
- t
ON
(Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns
- t
OFF
(Max, DG441). . . . . . . . . . . . . . . . . . . . . . . . 120ns
Low Charge Injection
Upgrade from DG201A/DG202
TTL, CMOS Compatible
Single or Split Supply Operation
Applications
Audio Switching
Battery Operated Systems
Data Acquisition
Hi-Rel Systems
Sample and Hold Circuits
Communication Systems
Automatic Test Equipment
Functional Diagrams
Ordering Information
PART
NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
PKG. NO.
DG441DJ
-40 to 85
16 Ld PDIP
E16.3
DG441DY
-40 to 85
16 Ld SOIC
M16.15
DG442DJ
-40 to 85
16 Ld PDIP
E16.3
DG442DY
-40 to 85
16 Ld SOIC
M16.15
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
IN
1
D
1
S
1
V-
GND
S
4
IN
4
D
4
IN
2
S
2
V+
NC
S
3
D
3
IN
3
D
2
TRUTH TABLE
LOGIC
V
IN
DG441
DG442
0
0.8V
ON
OFF
1
2.4V
OFF
ON
S
1
D
1
S
2
D
2
S
3
D
3
S
4
D
4
IN
1
DG441
IN
2
IN
3
IN
4
IN
1
DG442
IN
2
IN
3
IN
4
S
1
D
1
S
2
D
2
S
3
D
3
S
4
D
4
SWITCHES SHOWN FOR LOGIC "1" INPUT
Data Sheet
June 1999
2
Schematic Diagram
(One Channel)
Pin Descriptions
PIN
SYMBOL
DESCRIPTION
1
IN
1
Logic Control for Switch 1
2
D
1
Drain (Output) Terminal for Switch 1
3
S
1
Source (Input) Terminal for Switch 1
4
V-
Negative Power Supply Terminal
5
GND
Ground Terminal (Logic Common)
6
S
4
Source (Input) Terminal for Switch 4
7
D
4
Drain (Output) Terminal for Switch 4
8
IN
4
Logic Control for Switch 4
9
IN
3
Logic Control for Switch 3
10
D
3
Drain (Output) Terminal for Switch 3
11
S
3
Source (Input) Terminal for Switch 3
12
NC
No Internal Connection
13
V+
Positive Power Supply Terminal (Substrate)
14
S
2
Source (Input) Terminal for Switch 2
15
D
2
Drain (Output) Terminal for Switch 2
16
IN
2
Logic Control for Switch 2
S
D
V+
IN
X
GND
V-
V-
V+
1 PER DIE COMMON TO
EVERY CHANNEL
DG441, DG442
3
Absolute Maximum Ratings
Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0V
GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
Digital Inputs, V
S
, V
D
(Note 1) . . . . . (V-) -2V to (V+) + 2V or 30mA,
Whichever Occurs First
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA
Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . 100mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20V (Max)
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V (Max)
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V (Min)
Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20ns
Thermal Resistance (Typical, Note 2)
JA
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
115
Maximum Junction Temperature (Plastic Packages) . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Signals on S
X
, D
X
or IN
X
exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
2.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
(Dual Supply) Test Conditions: V+ = +15V, V- = -15V, V
IN
= 2.4V, 0.8V, V
ANALOG
= V
S
, V
D
,
Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
TEMP
(
o
C)
MIN
(NOTE 3)
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
ON
R
L
= 1k
, C
L
= 35pF, V
S
=
10V, (Figure 1)
25
-
150
250
ns
Turn-OFF Time, t
OFF
DG441
25
-
90
120
ns
DG442
-
110
210
ns
Charge Injection, Q (Figure 2)
C
L
= 1nF, V
G
= 0V, R
G
= 0
25
-
-1
-
pC
OFF Isolation (Figure 4)
R
L
= 50
, C
L
= 5pF, f = 1MHz
25
-
60
-
dB
Crosstalk (Channel-to-Channel) (Figure 3)
25
-
-100
-
dB
Source OFF Capacitance, C
S(OFF)
f = 1MHz, V
ANALOG
= 0 (Figure 5)
25
-
4
-
pF
Drain OFF Capacitance, C
D(OFF)
25
-
4
-
pF
Channel ON Capacitance,
C
D(ON)
+ C
S(ON)
25
-
16
-
pF
DIGITAL INPUT CHARACTERISTICS
Input Current V
IN
Low, I
IL
V
IN
Under Test = 0.8V, All Others = 2.4V
Full
-0.5
-0.00001
0.5
A
Input Current V
IN
High, I
IH
V
IN
Under Test = 2.4V, All Others = 0.8V
Full
-0.5
0.00001
0.5
A
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
-15
-
15
V
Drain-Source ON Resistance, r
DS(ON
)
I
S
=
10mA, V
D
=
8.5V, V+ = 13.5V,
V- = -13.5V
25
-
50
85
85
-
-
100
Source OFF Leakage Current, I
S(OFF)
V+ = 16.5V, V- = -16.5V, V
D
=
15.5V,
V
S
=
15.5V
25
-0.5
0.01
0.5
nA
85
-5
-
5
nA
Drain OFF Leakage Current, I
D(OFF)
25
-0.5
0.01
0.5
nA
85
-5
-
5
nA
Channel ON Leakage Current,
I
D(ON)
+ I
S(ON)
V+ = 16.5V, V- = -16.5V, V
S
= V
D
=
15.5V
25
-0.5
0.08
0.5
nA
85
-10
-
10
nA
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = 16.5V, V- = -16.5V, V
IN
= 0V or 5V
Full
-
15
100
A
Negative Supply Current, I-
25
-1
-0.0001
-
A
Full
-5
-
-
A
Ground Current, I
GND
Full
-100
-15
-
A
DG441, DG442
4
Electrical Specifications
(Single Supply) Test Conditions: V+ = 12V, V- = 0V, V
IN
= 2.4V, 0.8V, Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
TEMP
(
o
C)
MIN
(NOTE 3)
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
ON
R
L
= 1k
, C
L
= 35pF, V
S
= 8V, (Figure 1)
25
-
300
450
ns
Turn-OFF Time, t
OFF
25
-
60
200
ns
Charge Injection, Q (Figure 2)
C
L
= 1nF, V
G
= 6V, R
G
= 0
25
-
2
-
pC
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
0
-
12
V
Drain-Source ON Resistance,
r
DS(ON)
I
S
= 10mA, V
D
= 3V, 8V V+ = 10.8V
25
-
100
160
Full
-
-
200
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = 13.2V, V- = 0V, V
IN
= 0V or 5V
Full
-
15
100
A
Negative Supply Current, I-
25
-1
-0.0001
-
A
Full
-100
-0.0001
-
A
Ground Current, I
GND
Full
-100
-15
-
A
NOTES:
3. Typical values are for DESIGN AID ONLY, not guaranteed nor production tested.
Test Circuits and Waveforms
V
O
is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing
edge of the output waveform.
NOTE: Logic input waveform is inverted for switches that have the
opposite logic sense.
FIGURE 1A. MEASUREMENT POINTS
Repeat test for Channels 2, 3 and 4.
For load conditions, see Specifications. C
L
includes fixture and stray
capacitance.
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
50%
t
r
< 20ns
t
f
< 20ns
t
OFF
80%
3V
0V
V
S
0V
t
ON
V
O
LOGIC
INPUT
SWITCH
INPUT
SWITCH
OUTPUT
80%
SWITCH
INPUT
LOGIC
INPUT
S
1
IN
1
3V
V+
D
1
R
L
C
L
V
O
GND
V-
V
O
V
S
R
L
R
L
r
DS ON
(
)
+
------------------------------------
=
DG441, DG442
5
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
FIGURE 3. CROSSTALK TEST CIRCUIT
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. SOURCE/DRAIN CAPACITANCES TEST CIRCUIT
Test Circuits and Waveforms
(Continued)
SWITCH
V
O
IN
X
OFF
ON
IN
X
OFF
OFF
OFF
ON
Q =
V
O
x C
L
(DG441)
(DG442)
OUTPUT
V+
D
1
C
L
V
O
GND
V-
V
IN
= 3V
R
G
V
G
0V, 2.4V
ANALYZER
+15V
V+
C
V
S
10dBm
SIGNAL
GENERATOR
R
L
GND
IN
1
V
D
IN
2
50
0V, 2.4V
NC
V-
-15V
C
V
D
ANALYZER
R
L
+15V
10dBm
SIGNAL
GENERATOR
V+
C
V-
-15V
C
0V, 2.4V
V
S
V
D
IN
X
GND
+15V
V+
C
GND
V
S
V
D
IN
X
V-
-15V
C
IMPEDANCE
ANALYZER
f = 1MHz
0V, 2.4V
DG441, DG442
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