File Number

4153.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Intersil Corporation 1999

HA456

120MHz, Low Power, 8 x 8 Video
Crosspoint Switch

The HA456 is the first 8 x 8 video crosspoint switch suitable
for high performance video systems. Its high level of
integration significantly reduces component count, board
space, and cost. The crosspoint switch contains a digitally
controlled matrix of 64 fully buffered switches that connect
eight video input signals to any, or all, matrix outputs. Each
matrix output connects to an internal, high-speed (200V/

s),

unity gain buffer capable of driving 400

and 5pF to

2V.

For applications requiring gain or increased drive capability,
the HA456 outputs can be connected directly to two
HFA1412 quad, gain of two video buffers, which are capable
of driving 75

loads.

This crosspoint's true high impedance three-state output
capability, makes it feasible to parallel multiple HA456s and
form larger switch matrices.

Features

· Fully Buffered Inputs and Outputs (A

= +1)

· Routes Any Input Channel to Any Output Channel

· Switches Standard and High Resolution Video Signals

· Serial or Parallel Digital Interface

· Expandable for Larger Switch Matrices

· Wide Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . 120MHz

· High Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . 200V/

· Differential Gain and Phase . . . . . . . 0.05%, 0.05 Degrees

· Low Crosstalk at 10MHz . . . . . . . . . . . . . . . . . . . . . -55dB

Applications

· Professional Video Switching and Routing

· Security and Video Editing Systems

Ordering Information

PART NUMBER

TEMP.

RANGE (

PACKAGE

PKG. NO.

HA456CN

0 to 70

44 Ld MQFP

Q44.10x10

HA456CM

0 to 70

44 Ld PLCC

N44.65

Pinouts

HA456 (MQFP)

TOP VIEW

HA456 (PLCC)

TOP VIEW

10
11

12 13 14 15 16 17

39 38 37 36 35 34

44 43 42 41 40

IN0

D0/SER IN

D1/SER OUT

V+

OUT0

OUT1

IN1

IN2

DGND

IN3

DGND

IN4

EDGE/LEVEL

IN5

OUT2

V-

OUT3

AGND

OUT4

AGND

OUT5

AGND

OUT6

V+

IN6

SER/

IN7

V-

TCH

OUT7

44 43 42 41 40

IN1

IN2

DGND

IN3

DGND

IN4

EDGE/LEVEL

IN5

IN0

D0/SER IN

D1/SER OUT

V+

OUT0

OUT1

V+

IN6

SER/

IN7

V-

TCH

OUT7

OUT2
V-
OUT3

AGND
OUT4
NC

AGND
OUT5
AGND

OUT6
V+

Data Sheet

August 1999

Pin Description

PIN

NAME

FUNCTION

MQFP

PLCC

3, 6, 17, 28, 39

1, 9, 12, 23, 34

No connect. Not internally connected.

D1/ SER OUT

Parallel Data Bit input D1 for Parallel Programming Mode. Serial Data Output (MSB of shift
register) for cascading multiple HA456s in serial programming mode. Simply connect
Serial Data Out of one HA456 to Serial Data In of another HA456 to daisy chain multiple
devices.

D0/SER IN

Parallel Data Bit Input D0 for Parallel Programming Mode. Serial Data Input (input to shift
register) for serial programming mode.

42, 43, 1

4, 5, 7

A2, A1, A0

Output Channel Address Bits. These inputs select the output being programmed in parallel
programming mode.

44, 2, 4, 7, 9, 11,

13, 15

6, 8, 10, 13,

15, 17, 19, 21

IN0-IN7

Analog Video Input Lines.

5, 8

11, 14

DGND

Digital Ground. Connect both DGND pins to AGND.

EDGE/LEVEL

A user strapped input that defines whether synchronous channel switching is edge or level
controlled. With this pin strapped high, the slave register loads from the master register
(thus changing the switch matrix state) on the rising edge of the LATCH signal. If it is
strapped low (level mode), the slave register is transparent while LATCH is low, passing
data directly from the master register to the switch state decoders. Strapping EDGE/LEVEL
and LATCH low causes the channel switch to execute on the WR rising edge (not
recommended for serial mode operation).

12, 23, 38

18, 29, 44

V+

Positive Supply Voltage. Connect all V+ pins together and decouple each pin to AGND
(Figure 2).

SER/PAR

A user strapped input that defines whether the serial (SER/PAR=1) or parallel
(SER/PAR=0) digital programming interface is being utilized.

16, 32

22, 38

V-

Negative Supply Voltage. Connect both V- pins together and decouple each pin to AGND
(Figure 2).

WRITE Input. In serial mode, data shifts into the shift register (Master Register) LSB from
SER IN on the WR rising edge. In parallel mode, the Master Register loads with D3:0 (iff
D3:0=0000 through 1000), or the appropriate action is taken (iff D3:0=1011 through 1111),
on the WR rising edge (see Table 1).

LATCH

Synchronous Channel Switch Control Input. If EDGE/LEVEL = 1, data is loaded from the
Master Register to the Slave Register on the rising edge of LATCH. If EDGE/LEVEL = 0,
data is loaded from the Master to the Slave Register while LATCH = 0. In parallel mode,
commands 1011 through 1110 execute asynchronously, on the WR rising edge, regardless
of the state of LATCH or EDGE/LEVEL. Parallel mode command 1111 executes a software
"Latch" (see Table 1).

Chip Enable. When CE = 0 and CE = 1, the WR line is enabled.

22, 24, 26, 29,

31, 33, 35, 37

28, 30, 32, 35,

37, 39, 41, 43

OUT7-OUT0

Analog Video Outputs.

25, 27, 30

31, 33, 36

AGND

Analog Ground.

Parallel Data Bit Input D3 when SER/PAR = 0. D3 is unused with serial programming.

Parallel Data Bit Input D2 when SER/PAR = 0. D2 is unused with serial programming.

HA456

Absolute Maximum Ratings

Thermal Information

Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
Positive Supply Voltage (V+) Referred to AGND . . . . . . . . . . . . . 6V
Negative Supply Voltage (V-) Referred to AGND . . . . . . . . . . . . -6V
DGND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND

Analog Input Voltage

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±

SUPPLY

Digital Input Voltage . . . . . . . . . . . . . . (V+ + 0.3V) to (DGND - 0.3V)
ESD Rating

Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . 1.5kV

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0

C to 70

Supply Voltage Range (Typical)

. . . . . . . . . . . . . . . . . . . ±

4.5V to

5.5V

Thermal Resistance (Typical, Note 1)

(

C/W)

PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Moisture Sensitivity (see Technical Brief TB363)

PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 3

Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . .175

Maximum Junction Temperature (Plastic Package) . . . . . . . . .150

Maximum Storage Temperature Range . . . . . . . . . . -65

C to 150

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300

(Lead Tips Only)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

SUPPLY

5V, AGND = DGND = 0V, R

= 400

(

Note 2)

Unless Otherwise Specified.

PARAMETER

TEST CONDITIONS

(NOTE 3)

TEST

LEVEL

TEMP

(

MIN

TYP

MAX

UNITS

Voltage Gain

= -1.5V to +1.5V, Worst Case

Switch Configuration

0.992

0.996

1.00

V/V

Full

0.99

0.995

1.00

Channel-to-Channel Gain Mismatch

0.001

0.004

V/V

Full

0.001

0.005

Supply Current

All Outputs Enabled, R

= Open,

= 0V,

Total for All V+ (3) or V- (2) Pins

Full

Disabled Supply Current

All Outputs Disabled, R

= Open,

Total for All V+ (3) or V- (2) Pins

Full

Input Voltage Range

Full

2.5

Analog Input Current

= 0V

Full

1.6

Input Noise (R

= 75

)

DC to 40MHz

0.15

RMS

10kHz

nV/

Analog Input Resistance

Analog Input Capacitance (Input
Connected to One Output or All Outputs,
Note 6)

PLCC Package

3.2

MQFP Package

2.5

Output Offset Voltage

= 0V, Worst Case Switch

Configuration

-18

-6.5

Full

-20

-7.5

Channel-to-Channel Offset Voltage
Mismatch

Full

Offset Voltage Drift

Full

Output Voltage Swing

2.5V

2.2

2.48

Full

2.1

2.47

Output Resistance

Enabled, DC

0.25

Output Leakage Current
(Including D1/SER OUT)

All Outputs Disabled,
V

OUT

= 2.5V

0.2

Full

Output Resistance

Output Disabled

0.6

HA456

Output Capacitance
(Output Disabled)

PLCC Package

3.5

MQFP Package

2.9

Power Supply Rejection Ratio

DC, V

4.5V to

5.5V, V

= 0V

Full

Digital Input Current (Note 5)

= 0V or 5V

Full

Digital Input Low Voltage

Full

0.8

Digital Input High Voltage

2.0

Full

2.2

SER OUT Logic Low Voltage

Serial Mode, I

= 1.6mA

Full

0.4

SER OUT Logic High Voltage

Serial Mode, I

= -0.4mA

Full

3.0

AC CHARACTERISTICS (Note 4)

-3dB Bandwidth (Note 6)

= 5pF, V

= 200mV

P-P

120

MHz

= 5pF, V

= 1V

P-P

MHz

= 5pF, V

= 2V

P-P

MHz

Slew Rate (Note 6)

OUT

= 4V

P-P

200

All Hostile Crosstalk (Note 6)

10MHz, V

= 1V

P-P

, R

=1k

-55

All Hostile Off Isolation (Note 6)

10MHz, V

= 1V

P-P

Differential Phase

NTSC or PAL, R

0.05

DEG

NTSC or PAL, R

10k

0.05

DEG

Differential Gain

NTSC or PAL, R

0.05

NTSC or PAL, R

10k

0.02

TIMING CHARACTERISTICS (See Figure 3 for more information)

Write Pulse Width High (t

)

Full

Write Pulse Width Low (t

)

Full

Chip-Enable Setup Time to Write (t

)

Full

Chip-Enable Hold Time From Write (t

)

Full

Data and Address Setup Time to Write (t

)

Parallel Mode

Full

Serial Mode

Full

Data and Address Hold Time From Write (t

)

Full

Latch Pulse Width (t

)

Full

Latch Delay From Write (t

)

Full

LATCH Edge to Output Disabled (t

OFF

)

Serial Mode

Full

LATCH Edge to Output Enabled (t

)

Serial Mode

Full

185

Output Break-Before-Make Delay
(t

ON -

OFF

)

Serial Mode

Full

155

NOTES:

2. For the lowest crosstalk, and the best composite video performance, use R

3. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only.

4. See AC Test Circuits (Figure 6 through Figure 9).

5. Excludes D1/SER OUT which is a bidirectional terminal and thus falls under the higher Output Leakage limit.

6. See Typical Performance Curves for more information.

Electrical Specifications

SUPPLY

5V, AGND = DGND = 0V, R

= 400

(

Note 2)

Unless Otherwise Specified. (Continued)

PARAMETER

TEST CONDITIONS

(NOTE 3)

TEST

LEVEL

TEMP

(

MIN

TYP

MAX

UNITS

HA456

Application Information

HA456 Architecture

The HA456 video crosspoint switch consists of 64 switches
in an 8 x 8 grid (Figure 1). Each input is fully buffered and
presents a constant input capacitance whether the input
connects to one output or all eight outputs. This yields
consistent input termination impedances regardless of the
switch configuration. The 8 matrix outputs are followed by 8
unity gain, wideband, tristatable buffers optimized for driving
400

and 5pF loads. The output disable function is useful for

multiplexing two or more HA456s to create a larger input
matrix (e.g., two multiplexed HA456s yield a 16x8
crosspoint).

The HA456 outputs can be disabled individually or
collectively under software control. When disabled, an output
enters a high-impedance state. In multichip parallel
applications, the disable function prevents inactive outputs
from loading lines driven by other devices. Disabling an
unused output also reduces power consumption.

The HA456 outputs connect easily to two HFA1412 quad,
gain-of-two buffers when 75

loads must be driven.

Power-On RESET

The HA456 has an internal power-on reset (POR) circuit that
disables all outputs at power-up, and presets the switch
matrix so that all outputs connect to IN0. In parallel mode,
the desired switch state may be programmed before the
outputs are enabled. In serial mode, all outputs are
connected to GND each time they are enabled, so switch
state programming must occur after the output is enabled.

Digital Interface

The desired switch state can be loaded using a 7-bit parallel
interface mode or 32-bit serial interface mode (see Tables 1
through 3). All actions associated with the WR line occur on
its rising edge. The same is true for the LATCH line if
EDGE/LEVEL=1. Otherwise, the Slave Register updates
asynchronously (while LATCH=0, if EDGE/LEVEL=0). WR
is logically ANDed with CE and CE to allow active high or
active low chip enable.

7-Bit Parallel Mode

In the parallel programming mode (SER/PAR = 0), the 7
control bits (A2:0 and D3:0) typically specify an output
channel (A2:0) and the corresponding action to be taken
(D3:0). Command codes are available to enable or disable
all outputs, or individual outputs, as shown in Table 1. Each
output has 4-bit Master and Slave Registers associated with
it, that hold the output's currently selected input address
(defined by D3:0). The input address - if applicable - is
loaded into the Master Register on the rising edge of WR. If
the HA456 is in level mode, and if LATCH=0 (asynchronous
switching), then the input address flows through the
transparent Slave Register, and the output immediately

switches to the new input. For synchronous switching on the
rising edge of LATCH, strap the HA456 for edge mode,
program all the desired switch connections, and then drive
an inverted pulse on the LATCH input. Note: Operations
defined by commands 1011 - 1111 occur asynchronously on
the WR rising edge, without regard for the state of LATCH or
EDGE/LEVEL.

32-Bit Serial Mode

In the serial programming mode, all master registers are
loaded with data, making it unnecessary to specify an output
address (A2:0). The input data format is D3-D0, starting with
OUT0 and ending with OUT7 for 32 total bits (i.e., first bit
shifted in is D3 for OUT0, and 32nd bit shifted in is D0 for
OUT7). Only codes 0000 through 1010 are valid serial mode
commands. Code 1010 disables an individual output, while
code 1001 enables it. After data is shifted into the 32-bit
Master Register, it transfers to the Slave Register on the
rising edge of the LATCH line (Edge mode), or when
LATCH=0 (Level mode, see Figure 5).

HA456

Figure 2 shows a typical application of the HA456 with
HFA1412 quad, gain-of-two buffers at the outputs to drive
75

loads. This application shows the HA456 digital-switch

control interface set up in the 7-bit parallel mode. The HA456
uses 7 data lines and 3 control lines (WR, CE and LATCH).

The input/output information is presented to the chip at A2:0
and D3:0 by a parallel printer port. The data is stored in the
Master Registers on the rising edge of WR. When the
LATCH line goes high, the switch configuration loads into the
Slave Registers, and all 8 outputs reconfigure at the same
time. Each 7-bit word updates only one output at a time. If
several outputs are to be updated, the data is individually
loaded into the Master Registers. Then, a single LATCH
pulse can reconfigure all channels simultaneously.

An IBM compatible PC loads the programming data into the
HA456 via its parallel port (LPT1) using a simple BASIC
program.

TABLE 1. PARALLEL INTERFACE COMMANDS

A2:0

D3:0

ACTION

Selects
Output
Being
Programmed

0000 to 0111

Connect the input defined by D3:0 to the output selected by A2:0. Doesn't enable a disabled output.

1000

Connect the output selected by A2:0 to GND. Doesn't enable a disabled output.

1011

Asynchronously disable the single output selected by A2:0, and leave the Master Register unchanged.

1100

Asynchronously enable the single output selected by A2:0, and leave the Master Register unchanged.

Address
Inputs are
Irrelevant for
These
Functions

1101

Asynchronously disable all outputs, and leave the Master Register unchanged.

1110

Asynchronously enable all outputs, and leave the Master Register unchanged.

1111

Send a Software "Latch" pulse to the Slave Register to load it from the Master Register, iff, the LATCH input=1.
If the LATCH input=0, then this command is a NOP. The Master Register is unchanged by this command.

1001 or 1010

Do not use these codes in the parallel programming mode. These codes are for serial programming only.

TABLE 2. SERIAL INTERFACE COMMANDS

D3:0

ACTION

0000 to 0111

Connect the output to the input channel defined by D3:0. Doesn't enable a disabled output.

1000

Connect the output to GND. Doesn't enable a disabled output.

1001

Enable the output and connect it to GND. The default power-up state is all outputs disabled, so use this code to enable
outputs after power is applied, but before programming the switch configuration.

1010

Disable the output. The output is no longer associated with any input channel; the desired input must be redefined after
reenabling the output.

1011 to 1111

Do not use these codes in the serial programming mode.

TABLE 3. DEFINITION OF DATA AND ADDRESS BIT FUNCTIONS

SER/PAR

A2:0

COMMENT

Serial

Data

Output

Serial

Data

Input

32-Bit Serial Mode

Parallel Data

Input

Parallel Data

Input

Parallel Data

Input

Output

Address

Parallel Mode; D2:0 define the

command to be executed

Parallel Data

Input

Parallel Data

Input

Parallel Data

Input

Output

Address

Parallel Mode; D2:0 define the

Input Channel

HA456

Waveforms

FIGURE 3. DIGITAL TIMING REQUIREMENTS

2
3
4
5

7
8

40
36
34

43
42

33
31

29
26

24
22
21

12, 23, 38

25, 27, 30

5, 8
16, 32

7
8

10
12

IN 1

IN 2
IN 3

IN 4

OUT1

OUT2

OUT3
OUT4

V+

V-

IN0
IN1

IN2
IN3
IN4

IN5

IN6
IN7

LATCH

D2
D3

A0
A1

D0/SER IN
D1/SER OUT

OUT0

OUT1

OUT2
OUT3

OUT4

OUT5
OUT6
OUT7

EDGE/LEVEL

V+

AGND

DGND

V-

SER/PAR

HA456 (MQFP PINOUT)

HFA1412

VIDEO

INPUTS

+5V

-5V

NOTE: All decoupling capacitors 0.1

F Ceramic (1 per supply pin). For lowest crosstalk connect unused pins to GND use R

to tune the overall

output response.

FIGURE 2. TYPICAL HIGH PERFORMANCE, PARALLEL MODE APPLICATION CIRCUIT (SEE FIGURE 18)

= +2)

-IN0:3

2, 6 9, 13

OUT

VALID DATA

A2:0, D3:0

LATCH

(EDGE MODE)

HA456

FIGURE 4. PARALLEL PROGRAMMING MODE OPERATION (SER/PAR = 0)

FIGURE 5. SERIAL PROGRAMMING MODE OPERATION (SER/PAR = 1)

Waveforms

(Continued)

DATA (N)

DATA (N + 1)

DATA (N + 2)

DATA (N)

DATA (N + 1)

DATA (N + 2)

LATCH

MASTER REGISTER CONTENTS

SLAVE REGISTER CONTENTS

(EDGE/LEVEL = 0)

SLAVE REGISTER CONTENTS

(EDGE/LEVEL = 1)

DATA (N + 2)

SLAVE REGISTER CONTENTS

(EDGE/LEVEL = 0)

SLAVE REGISTER CONTENTS

(EDGE/LEVEL = 1)

LATCH

NEW DATA

NEW DATA FOR

OUT1 TO OUT6

NEW DATA FOR

OUT0

NEW DATA FOR

OUT7

t = 0

1st

WRITE

32nd

WRITE

OLD DATA

SER IN

HA456

AC Test Circuits

FIGURE 6. -3dB BANDWIDTH (NOTES 7-10)

FIGURE 7. ALL HOSTILE OFF ISOLATION (NOTES 10-12)

FIGURE 8. SINGLE CHANNEL CROSSTALK (NOTES 10, 13-16)

FIGURE 9. ALL HOSTILE CROSSTALK (NOTES 10, 15, 17-19)

NOTES:

7. Program the desired input to output combination (e.g., IN7 to OUT1).

8. Enable the selected output(s).

9. Drive the selected input with V

, and measure the -3dB frequency at the selected output (V

OUT

10. Load all outputs with the desired R

11. Disable all outputs.

12. Drive all inputs with V

and measure V

OUT

at any output; isolation (in dB) = -20log

OUT

13. Drive V

on one input which connects to one output (e.g., IN7 to OUT7).

14. Terminate all other inputs to GND.

15. Enable all outputs.

16. Measure V

OUT

at any undriven output; crosstalk (in dB) = 20log

OUT

17. Terminate one input to GND, and connect that input to a single output (e.g., IN0 to OUT0).

18. Drive the other seven inputs with V

, and connect these active inputs to the remaining seven outputs.

19. Measure V

OUT

at the quiescent output; crosstalk (in dB) = 20log

OUT

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

OUT0

OUT3

OUT4

OUT5

OUT6

OUT7

OUT1

OUT2

OUT

= 1V

P-P

, SWEEP FREQUENCY

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

OUT0

OUT3

OUT4

OUT5

OUT6

OUT7

OUT1

OUT2

= 1V

P-P

, AT 10MHz

OUT

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

OUT0

OUT3

OUT4

OUT5

OUT6

OUT7

OUT1

OUT2

= 1V

P-P

, AT10MHz

OUT

7 X 75

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

OUT0

OUT3

OUT4

OUT5

OUT6

OUT7

OUT1

OUT2

= 1V

P-P

, AT 10MHz

OUT

HA456

Typical Performance Curves

SUPPLY

5V, T

= 25

C, R

= 400

, Unless Otherwise Specified

FIGURE 10. SMALL SIGNAL PULSE RESPONSE

FIGURE 11. LARGE SIGNAL PULSE RESPONSE

FIGURE 12. FREQUENCY RESPONSE

FIGURE 13. GAIN FLATNESS

FIGURE 14. ALL HOSTILE CROSSTALK

FIGURE 15. ALL HOSTILE OFF-ISOLATION

OUTPUT V

GE (V)

TIME (20ns/DIV.)

1.4

1.2

1.0

0.8

0.6

0.4

0.2

-0.2

OUTPUT V

GE (V)

TIME (20ns/DIV.)

4.0

3.0

2.0

1.0

-1.0

-2.0

-3.0

-4.0

FREQUENCY (MHz)

100

200

-3

OUT

= 1V

P-P

OUT

= 0.2V

P-P

-6

135

180

OUT

= 0.2V

P-P

GAIN (dB)

PHASE (DEGREES)

GAIN

PHASE

OUT

= 2V

P-P

OUT

= 2V

P-P

OUT

= 1V

P-P

FREQUENCY (MHz)

GAIN (dB)

100

200

0.5

-0.5

OUT

= 1V

P-P

-1.0

1.0

-1.5

-2.0

OUT

= 0.2V

P-P

FREQUENCY (MHz)

100

200

-60

-70

-80

-90

-100

-10

-20

-30

-40

-50

= 1k

= 150

OSST

ALK (dB)

= 1V

P-P

= 150

= 1k

100

110

100

200

FREQUENCY (MHz)

OFF ISOLA

TION (dB)

= 1V

P-P

HA456

FIGURE 16. SLEW RATE vs V

OUT

FIGURE 17. INPUT IMPEDANCE vs FREQUENCY

FIGURE 18. FREQUENCY RESPONSE OF HA456-HFA1412 COMBINATION (PER FIGURE 2)

Typical Performance Curves

SUPPLY

5V, T

= 25

C, R

= 400

, Unless Otherwise Specified (Continued)

SLEW RA

TE (V/

OUT

P-P

)

250

225

200

175

150

125

100

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

FREQUENCY (MHz)

GNITUDE (dB

)

0.1

100

0.03

120

110

100

1 INPUT TO 1 OUTPUT

1 INPUT TO ALL OUTPUTS

PHASE (DEGREES)

PHASE

100

200

-3

OUT

= 1V

P-P

OUT

= 0.5V

P-P

-6

FREQUENCY (MHz)

GAIN (dB)

=150

= 0

HA456

HA456

Metric Plastic Quad Flatpack Packages (MQFP)

E E1

-A-

PIN 1

A2 A1

-16

-7

0.40

0.016

MIN

PLANE

0.005/0.009

0.13/0.23

WITH PLATING

BASE METAL

SEATING

0.005/0.007

0.13/0.17

-B-

0.008

0.20

A-B

0.076
0.003

-C-

-D-

-H-

Q44.10x10

(JEDEC MS-022AB ISSUE B)

44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE

SYMBOL

INCHES

MILLIMETERS

NOTES

MIN

MAX

MIN

MAX

0.096

2.45

0.004

0.010

0.10

0.25

0.077

0.083

1.95

2.10

0.012

0.018

0.30

0.45

0.012

0.016

0.30

0.40

0.515

0.524

13.08

13.32

0.389

0.399

9.88

10.12

4, 5

0.516

0.523

13.10

13.30

0.390

0.398

9.90

10.10

4, 5

0.029

0.040

0.73

1.03

0.032 BSC

0.80 BSC

Rev. 2 4/99

NOTES:

1. Controlling dimension: MILLIMETER. Converted inch

dimensions are not necessarily exact.

2. All dimensions and tolerances per ANSI Y14.5M-1982.

3. Dimensions D and E to be determined at seating plane

4. Dimensions D1 and E1 to be determined at datum plane

5. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is 0.25mm (0.010 inch) per side.

6. Dimension b does not include dambar protrusion. Allowable

dambar protrusion shall be 0.08mm (0.003 inch) total.

7. "N" is the number of terminal positions.

-C-

-H-

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

Sales Office Headquarters

NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240

EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05

ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029

HA456

Plastic Leaded Chip Carrier Packages (PLCC)

NOTES:

1. Controlling dimension: INCH. Converted millimeter dimensions are

not necessarily exact.

2. Dimensions and tolerancing per ANSI Y14.5M-1982.

3. Dimensions D1 and E1 do not include mold protrusions. Allowable

mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1
and E1 include mold mismatch and are measured at the extreme
material condition at the body parting line.

4. To be measured at seating plane

contact point.

5. Centerline to be determined where center leads exit plastic body.

6. "N" is the number of terminal positions.

-C-

SEATING
PLANE

0.020 (0.51)

MIN

VIEW "A"

D2/E2

0.025 (0.64)
0.045 (1.14)

0.042 (1.07)
0.056 (1.42)

0.050 (1.27) TP

0.042 (1.07)
0.048 (1.22)

PIN (1) IDENTIFIER

0.020 (0.51) MAX

3 PLCS

0.026 (0.66)
0.032 (0.81)

0.045 (1.14)

MIN

0.013 (0.33)

0.021 (0.53)

0.025 (0.64)

MIN

VIEW "A" TYP.

0.004 (0.10)

-C-

D2/E2

N44.65

(JEDEC MS-018AC ISSUE A)

44 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

SYMBOL

INCHES

MILLIMETERS

NOTES

MIN

MAX

MIN

MAX

0.165

0.180

4.20

4.57

0.090

0.120

2.29

3.04

0.685

0.695

17.40

17.65

0.650

0.656

16.51

16.66

0.291

0.319

7.40

8.10

4, 5

0.685

0.695

17.40

17.65

0.650

0.656

16.51

16.66

0.291

0.319

7.40

8.10

4, 5

Rev. 2 11/97

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