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Электронный компонент: HC5503

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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright Intersil Corporation 1999
HC5503
Low Cost 24V SLIC For PABX/Key
Systems
The Intersil HC5503 low cost SLIC is optimized for use in
small Analog or mixed Analog and Digital Key Telephone
Systems (KTS) or PBX products. The low component count
solution and surface mount package options, enable a small
desktop Key System/PBX product to be achieved. The
internal power dissipation of the end product is minimized by
the low power consumption and minimal power supply
voltage requirements of the HC5503.
The HC5503 integrated solution provides higher quality,
higher reliability and better performance solution than a
transformer, thick film hybrid or discrete analog subscriber
interface design.
The HC5503 is designed in a Dielectrically isolated bipolar
technology and is inherently latch proof and does not require
hot plug or power supply sequencing precautions.
Description
Wide Operating Battery Range (-21V to -44V)
Single Additional +5V Supply
25mA Short Loop Current Limit
Ring Relay Driver
Switch Hook and Ring Trip Detect
Low On-Hook Power Consumption
On-Hook Transmission
ITU-T Longitudinal Balance Performance
Loop Power Denial Function
Thermal Protection
Supports Tip, Ring or Balanced Ringing Schemes
Low Profile SO and PLCC Surface Mount Packaging
Pin Compatible with Industry Standard HC5504B SLIC
Applications
Analog Subscriber Line Interfaces in Analog Key Systems
and Digital ISDN PABX Systems
Related Literature
- AN571, Using Ring Sync with HC-5502A and HC-5504
SLICs
Block Diagram
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG.
NO.
HC5503CM
0 to 75
28 Ld PLCC
N28.45
HC5503CB
0 to 75
24 Ld SOIC
M24.3
RD
RFS
TIP
TF
RING
RF
V
BAT
V
CC
BGND
DGND
TX
RX
SHD
RS
RC
PD
RING RELAY
DRIVER
4-WIRE
INTERFACE
VF SIGNAL
PATH
LOOP CURRENT
DETECTOR
BIAS
LOGIC
INTERFACE
RING TRIP
DETECTOR
2-WIRE
INTERFACE
C
1
C2
AGND
THERMAL LIMIT
March 1999
File Number
4344.3
2
Absolute Maximum Ratings
(Note 1)
Thermal Information
Maximum Continuous Supply Voltages
(V
BAT
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -60 to 0.5V
(V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 15V
(V
CC
- V
BAT
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75V
Relay Drive Voltage (V
RD
) . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 15V
Operating Conditions
Operating Temperature Range
HC5503 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to 75
o
C
Relay Driver Voltage (V
RD
) . . . . . . . . . . . . . . . . . . . . . . . . 5V to 12V
Positive Supply Voltage (V
CC
) . . . . . . . . . . . . . . . . . . 4.75V to 5.25V
Negative Supply Voltage (V
BAT
) . . . . . . . . . . . . . . . . . .-22V to -26V
High Level Logic Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V
Low Level Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6V
Thermal Resistance (Typical, Note 2)
JA
(
o
C/W)
24 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
28 Lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(PLCC and SOIC - Lead Tips Only)
Die Characteristics
Transistor Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Diode Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 x 102
Substrate Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connected
Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied.
2.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Unless Otherwise Specified, V
BAT
= -24V, V
CC
= 5V, AG = BG = DG = 0V, Typical Parameters
T
A
= 25
o
C. Min-Max Parameters are Over Operating Temperature Range
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
On Hook Power Dissipation
I
LONG
= 0 (Note 3), V
CC
= 5V
-
80
100
mW
Off Hook Power Dissipation
R
L
= 600
, I
LONG
= 0 (Note 4), V
CC
= 5V
-
180
200
mW
Off Hook I
VCC
R
L
= 600
, I
LONG
= 0 (Note 3), T
A
= 0
o
C
-
-
6.0
mA
Off Hook I
VCC
R
L
= 600
, I
LONG
= 0 (Note 3), T
A
= 25
o
C
-
-
4.0
mA
Off Hook I
BAT
R
L
= 600
, I
LONG
= 0 (Notes 3, 4)
-
19
23
mA
Off Hook Loop Current
R
L
= 400
, I
LONG
= 0 (Note 3)
-
22.9
-
mA
Off Hook Loop Current
R
L
= 400
, V
BAT
= -21.6V, I
LONG
= 0 (Note 3)
T
A
= 25
o
C
17.5
-
-
mA
Off Hook Loop Current
R
L
= 200
, I
LONG
= 0 (Note 3)
-
25
30
mA
Fault Currents
TIP to Ground
(Note 4)
-
27.5
-
mA
RING to Ground
-
70
-
mA
TIP to RING
(Note 4)
-
30
-
mA
TIP and RING to Ground
-
140
-
mA
Ring Relay Drive V
OL
I
OL
= 62mA
-
0.2
0.5
V
Ring Relay Driver Off Leakage
V
RD
= 12V, RC = 1 = HIGH, T
A
= 25
o
C
-
-
25
A
Ring Trip Detection Period
R
L
= 600
,
(Note 5)
-
2
3
Ring Cycles
Switch Hook Detection Threshold
5
-
10.5
mA
Loop Current During Power Denial
R
L
= 200
-
2
-
mA
Dial Pulse Distortion
(Note 4)
0
-
0.5
ms
Receive Input Impedance
(Note 5)
-
90
-
k
Transmit Output Impedance
(Note 5)
-
10
20
HC5503
3
2-Wire Return Loss
Referenced to 600
+2.16
F (Note 4)
SR
L
LO
-
15.5
-
dB
ER
L
-
24
-
dB
SR
L
HI
-
31
-
dB
Longitudinal Balance
1V
RMS
200Hz - 3400Hz, (Note 4) IEEE Method
0
o
C
T
A
75
o
C
2-Wire Off Hook
53
58
-
dB
2-Wire On Hook
53
58
-
dB
4-Wire Off Hook at 1kHz
50
58
-
dB
Insertion Loss
0dBm Input Level, Referenced 600
2-Wire to 4-Wire at 3.4kHz
V
TR
to V
O
V
O
is the Output of the Transhybrid
Amplifier
-
0.05
0.2
dB
4-Wire to 2-Wire at 300Hz
-3.8
-4.0
-4.2
dB
Frequency Response
200 - 3400Hz Referenced to Absolute Loss at 1kHz
and 0dBm Signal Level (Note 4)
-
0.02
0.05
dB
Idle Channel Noise
2-Wire to 4-Wire
-
1
5
dBrnC
-
-89
-85
dBm0p
Idle Channel Noise
4-Wire to 2-Wire
(Note 4)
-
1
5
dBrnC
-
-89
-85
dBm0p
Absolute Delay
(Note 5)
2-Wire to 4-Wire, 4-Wire to 2-Wire
-
-
2
s
Trans Hybrid Loss
Balance Network Set Up for 600
Termination at
1kHz
30
40
-
dB
Overload Level
V
CC
= +5V
2-Wire to 4-Wire (On-hook)
2.5
-
-
V
PEAK
4-Wire to 2-Wire (Off-hook, R
L
= 600
)
3.1
-
-
V
PEAK
Level Linearity
At 1kHz, (Note 4) Referenced to 0dBm Level
2-Wire to 4-Wire, 4-Wire to 2-Wire
+3 to -40dBm
-
-
0.05
dB
-40 to -50dBm
-
-
0.1
dB
-50 to -55dBm
-
-
0.3
dB
Power Supply Rejection Ratio
(Note 4)
30 - 60Hz, R
L
= 200
V
CC
to 2-Wire
35
-
-
dB
V
CC
to Transmit
35
-
-
dB
V
BAT
to 2-Wire
20
-
-
dB
V
BAT
to Transmit
20
-
-
dB
V
CC
to 2-Wire
200 - 16kHz, R
L
= 200
35
-
-
dB
V
CC
to Transmit
35
-
-
dB
V
BAT
to 2-Wire
35
-
-
dB
V
BAT
to Transmit
35
-
-
dB
Logic Input Current (RS, RC, PD)
0V
V
IN
2.4V
-
-
20
A
Electrical Specifications
Unless Otherwise Specified, V
BAT
= -24V, V
CC
= 5V, AG = BG = DG = 0V, Typical Parameters
T
A
= 25
o
C. Min-Max Parameters are Over Operating Temperature Range (Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
HC5503
4
Logic Inputs
Logic `0' V
IL
-
-
0.8
V
Logic `1' V
IH
2.0
-
5.5
V
SHD Output
I
LOAD
800
A, V
CC
= 5V
Logic `0' V
OL
-
0.1
0.4
V
Logic `1' V
OH
I
LOAD
40
A, V
CC
= 5V
2.7
-
5.0
V
NOTES:
3. I
LONG
= Longitudinal Current.
4. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon initial
design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and specification com-
pliance.
5. Guaranteed by design, not tested.
Electrical Specifications
Unless Otherwise Specified, V
BAT
= -24V, V
CC
= 5V, AG = BG = DG = 0V, Typical Parameters
T
A
= 25
o
C. Min-Max Parameters are Over Operating Temperature Range (Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
HC5503
5
Design Information
Line Feed Amplifiers
The line feed amplifiers are high power operational
amplifiers and are connected to the subscriber loop through
150
of feed resistance as shown in Figure 1. The feed
resistors and synthesized impedance via feedback provide a
600
balanced load for the 2-wire to 4-wire transmission.
The tip feed amplifier is configured as a unity gain
noninverting buffer. A -4V bias (derived from the negative
battery (V
BAT
) in the bias network) is applied to the input of
the amplifier. Hence, the tip feed DC level is at -4V. The
principal reason for this offset is to accommodate sourcing
and sinking of longitudinal noise currents up to 15mA
RMS
without saturating the amplifier output and to provide
sufficient overhead for receive signals. The tip feed amplifier
also feeds the ring feed amplifier, which is configured as a
unity gain inverting amplifier as seen from the tip feed
amplifier. The noninverting input to the ring feed amp is
biased at a V
BAT
/2. Looking into this terminal the amplifier
has a noninverting gain of 2. Thus, the DC output at ring
feed is:
V
RF
(DC) = (4 + V
BAT
) Volts
For a -24V battery, V
RF
= -20V. Hence, the nominal battery
feed across the loop provided by the SLIC is 16V. When the
subscriber goes off-hook this DC feed causes current
(metallic current) to flow around the loop.
The received audio signal R
X
is fed into the tip feed amplifier
and appears at the tip feed terminal. It is also fed through the
ring feed amplifier and is inverted. Thus, a differential signal of
2V
RX
appears between tip feed and ring feed. The R
X
signal
causes AC audio currents to flow around the loop which are
then AC coupled to the earpiece of the telephone set.
2-Wire Impedance Matching
The HC5503 is optimized for operation with a -24V battery.
Impedance matching to a 600
load, is achieved through
the combination of the feed resistors (R
B1
, R
B2
) and
negative feedback through resistor R
2
(reference Figure 1).
R
B1
and R
B2
are sense resistors that detect loop current
and provide negative feedback to synthesize the remaining
300
required to match a 600
line.
The impedance looking into the tip terminal is 150
(R
B1
)
plus the synthesized impedance of the tip amplifier. The
synthesized tip impedance is equal to the tip feed voltage Va
divided by
IL. (Note, the tip feed amplifier is a voltage
follower. Thus, the tip feed voltage is equal to the receive
input voltage V
RX
, both are labeled Va.) The synthesized
impedance of the ring terminal is calculated the same way
and is the ring feed voltage divided by
IL. (Note, the ring
feed voltage is equal in magnitude to the tip feed voltage, but
opposite in phase as a result of the ring feed amplifier gain.)
TIP
150
TIP FEED
-
+
90k
-
+ 4V
DC
(NOTE)
C
3
R
3
TO TRANSHYBRID OP-AMP
R
1
INPUT
FROM
CODEC
-
+
+
-
-
+2
C
4
4RS
I
L
+
+4RS
I
L
+
-
RING FEED
R
B2
150
-
I
L
+
RING
V
BAT
2
(NOTE)
R
R
HC5503
Z
IN
R
B1
= R
B2
= R
S
= 150
-
+
V
IN
R
2
Va
RX
TX
R
B1
I
L
+
-
NOTE: Grounded for AC analysis.
FIGURE 1. IMPEDANCE MATCHING CIRCUITRY
HC5503
6
The value of Va, as a result of feedback through R
2
from the
T
X
output, is given in Equation 1. Equation 1 is a voltage
divider equation between resistors R
2
and the parallel
combination of resistors; R
1
, R
3
and the internal 90k
resistor R
INTERNAL
. The Voltage on the transmit out (T
X
) is
the sum of the voltage drops across resistors R
B1
and R
B2
that is gained up by 2 to produce an output voltage at the
V
TX
pin that is equal to -4R
S
IL.
Where: V
TX
= -4R
S
IL = -600
IL.
To match a 600
line, the synthesized tip and ring impedance
must be equal to 150
. The impedance looking into either the
tip or ring terminal is once again the voltage at the terminal (Va)
divided by the AC current
IL as shown in Equation 2.
Substituting the value of 600
IL for V
TX
in Equation 1 and
dividing both sides by
IL results in Equation 3.
Setting Va/
IL equal to 150
and solving for R
2
, given that
R
1
= 10k
, R
INTERNAL
= 90k
and R
3
= 150k
the value of
R
2
to match the input impedance of 600
is determined to
be 25.47k
. (Note: nearest standard value is 24.9k
).
The amount of negative feedback is dependent upon the
additional synthesized resistance required for matching. The
sense resistors R
B1
and R
B2
should remain at 150
to
maintain the SHD threshold listed in the electrical
specifications. The additional synthesized resistance is
determined by the feed back factor X (Equation 4) which
needs to be applied to the transmit output and fed into the
RX pin of the HC5503. The feed back factor is equal to the
voltage divider between R2 and the parallel combination of
R
1
, R
3
and R
INTERNAL
, reference Figure 2.
The voltage that is feed back into the RX pin is equal to the
voltage at V
TX
times the feedback factor (Equation 5).
Where V
TX
is equal to -4R
S
IL (R
S
= 150
)
So:
But, from Equation 2:
Therefore:
Equation 8 shows that 1/4 of the T
X
output voltage is
required to synthesize 150
at both the Tip feed and Ring
feed amplifiers.
To match a 900
load would require 300
worth of
synthesized impedance (300
from R
B1
+ R
B2
and 600
from the Tip feed + Ring feed amplifiers).
Setting Va/
IL equal to 300
and solving for R
2
in Equation 3,
given that R
1
= 10k
, R
INTERNAL
= 90k
and R
3
= 150k
the value of R
2
to match the input impedance of 900
is
determined to be 8.49k
(Note: nearest standard value is
8.45k
). The feed back factor to match a 900
load is 1/2
(300/600).
The selection of the value of 150k
for R
3
is arbitrary. The
only requirement is that it be large enough to have little effect
on the parallel combination between R
INTERNAL
(90k
) and
R
1
(10k
). R
3
should be greater then 90k
.
The selection of the value of 10k
for R
1
is also arbitrary.
The only requirement is that the value be small enough to
offset any process variations of R
INTERNAL
and large
enough to avoid loading of the CODEC's output. A value of
10k
is a good compromise.
2-Wire to 4-Wire Gain
The 2-wire to 4-wire gain is defined as the output voltage
V
TX
divided by the tip to ring voltage (V
TR
). Where:
V
TX
= -4R
S
IL = -600
IL and V
TR
= (RL)
IL = 600
IL.
The 2-wire to 4-wire gain is therefore equal to -1.0, as
shown in Equation 9.
V
a
R
1
90k
R
3
R
1
90k
R
3
R
2
+
-------------------------------------------------
V
TX
=
(EQ. 1)
Z
Tipfeed
Z
Ringfeed
V
a
I
L
--------
150
=
=
=
(EQ. 2)
V
a
I
L
--------
R
1
90k
R
3
R
1
90k
R
3
R
2
+
-------------------------------------------------
600
=
(EQ. 3)
FeedbackFactor
X
R
1
90k
R
3
R
1
90k
R
3
R
2
+
-------------------------------------------------
=
=
(EQ. 4)
FIGURE 2. FEEDBACK EQUIVALENT CIRCUIT
HC5503
R
X
T
X
R
1
R
3
150k
R
2
24.9k
R
INTERNAL
90.0k
10k
FEED BACK
T
X
= -4R
S
IL
V
a
V
TX
X
( )
=
(EQ. 5)
X
V
a
I
L
600
-------------------
=
(EQ. 6)
V
a
I
L
--------
150
=
(EQ. 7)
X
V
a
V
TX
-----------
150
600
----------
1
4
---
=
=
=
(EQ. 8)
A
2
4
V
TX
V
TR
-----------
600
I
L
600
I
L
----------------------
1.0
=
=
=
(EQ. 9)
HC5503
7
4-Wire to 2-Wire Gain
The 4-wire to 2-wire gain is defined as the output voltage
V
TR
divided by the input voltage, V
IN
. To determine the
4-wire to 2-wire gain we need to define V
TR
in terms of V
IN
.
The voltage at V
TR
is the loop current times the load
impedance Z
L
.
For optimum 2-wire return loss, the input impedance of the
SLIC (Z
O
) must equal the load impedance (Z
L
) of the line. All
Equations going further assume Z
L
= Z
O
.
The loop current
IL is the total voltage across the loop
divided by the total resistance of the loop. The total voltage
across the loop is the sum of the tip feed voltage (V
TF
) and
the ring feed voltage (V
RF
) where V
TF
= -V
RF
. The total
resistance is the sum of the sense resistors RB
1
and RB
2
and the load Z
L
(Z
L
+2R
S
). The total loop current is defined
in Equation 11.
From Equation 10:
Substituting Equation 12 into Equation 11 and solving for
V
TR
:
Using Superposition, the voltage at the receive input R
X
is
given as:
Where R
1
is the effective impedance that is formed by the
parallel combination of R
INTERNAL
(90k
), R
3
(150k
), R
1
(10k
) and is equal to 8.49k
. R
2
is the effective
impedance that's formed by the parallel combination of
R
INTERNAL
(90k
), R
3
(150k
), R
2
(24.9k
) and is equal
to 17.25k
.
V
RX
for the recommended values of R
1
and R
2
is given in
Equations 15 and 16. For impedance matching to a load
other than 600
, recalculate the parallel impedances R
1
,
R
2
and substitute into Equation 15. The 4-wire to 2-wire
gain is recalculated by using the Equations below.
Substituting Equation 16 into Equation 13:
From Equation 10:
From Equation 1:
Substituting Equation 18 into Equation 19:
Substituting Equation 20 into Equation 17:
Assuming R
S
= 150
and rearranging terms:
The 4-wire to 2-wire gain (Given that: R
1
= 10k
, R
2
= 24.9k
and R
3
= 150k
)
for a 600
load is:
V
TR
I
L
Z
L
I
L
Z
O
=
=
(EQ. 10)
I
L
V
TF
V
RF
Z
O
2R
S
+
----------------------------
2 V
TF
(
)
Z
O
2R
S
+
--------------------------
=
=
(EQ. 11)
I
L
V
TR
Z
O
-----------
=
(EQ. 12)
V
TR
2 V
TF
(
)
Z
O
2R
S
+
--------------------------
Z
O
=
(EQ. 13)
V
RX
V
TF
R
1
R
1
R
2
+
-----------------------
V
TX
R
2
R
2
R
1
+
-----------------------
V
IN
+
=
=
(EQ. 14)
V
RX
V
TF
8.49k
8.49k
24.9k
+
----------------------------------------------
V
TX
17.25k
17.25k
10k
+
---------------------------------------------
V
IN
+
=
=
(EQ. 15)
V
RX
V
TF
0.25
(
)
V
TX
0.633
(
)
V
IN
+
=
=
(EQ. 16)
V
TR
2 0.25
(
)
V
TX
0.633
(
)
V
IN
+
(
)
Z
O
2R
S
+
-------------------------------------------------------------------------
Z
O
=
(EQ. 17)
I
L
V
TR
Z
O
-----------
=
(EQ. 18)
V
TX
4RS
I
L
=
(EQ. 19)
V
TX
4RS
V
TR
Z
O
-----------
=
(EQ. 20)
V
TR
2RS
V
TR
Z
O
-----------
1.266V
IN
+
Z
O
Z
O
2R
S
+
--------------------------
=
(EQ. 21)
1
300
Z
O
300
+
------------------------
+
V
TR
1.266Z
O
Z
O
300
+
------------------------
V
IN
=
(EQ. 22)
A
4
2
V
TR
V
IN
-----------
1.266Z
O
Z
O
600
+
------------------------
0.633
3.96dB
=
=
=
=
(EQ. 23)
HC5503
8
The Transversal Amplifier (TA)
Whereas the feed amplifiers perform the 4-wire to 2-wire
transmission function, the transversal amplifier acts as the
2-wire to 4-wire hybrid. The TA is a summing amplifier
configured to reject common mode signals. It will reject 2-
wire common mode signals. R
B1
and R
B2
act as loop
current sense resistors. The voice signal output of the
amplifier is a function of the differential voltages appearing
across R
B1
and R
B2
.
The transversal amplifier also has a DC output proportional
to the metallic current in the loop. The output voltage is
given by:
V
TX
= 2(I
TIP
+ I
RING
) (R
B1
+ R
B2
)
This DC level is used as an input to a comparator whose
output feeds into the logic circuitry as SH. This signal is used
to gate SHD output.
Voice signals on the loop are transformed by the TA into
ground referenced signals. Since the TA output has a DC
offset it is necessary to AC couple the output to any external
circuitry. Note, that during 4-wire to 2-wire transmission, the
transversal amplifier will have an audio signal at its output
proportional to the 4-wire audio receive signal and the loop's
equivalent AC impedance. This is called the transhybrid
return, and must be cancelled (or balanced) out to prevent
an echo effect. Reference the Transhybrid Circuit section for
more information.
Loop Current Limiting
The maximum loop length for this application is a 533
load
across the feed amplifiers (24V
SUPPLY
- 8V
OVERHEAD
)/
30mA
MAX
loop current). However, on a short loop the line
resistance often approaches zero. Thus, a need exists to
control the maximum DC loop current that can flow around
the loop to prevent an excessive current drain from the
system battery. This limit is internally set to 30mA on the
HC5503. Figure 3 depicts the feedback network that
modifies the V
RF
voltage as a function of metallic current.
Figure 4 illustrates the loop current characteristics as a
function of line resistance.
As indicated above, the TA has a DC voltage output directly
proportional to the loop current. This voltage level is scaled
by R
19
and R
18
. The scaled level forms the `Metallic' input
to one side of a Transconductance Amplifier.
The reference input to this amplifier is generated in the bias
network, and is equivalent to 30mA. When the metallic input
exceeds the set reference level, the transconductance
amplifier sources current. This current will charge C
1
in
positive direction causing the V
RF
(Ring Feed) voltage to
approach the V
TF
(Tip Feed), effectively reducing the battery
feed across the loop which will limit the DC loop current. C
1
will continue to charge until an equilibrium level is attained at
I
LOOP
= I
LOOP
mA (Max). The time constant of this feedback
loop is set by R
21
(90k
) and C
1
which is nominally 0.33
F.
The V
RF
voltage level is also modified to reduce or control
loop current during ring line faults (e.g., ground or power line
crosses), and thermal overload. Figure 8 illustrates this. The
thermal and fault current circuitry works in parallel with the
transconductance amplifier.
Longitudinal Amplifier
The longitudinal amplifier is an operational amplifier
configured as a closed loop differential amplifier with a
nominal gain of 0.1. The output is a measure of any
imbalance between I
TIP
and I
RING
. The transfer function of
this amplifier is given by:
V
LONG
= 0.1(I
TIP
- I
RING
) 150.
The gain factor is much less than one since ring voltage (up
to 150V
PEAK
) can appear at the Ring or Ring Feed Sense
terminals and are attenuated to avoid exceeding the
common mode range of the longitudinal amplifier's input.
C
1
V
RF
V
TIP
R
B2
R
B1
V
RING
V
TF
TRANSVERSAL
AMP
V
TX
= -600 I
LOOP
V
B5
R
19
R
18
90K
-4V
V
B
/2
KV
TX
FOR KV
TX
< V
B5
I
GM
> 0,
RING
90K
A
VCL
= 2
1.8K
R
21
FEED
+
-
+
-
+
-
V
RF
V
TX
FIGURE 3. DC LOOP CURRENT CHARACTERISTICS
HC5503
9
The longitudinal amplifier's principal functions is Ring Trip
Detection. The output of the amplifier after being filtered by
R
20
and C
2
to attenuate AC signals is fed into a detector
whose output inhibits the ring relay driver to remove ringing
signals from the line in an off-hook condition, reference
Figure 8.
Ringing The Line
The Ring Command (RC) input is taken low during ringing.
This activates the ring relay driver (RD) output providing the
telephone is not off-hook or the line is not in a power denial
state. The ring relay connects the ring generator to the
subscriber loop. The ring generator output is usually an
80V
RMS
, 20Hz signal. The ring signal should not exceed
150V peak. Since the telephone ringer is AC coupled only
ring current will flow. This ringing current flows directly into
V
BAT
via a set of relay contacts. The high impedance
terminal RFS is provided so that the low impedance V
RF
node can be isolated from the hot end of the ring path in the
battery referenced ring scheme.
The AC ring current flowing in the subscriber circuit will be
sensed across R
B2
, and will give rise to an AC voltage at the
output of the longitudinal amplifier. R
20
and C
2
attenuate this
signal before it reaches the ring trip detector to prevent false
ring trip. C
2
is nominally set at 1.0
F.
When the subscriber goes off-hook, a DC path is established
between the output of the ring generator and the battery
ground or V
BAT
terminal. A DC longitudinal imbalance is
established since no tip feed current is flowing through the
tip feed resistors. The longitudinal amplifier output is driven
negative. Once it exceeds the ring trip threshold of the ring
trip detector, the logic circuitry is driven by GK to trip the ring
relay establishing an off-hook condition such that SHD will
become active as loop metallic current starts to flow.
In addition to its ability to be used for tip or ring injected
systems, the HC5503 can also be configured for systems
utilizing balanced ringing. The main advantage of balanced
ringing is that it tends to minimize cross coupling effects owing
to the differential nature of the ring tone across the line.
Figure 5 illustrates the sequence of events during ring trip with
ring synchronization for a tip injected ring system. Note that
owing to the 90 degree phase shift introduced by the low pass
filter (R
20
, C
2
) the RS pulse will occur at the most negative
point of the attenuated ring signal that is fed into the ring trip
detector. Hence, when DC conditions are established for
SHD, the AC component actually assists ring trip taking place.
For a ring side injected ring system, the RS pulse should
occur at the positive zero crossing of the ring signal as it
appears at RFS. If ring synchronization is not used, then the
RS pin should be held permanently to a logic high of 5V
nominally: ring trip will occur asynchronously with respect to
the ring voltage. Ring trip is guaranteed to take place within
three ring cycles after the telephone going off-hook.
It is recommended that an RC snubber network is placed
across the ring relay contacts to minimize inductive kick-
back effects from the telephone ringer. Typical values for
such a network are shown in Figure 10.
Transhybrid Circuit
The purpose of the transhybrid circuit is to remove the
receive signal (R
X
) from the transmit signal (T
X
), thereby
preventing an echo on the transmit side. This is
accomplished by using an external op amp (usually part of
the CODEC) and by the inversion of the signal from the
4-wire receive port (R
X
) to the 4-wire transmit port (T
X
).
Figure 6 shows the transhybrid circuit. Because the voltage
at R
X
is 180 degrees out of phase with the voltage at T
X
, the
input signal will be subtracted from the output signal if I
1
equals I
2
. Node analysis yields the following Equation:
The voltage at T
X
is the product of the 4-wire to 2-wire
(A
4-2
= 0.633) and 2-wire to 4-wire (A
2-4
= -1.0) voltage
gains, and is therefore equal to 0.633. The voltage at R
X
,
when taking into account the negative feedback through R
2
,
HC5503 I
LOOP
SATURATION
I
LOOP
(mA)
R
LOOP
(
)
533
0
20
30
R
LOOP
= R
B1
+ R
B2
+ Z
TF
+ Z
RF
+ R
LINE
+ R
SET
10
FIGURE 4. DC LOOP CURRENT CHARACTERISTICS
FIGURE 5. RING TIP SEQUENCE
150V
V
RING
150V
PEAK
,
MAX
>50
s
C
2
CHARGES
TO 0V
VALUE
RING RELAY
HAS TRIPPED
DC SHIFT OWING TO
DC CURRENT DIFFERENCE
BETWEEN I
TIP
AND I
RING
QUESCENT
SUBSCRIBER
GOES OFF-HOOK
RING
TRIP
THRESHOLD
0V
0V
5V
RS
V
C4
I
1
I
2
+
T
X
R
4
-------
R
X
R
3
--------
+
0
=
=
(EQ. 24)
HC5503
10
is the calculated value of 0.633 plus the feedback which is
1/4 T
X
(for matching to a 600
load, reference Equation 8).
The voltage at R
x
is calculated in Equation 25.
Substituting the values for T
X
and R
X
into Equation 24 and
setting the them equal to each other, the values of R3 and
R
4
can then be determined.
Setting the value of R
3
to 150k
sets the value of R
4
to be
200k
.
Notice that the input voltage for the incoming signal (I
1
) is
taken at R
X
, instead of the conventional method at the
CODEC (point A, Figure 6). This alternative method is used
because the tolerance effects of R
1
on the transhybrid
balance are eliminated.
Power Denial (PD)
Power denial limits power to the subscriber loop: it does not
power down the SLIC, i.e., the SLIC will still consume its
normal on-hook quiescent power during a power denial
period. This function is intended to "isolate" from the battery,
under processor control, selected subscriber loops during an
overload or similar fault status.
If
PD is selected, the logic circuitry inhibits RC and switches in
a current source to C
1
. The capacitor charges up to a nominal
-3.5V at which point it is clamped. Since tip feed is always at
-4V, the battery feed across the loop is essentially zero, and
minimum loop power will be dissipated if the circuit goes off-
hook. No signalling functions are available during this mode.
After power denial is released (
PD = 1), it will be several
hundred milliseconds (300ms) before the V
RF
output
reaches its nominal battery setting. This is due to the RC
time constant of R
21
and C
1
.
The Logic Network
The logic network utilizes I
2
L logic. All external inputs and
outputs are LS TTL compatible: the relay driver is an open
collector output that can sink 60mA with a V
CE
of 1V.
Figure 9 is a schematic of the combination logic within the
network. The external inputs RC (Relay Control) and
PD
(Power Denial) allow the switch controller to ring the line or
deny power to the loop, respectively. The Ring
Synchronization input (RS) facilitates switching of the ring
relay near a ring current zero crossing in order to minimize
inductive kickback from the telephone ringer.
Line Fault Protection
The subscriber loop can exist in a very hostile electrical
environment. It is often in close proximity to very high voltage
power lines, and can be subjected to lightning induced
voltage surges. The SLIC has to provide isolation between
the subscriber loop and the PBX/Key telephone system.
The most stringent line fault condition that the SLIC has to
withstand is that of the lightning induced surge.
The Intersil monolithic SLIC, in conjunction with a simple low
cost diode bridge, can achieve up to 450V of isolation
between the loop and switch. The level of isolation is a
function of the packaging technology and geometry together
with the chip layout geometries. One of the principal reasons
for using DI technology for fabricating the SLIC is that it
lends itself most readily to manufacturing monolithic circuits
for high voltage applications.
Figures 10 shows the application circuit for the HC5503. A
secondary protection diode bridge is indicated which
protects the feed amplifiers during a fault. Most line systems
will have primary protection networks. They often take the
form of a carbon block or arc discharge device. These limit
the fault voltage to less than 450V peak before it reaches the
line cards. Thus when a transient high voltage fault has
occurred, it will be transmitted as a wave front down the line.
The primary protection network must limit the voltage to
less than 450V.
The attenuated wave front will continue
down the line towards the SLIC. The feed amplifier outputs
appear to the surge as very low impedance paths to the
system battery. Once the surge reaches the feed resistors,
fault current will flow into or out of the feed amplifier output
stages until the relevant protection diodes switch on. Once
the necessary diodes have started to conduct all the fault
current will be handled by them.
If the user wishes to characterize SLIC devices under
simulated high voltage fault conditions on the bench, he
should ensure that the negative battery power supply has
sufficient current capability to source the negative peak
fault current and low series inductance. If this is not the
case, then the battery supply could be pulled more
negative and destroy the SLIC if the total (V
CC
+ V
BAT
)
voltage across it exceeds 75V.
R
X
0.633
1
4
---
0.633
(
)
0.474
=
=
(EQ. 25)
0.633
R
4
---------------
0.474
R
3
---------------
=
(EQ. 26)
HC5503
R
X
T
X
CODEC/
FILTER
I
1
I
2
V
0
+
-
V
IN
+
-
+
-
FIGURE 6. TRANSHYBRID CIRCUIT
R
1
R
3
R
4
R
5
R
2
A
150k
200k
HC5503
11
Pin Descriptions
28 PIN
PLCC
24 PIN
DIP/SOIC
SYMBOL
DESCRIPTION
2
1
TIP
An analog input connected to the TIP (more positive) side of the subscriber loop. Functions with the Ring
terminal to receive voice signals from the telephone and for loop monitoring purposes.
3
2
RING
An analog input connected to the RING (more negative) side of the subscriber loop. Functions with the Tip
terminal to receive voice signals from the telephone and for loop monitoring purposes.
4
3
RFS
Senses ring side of loop for ring trip detection. During ringing, the ring signal is inserted into the line at this
node and RF is isolated from RFS via a relay.
5
4
V
CC
Positive Voltage Source - Most positive supply. V
CC
is typically 5V.
6
5
C
1
Capacitor #1 - An external capacitor to be connected between this terminal and analog ground. Required for
proper operation of the loop current limiting function, and for filtering V
BAT
. Typical value is 0.3
F, 16V.
7
6
DG
Digital Ground - To be connected to zero potential and serves as a reference for all digital inputs and out-
puts on the SLIC microcircuit.
9
7
RS
Ring Synchronization Input - A TTL - compatible clock input. The clock should be arranged such that a pos-
itive pulse transition occurs on the zero crossing of the ring voltage source, as it appears at the RFS termi-
nal. For Tip side injected systems, the RS pulse should occur on the negative going zero crossing and for
Ring injected systems, on the positive going zero crossing. This ensures that the ring relay activates and
deactivates when the instantaneous ring voltage is near zero. If synchronization is not required, the pin
should be tied to 5V.
10
8
RD
Relay Driver - A low active open collector logic output. When enabled, the external ring relay is energized.
11
9
TF
Tip Feed - A low impedance analog output connected to the TIP terminal through a 150
feed resistor.
Functions with the RF terminal to provide loop current, feed voice signals to the telephone set, and sink
longitudinal current.
12
10
RF
Ring Feed - A low impedance analog output connected to the RING terminal through a 150
feed resistor.
Functions with the TF terminal to provide loop current, feed voice signals to the telephone set, and sink
longitudinal current.
13
11
V
BAT
Negative Voltage Source - Most negative supply. V
BAT
is typically -24V. Frequently referred to as "battery".
14
12
BG
Battery Ground - To be connected to zero potential. All loop current and some quiescent current flows into
this ground terminal.
16
13
SHD
Switch Hook Detection - A low active LS TTL - compatible logic output. This output is enabled for loop cur-
rents exceeding 10.5mA and disabled for loop currents less than 5mA.
18
15
PD
Power Denial - A low active TTL - Compatible logic input. When enabled, the switch hook detect (SHD) is
not necessarily valid, and the relay driver (RD) output is disabled.
19
16
RC
Ring Command - A low active TTL - Compatible logic input. When enabled, the relay driver (RD) output
goes low on the next high level of the ring sync (R
S
) input, as long as the SLIC is not in the power denial
state (PD = 0) or the subscriber is not already off-hook (SHD = 0).
25
21
R
X
Receive Input, Four Wire Side - A high impedance analog input which is internally biased. Capacitive coupling
to this input is required. AC signals appearing at this input deferentially drive the Tip feed and Ring feed termi-
nals, which in turn drive tip and ring through 150
of feed resistance on each side of the line.
26
22
C
2
Capacitor #2 - An external capacitor to be connected between this terminal and analog ground. This ca-
pacitor prevents false ring trip detection from occurring when longitudinal currents are induced onto the
subscriber loop from nearby power lines and other noise sources. Recommended value is 1.0
F, 20V. This
capacitor should be nonpolarized.
27
23
AG
Analog Ground - To be connected to zero potential and serves as a reference for the transmit output (TX)
and receive input (RX) terminals.
28
24
TX
Transmit Output, Four Wire Side - A low impedance analog output which represents the differential voltage
across Tip and Ring. Transhybrid balancing must be performed beyond this output to completely implement two
to four wire conversion. This output is unbalanced and referenced to analog ground. Since the DC level of this
output varies with loop current, capacitive coupling to the next stage is essential.
17
14
NC
Used during production testing. For proper operation of the SLIC, this pin should float.
1, 8, 15,
20, 21, 22,
23, 24
17, 18, 19,
20
NC
No internal connection.
NOTE: All grounds (AG, BG, and DG) must be applied before V
CC
or V
BAT
. Failure to do so may result in premature failure of the part. If a user
wishes to run separate grounds off a line card, the AG must be applied first.
HC5503
12
Functional Block Diagram
Pinouts
HC5503 (SOIC)
TOP VIEW
HC5503 (PLCC)
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
21
22
23
24
15
14
13
TIP
RING
C1
DG
RS
TF
RF
BG
TX
C2
N/C
N/C
AG
N/C
V
CC
R
X
N/C
RC
PD
N/C
SHD
RD
RFS
V
BAT
C1
DG
N/C
RS
RD
TF
RX
N/C
N/C
N/C
N/C
RC
RING
TIP
TX
AG
C2
N/C
RF
BG
N/C
SHD
N/C
PD
V
CC
N/C
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
RFS
V
BA
T
DIFF
AMP
LOOP
MONITORING
RING
CONTROL
2-WIRE
LOOP
SECONDARY
PROTECTION
LINE
DRIVERS
TIP
RING
V
BAT
V
BAT
PD
POWER DENIAL
RING
150
RF
BG
TF
TIP
RD
RC
RS
RING SYNC
RING COMMAND
RING
TRIP
SHD
TX
TRANSMIT
OUTPUT
RX
RECEIVE
INPUT
SLIC MICROCIRCUIT
1/2 RING
RELAY
V
BAT
RING
VOLTAGE
RFS
1/2 RING
RELAY
150
SWITCH HOOK
DETECTION
BATTERY
FEED
LOOP
CURRENT
LIMITER
-
+
+1
-1
FIGURE 7.
HC5503
13
Schematic Diagram
FIGURE 8. FUNCTIONAL SCHEMATIC
VB2
VB1
VB2
VB3
VB4
VB5
5V
IB1 IB2 IB3 IB4 IB5 IB6 IB7 IB8
V
BAT
IB9 IB10 IB11
V
CC
V
CC
A-100
TRANSV'L
I/V AMP
-
+
IB6
R
6
R
5
R
11
V
CC
R
7
R
8
R
10
R
9
R
22
R
23
R
3
R
4
R
1
R
2
R
16
R
15
VBAT
V
BAT
R
12
V
BAT
V
CC
A-200
LONG'L
I / V AMP
IB7
-
+
R
20
V
BAT
V
CC
A-400
TIP FEED
AMP
IB4
-
+
RING
FEED
SENSE
V
BAT
V
BAT
5V
VB4
IB8
RING TRIP DETECTOR
+
SWITCH HOOK
VB1
IB6
+
R
18
DETECTOR
V
CC
QD28
QD27
VBAT
-
+
-
GND SHORTS
CURRENT
LIMITING
IB1
VB3
THERMAL
LIMITING
VB5
STTL
AND LOGIC
INTERFACE
RFC
SH
GK
VB5
-
+
IB2
LOAD CURRENT
LIMITING
R
14
R
13
V
BAT
VBAT/2 REFERENCE
R
21
V
BAT
A-300
RING FEED
AMP
IB5
-
+
RING
RF
TIP
TF
12
3
4
2
11
RX
C2
V
BAT
BAT
ANA
DIG
V
CC
GND
GND
GND
25
26
13
14
27
7
5
V
CC
5V IB10
VBAT
PD
18
RC
SHD
NC
19
16
17
TX
C1
RS
RD
10
9
28
6
R
17
VB2
V
CC
R
19
V
BAT
QD3 QD36
VOLTAGE AND CURRENT
BIAS NETWORK
PLCC PIN NUMBERS SHOWN
HC5503
14
Overvoltage Protection and Longitudinal
Current Protection
The SLIC device, in conjunction with an external protection
bridge, will withstand high voltage lightning surges and
power line crosses.
High voltage surge conditions are as specified in Table 1.
The SLIC will withstand longitudinal currents up to a
maximum or 10mA
RMS
, 5mA
RMS
per leg, without any
performance degradation.
FIGURE 9. LOGIC NETWORK
Schematic Diagram
(Continued)
LOGIC GATE SCHEMATIC
15
5
6
12
4
16
13
A
B
C
C
B
A
TTL
TO
STTL
TTL
TO
STTL
TTL
TO
STTL
TO
R
21
SHD
RD
PD
RC
RS
TTL
TO
STTL
RELAY
DRIVER
SH
GK
11
14
9
7
8
10
2
1
SCHOTTKY LOGIC
TABLE 1.
PARAMETER
TEST
CONDITION
PERFORMANCE
(MAX)
UNITS
Longitudinal
Surge
10
s Rise/
1000
s Fall
450 (Plastic)
V
PEAK
Metallic Surge
10
s Rise/
1000
s Fall
450 (Plastic)
V
PEAK
T/GND
R/GND
10
s Rise/
1000
s Fall
450 (Plastic)
V
PEAK
50/60Hz Current
T/GND
R/GND
11 Cycles
Limited to
10A
RMS
315 (Plastic)
V
RMS
HC5503
15
Application Circuit
NOTES:
6. R
5
sets the 2-wire to 4-wire gain. R
5
= 150k
then A
2-4
= 0dB. R
5
= 75k
then A
2-4
= -6.0dB.
7. Secondary protection diode bridge recommended is a 2A, 200V type.
8. All grounds (AG, BG, and DG) must be applied before V
CC
or V
BAT
. Failure to do so may result in premature failure of the part. If a user wishes
to run separate grounds off a line card, the AG must be applied first.
9. Application shows Ring Injected Ringing, Balanced or Tip injected configuration may be used.
FIGURE 10. -24V APPLICATION CIRCUIT
Typical Component Values:
C
1
= 0.33
F, 20%, 20V.
C
2
= 1.0
F, 10%, 20V.
C
3
= C
4
= 0.47
F, 20%, 30V.
C
5
, C
6
= 0.01
F, 30V.
C
S1
= C
S2
= 0.1
F, 200V typically, depending on V
RING
and
line length.
R
B1
= R
B2
= 150 (1% absolute value).
R
S1
= R
S2
= 1k
, 1%, 1/4W.
R
1
= 10k
, 1%, 1/4W.
R
2
= 24.9k
, 1%, 1/4W.
R
3
= R
5
= 150k
, 1%, 1/4W.
R
4
= 200k
, 1%, 1/4W.
D
1
, D
2
, D
3
, D
4
, D
5
= 1N40007, 100V, 3A.
Z
1
= 250V to 350V transient protection.
PTC used as ring generator ballast.
R
B1
R
B2
+5V
C
5
C
6
C
2
C
1
C
4
C
3
R
2
R
1
TIP
RING
V
CC
-24V
V
BAT
D
4
D
2
D
3
D
1
V
BAT
R
3
R
4
R
5
U2
V
OUT
28
6
26
5
27
7
14
13
12
11
10
16
18
9
19
25
C
S1
R
S1
C
S2
R
S2
PTC
K
1B
K
1A
K
1
D
5
V
BAT
+5V
-24V
SYSTEM CONTROLLER
-24V
CODEC/FILTER
V
IN
(NOTE 6)
RC
RS
SHD
RING
TIP
TIP FEED
RING FEED SENSE
RING FEED
HC5503
PD
V
CC
C
2
C
1
RD
RX
T
X
AGND
DGND
BGND
-BAT
U1
3
4
2
(PINOUT FOR PLCC)
PRIMARY
PROTECTION
Z1
MUST LIMIT
INPUT VOLTAGE
TO LESS THAN
450V
HC5503
16
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
HC5503