1
September 2004
HFA1114
850MHz Video Cable Driving Buffer
FN3151.5
Features
Access to Summing Node Allows Circuit Customization
User Programmable For Closed-Loop Gains of +1, -1
or +2 Without Use of External Resistors
Wide -3dB Bandwidth . . . . . . . . . . . . . . . . . . . . 850MHz
Very Fast Slew Rate . . . . . . . . . . . . . . . . . . . . 2400V/
s
Fast Settling Time (0.1%) . . . . . . . . . . . . . . . . . . . 11ns
High Output Current . . . . . . . . . . . . . . . . . . . . . . . 60mA
Excellent Gain Accuracy. . . . . . . . . . . . . . . . . . 0.99V/V
Overdrive Recovery. . . . . . . . . . . . . . . . . . . . . . . <10ns
Standard Operational Amplifier Pinout
Applications
RF/IF Processors
Driving Flash A/D Converters
High Speed Communications
Impedance Transformation
Line Driving
Video Switching and Routing
Radar Systems
Medical Imaging Systems
Description
The HFA1114 is a closed loop Buffer featuring user
programmable gain and ultra high speed performance.
Manufactured on Intersil' proprietary complementary bipolar
UHF-1 process, the HFA1114 offers a wide -3dB bandwidth
of 850MHz, very fast slew rate, excellent gain flatness, low
distortion and high output current.
A unique feature of the pinout allows the user to select a
voltage gain of +1, -1, or +2, without the use of any external
components. Gain selection is accomplished via connections
to the inputs, as described in the "Application Information"
section. The result is a more flexible product, fewer part types
in inventory, and more efficient use of board space.
Compatibility with existing op amp pinouts provides flexibility
to upgrade low gain amplifiers, while decreasing component
count. Unlike most buffers, the standard pinout provides an
upgrade path should a higher closed loop gain be needed at
a future date.
For applications requiring a standard buffer pinout, please
refer to the HFA1110 datasheet.
Pinout
HFA1114 (SOIC)
TOP VIEW
Pin Descriptions
Part # Information
PART NUMBER
(BRAND)
TEMP. RANGE
(
o
C)
PACKAGE
PKG.
NO.
HFA1114IB
(H1114I)
-40 to 85
8 Ld SOIC
M8.15
HFA11XXEVAL
DIP Evaluation Board for High Speed
Op Amps
NC
-IN
+IN
V-
1
2
3
4
8
7
6
5
NC
V+
OUT
SN
+
-
300
300
NAME
PIN
NUMBER
DESCRIPTION
NC
1, 8
No Connection
-IN
2
Inverting Input
+IN
3
Non-Inverting Input
V-
4
Negative Supply
SN
5
Summing Node
OUT
6
Output
V+
7
Positive Supply
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002., 2004All Rights Reserved
OBSOL
ETE PR
ODUCT
POSSIB
LE SUB
STITUT
E PROD
UCT
HFA111
2
2
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SUPPLY
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
170
Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . . 175
o
C
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V
SUPPLY
=
5V, A
V
= +1, R
L
= 100
,
Unless Otherwise Specified
PARAMETER
TEST
CONDITIONS
TEMP.
(
o
C)
MIN
TYP
MAX
UNITS
INPUT CHARACTERISTICS
Output Offset Voltage
25
-
8
25
mV
Full
-
-
35
mV
Output Offset Voltage Drift
Full
-
10
-
V/
o
C
PSRR
25
39
45
-
dB
Full
35
-
-
dB
Input Noise Voltage
100kHz
25
-
9
-
nV/
Hz
Non-Inverting Input Noise Current
100kHz
25
-
37
-
pA/
Hz
Non-Inverting Input Bias Current
25
-
25
40
A
Full
-
-
65
A
Non-Inverting Input Resistance
25
25
50
-
k
Inverting Input Resistance
25
240
300
360
Input Capacitance
Either Input
25
-
2
-
pF
Input Common Mode Range
Full
2.5
2.8
-
V
TRANSFER CHARACTERISTICS
Gain
A
V
= +1, V
IN
= +2V
25
0.980
0.990
1.02
V/V
Full
0.975
-
1.025
V/V
A
V
= +2, V
IN
= +1V
25
1.96
1.98
2.04
V/V
Full
1.95
-
2.05
V/V
DC Non-Linearity
A
V
= +2,
2V Full Scale
25
-
0.02
-
%
OUTPUT CHARACTERISTICS
Output Voltage
A
V
= -1
25
3.0
3.3
-
V
Full
2.5
3.0
-
V
Output Current
A
V
= -1, R
L
= 50
25, 85
50
60
-
mA
-40
o
C
35
50
-
mA
Closed Loop Output Impedance
A
V
= +2, DC
25
-
0.3
-
HFA1114
3
POWER SUPPLY CHARACTERISTICS
Supply Voltage Range
Full
4.5
-
5.5
V
Supply Current
25
-
21
26
mA
Full
-
-
33
mA
AC CHARACTERISTICS
-3dB Bandwidth (V
OUT
= 0.2V
P-P
)
A
V
= -1
25
-
800
-
MHz
A
V
= +1
25
-
850
-
MHz
A
V
= +2
25
-
550
-
MHz
Slew Rate (V
OUT
= 5V
P-P
)
A
V
= -1
25
-
2400
-
V/
s
A
V
= +1
25
-
1500
-
V/
s
A
V
= +2
25
-
1900
-
V/
s
Full Power BW
5V
P-P
, A
V
= +2
25
-
220
-
MHz
Gain Flatness
To 30MHz, A
V
= +2
25
-
0.015
-
dB
Gain Flatness
To 100MHz, A
V
= +2
25
-
0.07
-
dB
2nd Harmonic Distortion
50MHz, V
OUT
= 2V
P-P
25
-
-53
-
dBc
3rd Harmonic Distortion
50MHz, V
OUT
= 2V
P-P
25
-
-68
-
dBc
3rd Order Intercept
100MHz, A
V
= +2
25
-
28
-
dBm
1dB Compression
100MHz, A
V
= +2
25
-
19
-
dBm
Rise Time (V
OUT
= 0.5V Step)
A
V
= +2
25
-
700
-
ps
A
V
= +1
25
-
480
-
ps
Overshoot
V
OUT
= 0.5V Step, A
V
= +2
25
-
6
-
%
0.1% Settling Time
V
OUT
= 2V to 0V
25
-
11
-
ns
0.05% Settling Time
V
OUT
= 2V to 0V
25
-
15
-
ns
Overdrive Recovery Time
25
-
8.5
-
ns
Differential Gain
A
V
= +1, 3.58MHz, R
L
= 150
25
-
0.03
-
%
A
V
= +2, 3.58MHz, R
L
= 150
25
-
0.02
-
%
Differential Phase
A
V
= +1, 3.58MHz, R
L
= 150
25
-
0.05
-
Degrees
A
V
= +2, 3.58MHz, R
L
= 150
25
-
0.04
-
Degrees
Electrical Specifications
V
SUPPLY
=
5V, A
V
= +1, R
L
= 100
,
Unless Otherwise Specified (Continued)
PARAMETER
TEST
CONDITIONS
TEMP.
(
o
C)
MIN
TYP
MAX
UNITS
HFA1114
4
Application Information
Closed Loop Gain Selection
The HFA1114 features a novel design which allows the user
to select from three closed loop gains, without any external
components. The result is a more flexible product, fewer part
types in inventory, and more efficient use of board space.
This "buffer" operates in closed loop gains of -1, +1, or +2, and
gain selection is accomplished via connections to the
inputs.
Applying the input signal to +IN and floating -IN selects a gain
of +1, while grounding -IN selects a gain of +2. A gain of -1 is
obtained by applying the input signal to -IN with +IN grounded.
The table below summarizes these connections:
PC Board Layout
The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board. The
use of low inductance components such as chip resis-
tors and chip capacitors is strongly recommended,
while a solid ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10
F) tantalum in parallel with a small value
(0.1
F) chip capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the input
and output of the device. Capacitance directly on the output must
be minimized, or isolated as discussed in the next section.
For unity gain applications, care must also be taken to minimize
the capacitance to ground seen by the amplifier's inverting
input. At higher frequencies this capacitance will tend to short
the -INPUT to GND, resulting in a closed loop gain which
increases with frequency. This will cause excessive high
frequency peaking and potentially other problems as well.
An example of a good high frequency layout is the Evaluation
Board shown in Figure 2.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier's phase
margin resulting in frequency response peaking and possible oscil-
lations. In most cases, the oscillation can be avoided by placing a
resistor (R
S
) in series with the output prior to the capacitance.
Figure 1 details starting points for the selection of this resis-
tor. The points on the curve indicate the R
S
and C
L
combina-
tions for the optimum bandwidth, stability, and settling time,
but experimental fine tuning is recommended. Picking a
point above or to the right of the curve yields an overdamped
response, while points below or left of the curve indicate
areas of underdamped performance.
R
S
and C
L
form a low pass network at the output, thus
limiting system bandwidth well below the amplifier band-
width of 850MHz. By decreasing R
S
as C
L
increases (as
illustrated in the curves), the maximum bandwidth is
obtained without sacrificing stability. Even so, bandwidth
does decrease as you move to the right along the curve.
For example, at A
V
= +1, R
S
= 50
, C
L
= 30pF, the over-
all bandwidth is limited to 300MHz, and bandwidth drops
to 100MHz at A
V
= +1, R
S
= 5
, C
L
= 340pF.
Evaluation Board
The performance of the HFA1114 may be evaluated using
the HFA11XX Evaluation Board, slightly modified as follows:
2. Remove the 500
feedback resistor (R
2
), and leave the
connection open.
3. a. For A
V
= +1 evaluation, remove the 500
gain setting
resistor (R
1
), and leave pin 2 floating.
b. For A
V
= +2, replace the 500
gain setting resistor with
a 0
resistor to GND.
4. Isolate Pin 5 from the stray board capacitance to minimize
peaking and overshoot.
The layout and modified schematic of the board are shown in
Figure 2.
To order evaluation boards (part number HFA11XXEVAL),
please contact your local sales office.
Note: The SOIC version may be evaluated in the DIP board by
using a SOIC-to-DIP adapter such as Aries Electronics Part
Number 08-350000-10.
GAIN
(A
CL
)
CONNECTIONS
+INPUT (PIN 3)
-INPUT (PIN 2)
-1
GND
Input
+1
Input
NC (Floating)
+2
Input
GND
R
S
(
)
LOAD CAPACITANCE (pF)
50
45
40
35
30
25
20
15
10
5
0
0
40
80
120 160 200 240
280 320
360 400
A
V
= +1
A
V
= +2
FIGURE 1. RECOMMENDED SERIES OUTPUT RESISTOR vs
LOAD CAPACITANCE
1
2
3
4
8
7
6
5
+5V
10
F
0.1
F
V
H
50
GND
GND
R
1
-5V
0.1
F
10
F
50
IN
OUT
V
L
(A
V
= +1)
or 0
(A
V
= +2)
V
H
+IN
V
L
V+
GND
1
V-
OUT
TOP LAYOUT
BOTTOM LAYOUT
X
FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT
HFA1114
5
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Die Characteristics
DIE DIMENSIONS:
63 mils x 44 mils x 19 mils
1600
m x 1130
m x
483
m
METALLIZATION:
Type: Metal 1: AICu(2%)/TiW
Thickness: Metal 1: 8k
0.4k
Type: Metal 2: AICu(2%)
Thickness: Metal 2: 16k
0.8k
PASSIVATION:
Type: Nitride
Thickness: 4k
0.5k
TRANSISTOR COUNT:
52
SUBSTRATE POTENTIAL (Powered Up):
Floating (Recommend Connection to V-)
Metallization Mask Layout
HFA1114
NC
V-
NC
SN
OUT
+IN
-IN
NC
V+
HFA1114
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