1
August 1997
HI1171
8-Bit, 40 MSPS, High Speed D/A Converter
Features
Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . . 40MHz
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit
Integral Linearity Error . . . . . . . . . . . . . . . . . . 0.25 LSB
Low Glitch Noise
Single Supply Operation . . . . . . . . . . . . . . . . . . . . . . +5V
Low Power Consumption (Max) . . . . . . . . . . . . . .80mW
Evaluation Board Available (HI1171-EV)
Direct Replacement for the Sony CXD1171
Applications
Wireless Telecommunications
Signal Reconstruction
Direct Digital Synthesis
Imaging
Presentation and Broadcast Video
Graphics Displays
Signal Generators
Description
The HI1171 is an 8-bit, 40MHz, high speed D/A converter.
The converter incorporates an 8-bit input data register with
blanking capability, and current outputs. The HI1171 fea-
tures low glitch outputs. The architecture is a current cell
arrangement to provide low linearity errors.
The HI1171 is available in an Industrial temperature range
and is offered in a 24 lead (200 mil) SOIC plastic package.
For dual version, please refer to the HI1177 Data Sheet.
For triple version, please refer to the HI1178 Data Sheet.
Ordering Information
PART
NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
PKG. NO.
HI1171JCB
-40 to 85
24 Ld SOIC
M24.2-S
HI1171-EV
25
Evaluation Board
Pinout
HI1171
(SOIC)
TOP VIEW
Typical Application Circuit
1
2
3
4
5
6
7
8
9
10
11
12
(LSB) D0
D1
D2
D3
D4
D5
D6
D7
BLNK
DV
SS
V
B
CLK
16
17
18
19
20
21
22
23
24
15
14
13
DV
DD
AV
DD
I
OUT2
I
OUT1
AV
DD
VG
I
REF
AV
SS
DV
SS
DV
DD
AV
DD
V
REF
D7 (MSB)(8)
D6 (7)
D5 (6)
D4 (5)
D3 (4)
D2 (3)
D1 (2)
D0 (LSB) (1)
D7
D6
D5
D4
D3
D2
D1
D0
+5V
DV
DD
(23, 24)
0.1
F
DV
SS
(10, 13)
CLK (12)
BLNK (9)
+5V
0.1
F
(18, 19, 22) AV
DD
(14) AV
SS
D/A
(20) I
OUT1
(21) I
OUT2
(15) I
REF
V
B
(11)
0.1
F
3.3k
200
0.1
F
1k
(17) V
G
(16) V
REF
HI1171
OUT
File Number
3662.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
2
Functional Block Diagram
DECODER
DECODER
8-BIT
LATCH
CLOCK
GENERATOR
6 MSBs
CURRENT
CELLS
CURRENT CELLS
(FOR FULL SCALE)
BIAS VOLTAGE
GENERATOR
2 LSBs
CURRENT
CELLS
+
-
I
REF
V
REF
VG
I
OUT1
I
OUT2
(LSB) D0
D1
D2
D3
D4
D5
D6
(MSB) D7
BLNK
VB
CLK
HI1171
3
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage DV
DD
to DV
SS
. . . . . . . . . . . . . . . . . . . +7.0V
Analog Supply Voltage AV
DD
to AV
SS
. . . . . . . . . . . . . . . . . . +7.0V
Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DD
to V
SS
V
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0mA to 15mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
98
Maximum Junction Temperature, Plastic Package . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AV
DD
= +4.75V to +5.25V, DV
DD
= +4.75 to +5.25V, V
REF
= +2.0V, f
S
= 40MHz,
CLK Pulse Width = 12.5ns, T
A
= 25
o
C (Note 4)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM PERFORMANCE
Resolution, n
-
8
-
Bits
Integral Linearity Error, INL
f
S
= 40MHz (End Point)
-0.5
-
1.3
LSB
Differential Linearity Error, DNL
f
S
= 40MHz
-
-
0.25
LSB
Offset Error, V
OS
(Note 2)
-
-
1
mV
Full Scale Error, FSE (Adjustable to Zero)
(Note 2)
-
-
13
LSB
Full Scale Output Current, I
FS
-
10
15
mA
Full Scale Output Voltage, V
FS
1.9
2.0
2.1
V
Output Voltage Range, V
FSR
0.5
2.0
2.1
V
DYNAMIC CHARACTERISTICS
Throughput Rate
See Figure 7
40.0
-
-
MHz
Glitch Energy, GE
R
OUT
= 75
-
30
-
pV-s
Differential Gain,
A
V
(Note 3)
-
1.2
-
%
Differential Phase,
(Note 3)
-
0.5
-
Degree
REFERENCE INPUT
Voltage Reference Input Range
0.5
-
2.0
V
Reference Input Resistance
(Note 3)
1.0
-
-
M
DIGITAL INPUTS
Input Logic High Voltage, V
IH
(Note 3)
3.0
-
-
V
Input Logic Low Voltage, V
IL
(Note 3)
-
-
1.5
V
Input Logic Current, I
IL
, I
IH
(Note 3)
-
-
5.0
A
Digital Input Capacitance, C
IN
(Note 3)
-
5.0
-
pF
TIMING CHARACTERISTICS
Data Setup Time, t
SU
See Figure 1
5
-
-
ns
Data Hold Time, t
HLD
See Figure 1
10
-
-
ns
HI1171
4
Propagation Delay Time, t
PD
See Figure 9
-
10
-
ns
Settling Time, t
SET
(to
1
/
2
LSB)
See Figure 1
-
10
15
ns
CLK Pulse Width, t
PW1
, t
PW2
See Figure 1
12.5
-
-
ns
POWER SUPPLY CHARACTERISITICS
IAV
DD
14.3MHz, at Color Bar Data Input
-
10.9
11.5
mA
IDV
DD
14.3MHz, at Color Bar Data Input
-
4.2
4.8
mA
Power Dissipation
200
load at 2V
P-P
Output
-
-
80
mW
NOTES:
2. Excludes error due to external reference drift.
3. Parameter guaranteed by design or characterization and not production tested.
4. Electrical specifications guaranteed only under the stated operating conditions.
Electrical Specifications
AV
DD
= +4.75V to +5.25V, DV
DD
= +4.75 to +5.25V, V
REF
= +2.0V, f
S
= 40MHz,
CLK Pulse Width = 12.5ns, T
A
= 25
o
C (Note 4) (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Timing Diagram
FIGURE 1.
CLK
DATA
D/AOUT
100%
50%
0%
t
PW1
t
PW2
t
SU
t
HLD
t
SU
t
SU
t
PD
t
PD
t
PD
t
HLD
t
HLD
HI1171
5
Typical Performance Curves
FIGURE 2. OUTPUT FULL SCALE VOLTAGE vs REFERENCE
VOLTAGE
FIGURE 3. OUTPUT RESISTANCE vs GLITCH ENERGY
FIGURE 4. OUTPUT FULL SCALE VOLTAGE vs AMBIENT TEMPERATURE
Pin Descriptions
24 PIN
SOIC
PIN
NAME
PIN DESCRIPTION
1-8
D0(LSB) thru
D7(MSB)
Digital Data Bit 0, the Least Significant Bit thru Digital Data Bit 7, the Most Significant Bit.
9
BLNK
Blanking Line, used to clear the internal data register to the zero condition when High, normal operation
when Low.
10, 13
DV
SS
Digital Ground.
11
VB
Voltage Bias, connect a 0.1
F capacitor to DV
SS
.
12
CLK
Data Clock Pin 100kHz to 40MHz.
14
AV
SS
Analog Ground.
15
I
REF
Current Reference, used to set the current range. Connect a resistor to AV
SS
that is 16 times greater
than the resistor on I
OUT1
. (See Typical Applications Circuit).
16
V
REF
Input Reference Voltage used to set the output full scale range.
2
1
1
2
V
DD
= 5.0V, R = 200
16R = 3.3k
, T
A
= 25
o
C
OUTPUT FULL SCALE V
O
L
T
A
GE (V)
REFERENCE VOLTAGE (V)
100
200
100
200
OUTPUT RESISTANCE (
)
GLITCH ENERGY (pV/s)
2.0
1.9
0
-25
0
25
50
75
V
DD
= 5.0V, V
REF
= 2.0V
R = 200
,
16R = 3.3k
T
A
= 25
o
C
OUTPUT FULL SCALE V
O
L
T
A
GE (V)
AMBIENT TEMPERATURE (
o
C)
HI1171
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