4-1
October 1997
HI2559, CXD2559
1-Bit D/A Converter For Audio Application
Features
Two-Channel D/A Converter and Oversampling Digital
Filter Into a Single Chip
Distortion . . . . . . . . . . . . . . . . . . . . . . . . 0.012% or Less
S/N Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . .96dB or More
Master Clock . . . . . . . . . . . . . . . . . . . . . 384F
S
or 256F
S
Applications
CD Player and CD-ROM Player, etc.
Functions
Data Can Be Input at Rate of 1 x F
S
with a Built-In Digital
Filter
The 24-/32-Slot Serial Data Interface Enables
Independent Selection of Data Frontward Trunca-
tion/Rearward Truncation and MSB First/LSB First
Two Channels Can Be Attenuated Independently in 255
Steps
The Output From Two Channels (L/R/L + R/Mute) Can
Be Selected Independently
Digital Emphasis
Description
The HI2559, CXD2559 is a 1-bit stereo D/A converter featur-
ing a 2nd-order
system noise shaper. This good cost per-
formance LSI has functions such as digital attenuator and
digital de-emphasis and others.
Pinout
HI2559, CXD2559
(MQFP)
TOP VIEW
Ordering Information
PART
NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG. NO.
HI2559JCQ
-20 to 75
32 Ld MPQF
Q32.7x7-S
CXD2559Q
-20 to 75
32 Ld MPQF
Q32.7x7-S
WO
LA
TC
H
SH
I
F
T
AT
T
ML
S
L
SI
N
BCK
L
RCK
AO
UT
1
+
AV
SS
2
XV
DD
XT
L
O
XT
L
I
XV
SS
AV
SS
3
AO
UT
2
+
AV
DD0
AOUT2-
AV
SS0
DV
DD0
TEST
CLR
MASL
DV
SS0
AV
DD1
AOUT1-
AV
SS1
DV
SS1
XCLK
DASL0
DASL1
DV
DD1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
17
18
19
20
21
22
23
24
3231 30 29 28 27 26 25
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002. All Rights Reserved
File Number
4120.1
NOT
REC
OMM
END
ED F
OR N
EW D
ESIG
NS
4-2
Block Diagram
DIGITAL
FILTER
(OVER SAMPLING)
CLOCK GENERATOR
TIMING CIRCUIT
LRCK
BCK
SIN
MASL
MLSL
ATT
SHIFT
LATCH
S
P
HOST
COMPUTER
I/F
XTLI
XTLO
XCLK
DAC1
DAC2
AOUT1 (+)
AOUT1 (-)
AOUT2 (+)
AOUT2 (-)
ROM
ATT1
ATT2
RAM
Pin Descriptions
PIN NO.
SYMBOL
I/O
DESCRIPTION
1
AV
DD0
-
Analog power supply for Channel 2 output.
2
AOUT2()
O
Analog reversed phase output for Channel 2.
3
ADV
SS0
-
Analog GND for Channel 2 output.
4
DV
DD0
-
Digital power supply.
5
TEST
I
IC measurement. Fixed to Low.
6
CLR
I
System clear input. Cleared when low. Equipped with a pull-up resistor.
7
MASL
I
Selects whether 16-bit serial data is placed in the first 16-bit or the second 16-bit slot of the
serial IN 32-bit slots. Frontward truncation when High; rearward truncation when low.
Equipped with a pulldown resistor.
8
DV
SS0
-
Digital GND.
9
LRCK
I
Serial IN sampling frequency clock. Transfers Channel-1 data when High; Channel-2 data
when low.
10
BCK
I
Serial bit transfer clock 48 F
S
or 64 F
S
in serial IN. The serial input data is retrieved at the
rising edge.
11
SIN
I
Two channels per sampling serial data input. Data format is represented by 2's comple-
ments, and consists of 24-bit or 32-bit slots.
12
MLSL
I
Selects whether 16-bit serial data SIN (Pin 15) of serial IN at LSB first or MSB first. MSB-
first when High; LSB-first when Low. Equipped with a pull-up resistor.
HI2559, CXD2559
4-3
13
ATT
I
Data input of the microcomputer interface. Attenuation data, output selection setting value,
and de-emphasis on/off data re-input in serial mode.
14
SHIFT
I
Shift clock input of the microcomputer interface.
15
LATCH
I
Latch input of the microcomputer interface. Latched at the rising edge.
16
WO
I
Synchronization window control. Window open when Low (forced synchronization).
17
DV
DD1
-
Digital power supply.
18
DASL1
I
IC measurement. Fixed to Low.
19
DASL0
I
IC measurement. Fixed High.
20
XCLK
O
Inversion output of the clock input from XTLI (Pin 1).
21
DV
SS1
-
Digital GND.
22
AV
SS1
-
Analog GND for Channel 1 output.
23
AOUT1 (-)
O
Analog reversed phase output for Channel 1.
24
AV
DD1
I
Analog power supply for Channel 1 output.
25
AOUT1 (+)
O
Analog positive phase output for Channel 1.
26
AV
SS2
-
Analog GND for Channel 1 output.
27
XV
DD
-
Digital power supply for the master clock.
28
XTLO
O
Crystal oscillator output. Connects the master clock 256 F
S
or 384 F
S
crystal oscillator,
which is identified automatically.
29
XTLI
I
Crystal oscillator input. Connects the master clock 256 F
S
or 384 F
S
crystal oscillator,
which is identified automatically. External clock pulse is input at this pin.
30
XV
SS
-
Digital GND for master clock
31
AV
SS3
-
Analog GND for Channel 2 output.
32
AOUT2 (+)
O
Analog positive phase output for Channel 2.
Pin Descriptions
(Continued)
PIN NO.
SYMBOL
I/O
DESCRIPTION
HI2559, CXD2559
4-4
Absolute Maximum Ratings
T
A
= 25
o
C, V
SS
= 0V
Operating Conditions
Supply Voltage (V
DD
). . . . . . . . . . . . . . . . . . . . . . V
SS
-0.5V to 7.0V
Input Voltage (V
1
). . . . . . . . . . . . . . . . . . . . V
SS
-0.5V to V
DD
+0.5V
Output Voltage (V
0
) . . . . . . . . . . . . . . . . . . V
SS
- 0.5V to V
DD
+0.5V
Operating Temperature (TOPR). . . . . . . . . . . . . . . . . -20
o
C to 75
o
C
Storage Temperature (T
STG
) . . . . . . . . . . . . . . . . . . -55
o
C to 150
o
C
Supply Voltage (V
DD
) . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
Operating Temperature (T
A
) . . . . . . . . . . . . . . . . . . . . 20
o
C to 75
o
C
Sampling Frequency (F
S
) . . . . . . . . . . . . . . . . . . . . . 7kHz to 50kHz
Input/Output Capacitance
Input Pin (C
IN
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9pF (Max.)
Output Pin (C
OUT
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11pF (Max.)
Measurement conditions: V
DD
= V
I
= 0V, f = 1MHz
Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNITS
APPLICABLE
PIN
DC Electrical Specifications
Input Voltage
V
IH
0.7 V
DD
-
-
V
Note 1
V
IL
-
-
0.3 V
DD
V
IH
2.2
-
-
V
Note 2
V
IL
Output Voltage
V
OH
I
OH
= -2mA
V
DD
-0.8
-
0.4
V
Note 3
V
OL
I
OL
= 4mA
-
-
0.4
V
OH
I
OH
= -1mA
V
DD
/2
-
-
V
Note 4
V
OL
I
OL
= 1mA
-
-
V
DD
/2
V
OH
I
OH
= -4mA
V
DD
-0.8
-
-
V
Note 5
V
OL
I
OL
= 4mA
0
-
-
Input Leakage Current 1
I
IL1
V
IN
= V
SS
or V
DD
-10
-
10
A
Note 6
Input Leakage Current 2
I
IL2
V
IN
= V
SS
or V
DD
-40
-
40
A
Note 7
Input Leakage Current 3
I
IL
V
IL
= V
SS
-40
-100
-240
A
Note 8
Input Leakage Current 4
I
IH
V
IH
= V
DD
40
100
240
A
Note 9
Feedback Resistance
R
FB
V
IN
= V
SS
or V
DD
250k
1M
2.5M
Note 12
NOTES:
1. Input pins except for *2t
2. ATT, SHIFT, LATCH
3. XCLK
4. XLO
5. AOUT1 (+), AOUT1 (-), AOUT2 (+), AOUT2 (-)
6. ATT, SHIFT, LATCH, LRCK, BCK, SINt
7. WO
8. CLR, MLSLt
9. MASL
10. XTLI
AC Electrical Specifications
V
DD
= 5.0
10%, TOPR = -20
o
C to 75
o
C
PARAMETER
SYMBOL
Oscillation Frequency
256 F
S
fx
2
-
13
MHz
384 F
S
2
-
20
External Clock Pulse Input
High Level Width
258 F
S
t
CWH
38
-
250
ns
384 F
S
25
-
250
ns
HI2559, CXD2559
4-5
External Clock Pulse Input
Low Level Width
256 F
S
t
CWL
38
-
250
ns
384 F
S
25
-
250
ns
External Clock Pulse Input
Pulse Cycle (Note 2)
256 F
S
t
CYC
76
-
500
ns
384 F
S
50
-
500
ns
Input BCK Frequency
f
BCK
-
-
3.1
MHz
Input BCK Pulse Width
t
WIB
100
-
-
ns
Input Data Setup Time
t
IDS
10
-
-
ns
Input Data Hold Time
t
IDH
15
-
-
ns
Input LRCK Setup Time
t
ILRS
10
-
-
ns
Input LRCK Hold Time
t
ILRH
15
-
-
ns
Program Input Basic Time
t
PR
100
-
-
ns
Latch Input Pulse Width
t
WLT
200
-
-
ns
ATT Setup Time
t
SET
5
-
-
ns
ATT Hold Time
t
HOLD
100
-
-
ns
ATT Interval
t
INT
300
-
-
ns
NOTE:
11. Always input an external clock after turning the power on.
ANALOG CHARACTERISTICS
MEASUREMENT CONDITIONS
T
A
= 25
o
C, V
DD
= 5.0V, F
S
= 44kHz, signal frequency = 1kHz, measurement band = 4Hz to 20kHz,
Master Clock 384F
S
.
S/N
(EIAJ) *1
96
100
-
dB
THD + N
(EIAJ)
-
0.010
0.012
%
Dynamic Range
(EIAJ) *1, *2
91
93
-
dB
Channel Separation
(EIAJ)
-
90
-
dB
Output Level
-
2.58
-
V (ms)
Gain Difference Between Channels
-
-
0.1
dB
NOTES:
12. A-weighting filter used.
13. -60dB, 1kHz input.
AC Electrical Specifications
V
DD
= 5.0
10%, TOPR = -20
o
C to 75
o
C
PARAMETER
SYMBOL
HI2559, CXD2559
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