3-1
TM
HI5628
8-Bit, 125/60MSPS, Dual High Speed
CMOS D/A Converter
The HI5628 is an 8-bit, dual 125MSPS D/A converter which
is implemented in an advanced CMOS process. Operating
from a single +5V to +3V supply, the converter provides
20.48mA of full scale output current and includes an input
data register. Low glitch energy and excellent frequency
domain performance are achieved using a segmented
architecture. The single DAC version is the HI5660 while
10-bit versions exist in the HI5760 and HI5728. This DAC is
a member of the CommLinkTM family of communication
devices.
Features
Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . 125MSPS
Low Power . . . . . . . . . . . . . . 330mW at 5V, 170mW at 3V
Integral Linearity Error . . . . . . . . . . . . . . . . . . .
0.25 LSB
Differential Linearity . . . . . . . . . . . . . . . . . . . . .
0.25 LSB
Channel Isolation (Typ). . . . . . . . . . . . . . . . . . . . . . . 80dB
SFDR to Nyquist at 10MHz Output . . . . . . . . . . . . 60dBc
Internal 1.2V Bandgap Voltage Reference
Single Power Supply from +5V to +3V
CMOS Compatible Inputs
Excellent Spurious Free Dynamic Range
Applications
Direct Digital Frequency Synthesis
Wireless Communications
Signal Reconstruction
Arbitrary Waveform Generators
Test Equipment
High Resolution Imaging Systems
Pinout
HI5628 (LQFP)
Ordering Information
PART
NUMBER
TEMP.
RANGE
(
o
C)
PACKAGE
PKG. NO.
MAX
CLOCK
SPEED
HI5628IN
-40 to 85 48 Ld LQFP
Q48.7x7A 125MHz
HI5628/6IN
-40 to 85 48 Ld LQFP
Q48.7x7A 60MHz
HI5628EVAL1
25
Evaluation Platform
125MHz
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
9
10
11
12
13 14 15 16
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
QD4
QD3
QD2
QD1
QD0 (LSB)
DGND
DGND
DV
DD
DGND
NC
AV
DD
AGND
ID4
ID3
ID2
ID1
ID0 (LSB)
SLEEP
DV
DD
DGND
NC
AV
DD
DGND
DGND
ID5
ID6
ID7 (MSB)
DV
DD
DGND
QCLK
DGND
DV
DD
QD7 (MSB)
QD6
QD5
ICLK
A
GND
ICOMP1
REFLO
IOUT
A
IOUTB
A
GND
A
GND
QOUTB
QOUT
A
FSADJ
REFIO
QCOMP1
Data Sheet
September 2000
File Number
4520.5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Corporation.
|
Copyright Intersil Corporation 2000
CommLinkTM is a trademark of Intersil Corporation.
3-2
Typical Applications Circuit
NOTE: Recommended separate analog and digital ground planes, connected at a single point near the device. See AN9827.
IOUTB
IOUTA
50
+5V TO +3V (SUPPLY)
0.1
F
50
10
F
50
0.1
F
1.91k
FERRITE
10
H
+
BEAD
R
SET
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
9
10
11
12
13 14 15 16
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
AV
DD
ID5
ID4
ID3
ID6
ID7 (MSB)
QD7 (MSB)
ID2
ID1
ID0 (LSB)
QD6
QD5
QD4
QD3
QD2
QD1
QD0 (LSB)
I
CLK
/Q
CLK
DV
DD
0.1
F
DV
DD
SLEEP
DV
DD
0.1
F
DVDD
DGND
NC (GROUND)
AV
DD
AGND
ICOMP1
0.1
F
0.1
F
A
GND
QOUTA
QOUTB
50
50
0.1
F
REFIO
QCOMP1
0.1
F
AV
DD
0.1
F
AV
DD
AGND
AV
DD
NC (GND)
0.1
F
DV
DD
DGND
DVDD
DGND
DGND
DGND
DGND
ANALOG GROUND
PLANE
DIGITAL GROUND
PLANE
PLANE
AV
DD
NOTE: ICOMP1 AND QCOMP1 PINS (24, 14)
MUST BE TIED TOGETHER EXTERNALLY
DV
DD
10
F
0.1
F
FERRITE
10
H
BEAD
+5V TO +3V
POWER SUPPLY
(POWER PLANE)
(POWER PLANE)
HI5628
3-3
Functional Block Diagram
UPPER
VOLTAGE
REFERENCE
(LSB) ID0
ID1
ID2
ID3
ID4
ID5
ID6
ICLK
(MSB) ID7
5-BIT
DECODER
REFIO
LATCH
AV
DD
AGND
DV
DD
DGND
LATCH
CASCODE
CURRENT
SOURCE
SWITCH
MATRIX
BIAS
GENERATION
INT/EXT
FSADJ
REFERENCE
INT/EXT
SELECT
REFLO
31
34
34
31 MSB
SEGMENTS
3 LSBs
+
ICOMP1
SLEEP
IOUTA
IOUTB
UPPER
(LSB) QD0
QD1
QD2
QD3
QD4
QD5
QD6
QCLK
(MSB) QD7
5-BIT
DECODER
LATCH
LATCH
CASCODE
CURRENT
SOURCE
SWITCH
MATRIX
31
34
34
31 MSB
SEGMENTS
3 LSBs
+
QCOMP1
QOUTA QOUTB
HI5628
3-4
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage DV
DD
to DCOM . . . . . . . . . . . . . . . . . +5.5V
Analog Supply Voltage AV
DD
to ACOM . . . . . . . . . . . . . . . . . +5.5V
Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (D7-D0, CLK, SLEEP) . . . . . . . . DV
DD
+ 0.3V
Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . .
50
A
Reference Input Voltage Range . . . . . . . . . . . . . . . . . . AV
DD
+ 0.3V
Analog Output Current (I
OUT
) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AV
DD
= +5V, DV
DD
= +5V, V
REF
= Internal 1.2V, IOUTFS = 20mA, T
A
= 25
o
C for All Typical Values. Data given
is per channel except for `Power Supply Characteristics.'
PARAMETER
TEST CONDITIONS
HI5628IN
T
A
= -40
o
C TO 85
o
C
UNITS
MIN
TYP
MAX
SYSTEM PERFORMANCE (Per Channel)
Resolution
8
-
-
Bits
Integral Linearity Error, INL
"Best Fit" Straight Line (Note 7)
-0.5
0.25
+0.5
LSB
Differential Linearity Error, DNL
(Note 7)
-0.5
0.25
+0.5
LSB
Offset Error, I
OS
(Note 7)
-0.025
-
+0.025
% FSR
Offset Drift Coefficient
(Note 7)
-
0.1
-
ppm
FSR/
o
C
Full Scale Gain Error, FSE
With External Reference (Notes 2, 7)
-10
2
+10
% FSR
With Internal Reference (Notes 2, 7)
-10
1
+10
% FSR
Full Scale Gain Drifta
With External Reference (Note 7)
-
50
-
ppm
FSR/
o
C
With Internal Reference (Note 7)
-
100
-
ppm
FSR/
o
C
Gain Matching Between Channels
-0.5
0.1
0.5
dB
I/Q Channel Isolation
F
OUT
= 10MHz
-
80
-
dB
Output Voltage Compliance Range
(Note 3)
-0.3
-
1.25
V
Full Scale Output Current, I
FS
2
-
20
mA
DYNAMIC CHARACTERISTICS (Per Channel)
Clock Rate, f
CLK
(Note 3, 9)
125
-
-
MHz
Output Settling Time, (t
SETT
)
0.8% (
1 LSB, equivalent to 7 Bits) (Note 7)
-
5
-
ns
0.4% (
1/2 LSB, equivalent to 8 Bits) (Note 7)
-
15
-
ns
Singlet Glitch Area (Peak Glitch)
R
L
= 25
(Note 7)
-
5
-
pVs
Output Rise Time
Full Scale Step
-
1.5
-
ns
Output Fall Time
Full Scale Step
-
1.5
-
ns
Output Capacitance
-
10
-
pF
Output Noise
IOUTFS = 20mA
-
50
-
pA/
Hz
IOUTFS = 2mA
-
30
-
pA/
Hz
HI5628
3-5
AC CHARACTERISTICS - HI5628IN - 125MHz (Per Channel)
Spurious Free Dynamic Range,
SFDR Within a Window
f
CLK
= 125MSPS, f
OUT
= 32.9MHz, 10MHz Span (Notes 4, 7)
-
70
-
dBc
f
CLK
= 100MSPS, f
OUT
= 5.04MHz, 4MHz Span (Notes 4, 7)
-
73
-
dBc
Total Harmonic Distortion (THD) to
Nyquist
f
CLK
= 100MSPS, f
OUT
= 2.00MHz (Notes 4, 7)
-
67
-
dBc
Spurious Free Dynamic Range,
SFDR to Nyquist
f
CLK
= 125MSPS, f
OUT
= 32.9MHz, 62.5MHz Span (Notes 4, 7)
-
51
-
dBc
f
CLK
= 125MSPS, f
OUT
= 10.1MHz, 62.5MHz Span (Notes 4, 7)
-
61
-
dBc
f
CLK
= 100MSPS, f
OUT
= 40.4MHz, 50MHz Span (Notes 4, 7)
-
48
-
dBc
f
CLK
= 100MSPS, f
OUT
= 20.2MHz, 50MHz Span (Notes 4, 7)
-
56
-
dBc
f
CLK
= 100MSPS, f
OUT
= 5.04MHz, 50MHz Span (Notes 4, 7)
-
68
-
dBc
f
CLK
= 100MSPS, f
OUT
= 2.51MHz, 50MHz Span (Notes 4, 7)
-
68
-
dBc
AC CHARACTERISTICS - HI5628/6IN - 60MHz (Per Channel)
Spurious Free Dynamic Range,
SFDR Within a Window
f
CLK
= 60MSPS, f
OUT
= 10.1MHz, 10MHz Span (Notes 4, 7)
-
70
-
dBc
f
CLK
= 50MSPS, f
OUT
= 5.02MHz, 2MHz Span (Notes 4, 7)
-
73
-
dBc
f
CLK
= 50MSPS, f
OUT
= 1.00MHz, 2MHz Span (Notes 4, 7)
-
74
-
dBc
Total Harmonic Distortion (THD) to
Nyquist
f
CLK
= 50MSPS, f
OUT
= 2.00MHz (Notes 4, 7)
-
67
-
dBc
f
CLK
= 50MSPS, f
OUT
= 1.00MHz (Notes 4, 7)
-
68
-
dBc
Spurious Free Dynamic Range,
SFDR to Nyquist
f
CLK
= 60MSPS, f
OUT
= 20.2MHz, 30MHz Span (Notes 4, 7)
-
54
-
dBc
f
CLK
= 60MSPS, f
OUT
= 10.1MHz, 30MHz Span (Notes 4, 7)
-
60
-
dBc
f
CLK
= 50MSPS, f
OUT
= 20.2MHz, 25MHz Span (Notes 4, 7)
-
53
-
dBc
f
CLK
= 50MSPS, f
OUT
= 5.02MHz, 25MHz Span (Notes 4, 7)
-
67
-
dBc
f
CLK
= 50MSPS, f
OUT
= 2.51MHz, 25MHz Span (Notes 4, 7)
-
68
-
dBc
f
CLK
= 50MSPS, f
OUT
= 1.00MHz, 25MHz Span (Notes 4, 7)
-
68
-
dBc
f
CLK
= 25MSPS, f
OUT
= 5.02MHz, 25MHz Span (Notes 4, 7)
-
71
-
dBc
VOLTAGE REFERENCE
Internal Reference Voltage, V
FSADJ
Voltage at Pin 22 with Internal Reference
1.04
1.16
1.28
V
Internal Reference Voltage Drift
-
60
-
ppm
/
o
C
Internal Reference Output Current
Sink/Source Capability
-
0.1
-
A
Reference Input Impedance
-
1
-
M
Reference Input Multiplying Bandwidth
(Note 7)
-
1.4
-
MHz
DIGITAL INPUTS
D7-D0, CLK (Per Channel)
Input Logic High Voltage with
5V Supply, V
IH
(Note 3)
3.5
5
-
V
Input Logic High Voltage with
3V Supply, V
IH
(Note 3)
2.1
3
-
V
Input Logic Low Voltage with
5V Supply, V
IL
(Note 3)
-
0
1.3
V
Input Logic Low Voltage with
3V Supply, V
IL
(Note 3)
-
0
0.9
V
Input Logic Current, I
IH
-10
-
+10
A
Input Logic Current, I
IL
-10
-
+10
A
Digital Input Capacitance, C
IN
-
5
-
pF
Electrical Specifications
AV
DD
= +5V, DV
DD
= +5V, V
REF
= Internal 1.2V, IOUTFS = 20mA, T
A
= 25
o
C for All Typical Values. Data given
is per channel except for `Power Supply Characteristics.' (Continued)
PARAMETER
TEST CONDITIONS
HI5628IN
T
A
= -40
o
C TO 85
o
C
UNITS
MIN
TYP
MAX
HI5628
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