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Электронный компонент: HI5767/4CA

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1
HI5767
10-Bit, 20/40/60MSPS A/D Converter with
Internal Voltage Reference
The HI5767 is a monolithic, 10-bit, analog-to-digital
converter fabricated in a CMOS process. It is designed for
high speed applications where wide bandwidth and low
power consumption are essential. Its high sample clock
rate is made possible by a fully differential pipelined
architecture with both an internal sample and hold and
internal band-gap voltage reference.
The 250MHz Full Power Input Bandwidth and superior high
frequency performance of the HI5767 converter make it an
excellent choice for implementing Digital IF architectures in
communications applications.
The HI5767 has excellent dynamic performance while
consuming only 310mW power at 40MSPS. Data output
latches are provided which present valid data to the output
bus with a latency of 7 clock cycles.
The HI5767 is offered in 20MSPS, 40MSPS and 60MSPS
sampling rates.
Features
Sampling Rate . . . . . . . . . . . . . . . . . . . . . . 20/40/60MSPS
8.8 Bits at f
IN
= 10MHz, f
S
= 40MSPS
Low Power at 40MSPS . . . . . . . . . . . . . . . . . . . . .310mW
Wide Full Power Input Bandwidth . . . . . . . . . . . . 250MHz
On-Chip Sample and Hold
Internal 2.5V Band-Gap Voltage Reference
Fully Differential or Single-Ended Analog Input
Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . .+5V
TTL/CMOS Compatible Digital Inputs
CMOS Compatible Digital Outputs. . . . . . . . . . . 3.0V/5.0V
Offset Binary or Two's Complement Output Format
Applications
Digital Communication Systems
QAM Demodulators
Professional Video Digitizing
Medical Imaging
High Speed Data Acquisition
Pinout
HI5767 (SOIC, SSOP)
TOP VIEW
Ordering Information
PART
NUMBER
TEMP.
RANGE
(
o
C)
PACKAGE
PKG.
NO.
SAMPLING
RATE
(MSPS)
HI5767/2CB
0 to 70 28 Ld SOIC
M28.3
20
HI5767/4CB
0 to 70 28 Ld SOIC
M28.3
40
HI5767/6CB
0 to 70 28 Ld SOIC
M28.3
60
HI5767/6IB
-40 to 85 28 Ld SOIC
M28.3
60
HI5767/2CA
0 to 70 28 Ld SSOP
M28.15
20
HI5767/2IA
-40 to 85 28 Ld SSOP
M28.15
20
HI5767/4CA
0 to 70 28 Ld SSOP
M28.15
40
HI5767/6CA
0 to 70 28 Ld SSOP
M28.15
60
HI5767EVAL1
25
Evaluation Board
60
HI5767EVAL2
25
Evaluation Board
60
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DV
CC1
DGND
DV
CC1
DGND
AV
CC
AGND
V
REFIN
V
REFOUT
V
IN
+
V
IN
-
V
DC
AGND
AV
CC
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
D0
D2
D3
D4
DV
CC2
DGND
D6
D7
D8
D9
DFS
D1
CLK
D5
Data Sheet
March 2003
FN4319.5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2
Functional Block Diagram
DV
CC2
DGND2
OE
+
-
STAGE 1
STAGE 8
CLOCK
BIAS
V
DC
V
IN
-
V
IN
+
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
D8
D9 (MSB)
CLK
DFS
AV
CC
AGND
DV
CC1
DGND1
STAGE 9
X2
S/H
2-BIT
FLASH
2-BIT
DAC
+
-
X2
2-BIT
FLASH
2-BIT
DAC
2-BIT
FLASH
DIGITAL DELAY
AND
DIGITAL ERROR
CORRECTION
REFERENCE
V
REFOUT
V
REFIN
HI5767
3
Typical Application Schematic
Pin Descriptions
HI5767
ARE PLACED AS CLOSE
10
F AND 0.1
F CAPS
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BNC
CLOCK
V
IN
+
10
F
0.1
F
10
F
+
+
V
IN
-
DGND
AGND
V
REFOUT
(8)
V
REFIN
(7)
V
IN
-
(10)
CLK (22)
DFS (15)
DGND1 (4)
DGND2 (21)
DGND1 (2)
AGND (6)
AGND (12)
V
IN
+
(9)
(1) DV
CC1
V
DC
(11)
(LSB) (28) D0
(27) D1
(26) D2
(25) D3
(24) D4
(20) D5
(19) D6
(18) D7
(17) D8
(MSB) (16) D9
(5) AV
CC
(13) AV
CC
(23) DV
CC2
(3) DV
CC1
TO PART AS POSSIBLE
OE (14)
0.1
F
+5V
+5V
0.1
F
PIN NO.
NAME
DESCRIPTION
1
DV
CC1
Digital Supply (+5.0V)
2
DGND1
Digital Ground
3
DV
CC1
Digital Supply (+5.0V)
4
DGND1
Digital Ground
5
AV
CC
Analog Supply (+5.0V)
6
AGND
Analog Ground
7
V
REFIN
+2.5V Reference Voltage Input
8
V
REFOUT
+2.5V Reference Voltage Output
9
V
IN
+
Positive Analog Input
10
V
IN
-
Negative Analog Input
11
V
DC
DC Bias Voltage Output
12
AGND
Analog Ground
13
AV
CC
Analog Supply (+5.0V)
14
OE
Digital Output Enable Control Input
15
DFS
Data Format Select Input
16
D9
Data Bit 9 Output (MSB)
17
D8
Data Bit 8 Output
18
D7
Data Bit 7 Output
19
D6
Data Bit 6 Output
20
D5
Data Bit 5 Output
21
DGND2
Digital Ground
22
CLK
Sample Clock Input
23
DV
CC2
Digital Output Supply (+3.0V or +5.0V)
24
D4
Data Bit 4 Output
25
D3
Data Bit 3 Output
26
D2
Data Bit 2 Output
27
D1
Data Bit 1 Output
28
D0
Data Bit 0 Output (LSB)
PIN NO.
NAME
DESCRIPTION
HI5767
4
Absolute Maximum Ratings
T
A
= 25
o
C
Thermal Information
Supply Voltage, AV
CC
or DV
CC
to AGND or DGND . . . . . . . . . . .6V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND
to DV
CC
Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AV
CC
Operating Conditions
Temperature Range
HI5767/xCx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
HI5767/xIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Storage Temperature Range
. . . . . . . . .-
65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AV
CC
= DV
CC1
= 5.0V, DV
CC2
= 3.0V; V
REFIN
= V
REFOUT
; f
S
= 40MSPS at 50% Duty Cycle;
C
L
= 10pF; T
A
= 25
o
C; Differential Analog Input; Typical Values are Test Results at 25
o
C,
Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ACCURACY
Resolution
10
-
-
Bits
Integral Linearity Error, INL
f
IN
= 1MHz Sinewave
-
0.75
1.75
LSB
Differential Linearity Error, DNL
(Guaranteed No Missing Codes)
f
IN
= 1MHz Sinewave
-
0.35
1.0
LSB
Offset Error, V
OS
f
IN
= DC
-40
-
40
LSB
Full Scale Error, FSE
f
IN
= DC
-
4
-
LSB
DYNAMIC CHARACTERISTICS
Minimum Conversion Rate
No Missing Codes
-
0.5
1
MSPS
Maximum Conversion Rate
HI5767/2
No Missing Codes
20
-
-
MSPS
HI5767/4
No Missing Codes
40
-
-
MSPS
HI5767/6
No Missing Codes
60
-
-
MSPS
Effective Number of Bits, ENOB
HI5767/2
f
S
= 20MSPS, f
IN
= 10MHz
8.7
9
-
Bits
HI5767/4
f
S
= 40MSPS, f
IN
= 10MHz
8.55
8.8
-
Bits
HI5767/6
f
S
= 60MSPS, f
IN
= 10MHz
8.1
8.4
-
Bits
Signal to Noise and Distortion Ratio, SINAD
HI5767/2
f
S
= 20MSPS, f
IN
= 10MHz
-
55.9
-
dB
HI5767/4
f
S
= 40MSPS, f
IN
= 10MHz
-
54.7
-
dB
HI5767/6
f
S
= 60MSPS, f
IN
= 10MHz
-
53.8
-
dB
Signal to Noise Ratio, SNR
HI5767/2
f
S
= 20MSPS, f
IN
= 10MHz
-
55.9
-
dB
HI5767/4
f
S
= 40MSPS, f
IN
= 10MHz
-
55
-
dB
HI5767/6
f
S
= 60MSPS, f
IN
= 10MHz
-
54
-
dB
Total Harmonic Distortion, THD
HI5767/2
f
S
= 20MSPS, f
IN
= 10MHz
-
-71
-
dBc
RMS Signal
RMS Noise + Distortion
--------------------------------------------------------------
=
RMS Signal
RMS Noise
-------------------------------
=
HI5767
5
HI5767/4
f
S
= 40MSPS, f
IN
= 10MHz
-
-65
-
dBc
HI5767/6
f
S
= 60MSPS, f
IN
= 10MHz
-
-64.5
-
dBc
2nd Harmonic Distortion
HI5767/2
f
S
= 20MSPS, f
IN
= 10MHz
-
-76
-
dBc
HI5767/4
f
S
= 40MSPS, f
IN
= 10MHz
-
-73
-
dBc
HI5767/6
f
S
= 60MSPS, f
IN
= 10MHz
-
-70
-
dBc
3rd Harmonic Distortion
HI5767/2
f
S
= 20MSPS, f
IN
= 10MHz
-
-80
-
dBc
HI5767/4
f
S
= 40MSPS, f
IN
= 10MHz
-
-69
-
dBc
HI5767/6
f
S
= 60MSPS, f
IN
= 10MHz
-
-67
-
dBc
Spurious Free Dynamic Range, SFDR
HI5767/2
f
S
= 20MSPS, f
IN
= 10MHz
-
76
-
dBc
HI5767/4
f
S
= 40MSPS, f
IN
= 10MHz
-
69
-
dBc
HI5767/6
f
S
= 60MSPS, f
IN
= 10MHz
-
67
-
dBc
Intermodulation Distortion, IMD
f
1
= 1MHz, f
2
= 1.02MHz
-
64
-
dBc
Differential Gain Error
f
S
= 17.72MHz, 6 Step, Mod Ramp
-
0.5
-
%
Differential Phase Error
f
S
= 17.72MHz, 6 Step, Mod Ramp
-
0.2
-
Degree
Transient Response
(Note 2)
-
1
-
Cycle
Over-Voltage Recovery
0.2V Overdrive (Note 2)
-
1
-
Cycle
ANALOG INPUT
Maximum Peak-to-Peak Differential Analog Input
Range (V
IN
+ - V
IN
-)
-
0.5
-
V
Maximum Peak-to-Peak Single-Ended
Analog Input Range
-
1.0
-
V
Analog Input Resistance, R
IN
(Note 3)
-
1
-
M
Analog Input Capacitance, C
IN
-
10
-
pF
Analog Input Bias Current, I
B
+
or I
B
-
(Note 3)
-10
-
+10
A
Differential Analog Input Bias Current
I
BDIFF
= (I
B
+
- I
B
-)
(Note 3)
-
0.5
-
A
Full Power Input Bandwidth, FPBW
-
250
-
MHz
Analog Input Common Mode Voltage Range
(V
IN
+ + V
IN
-) / 2
Differential Mode (Note 2)
0.25
-
4.75
V
INTERNAL REFERENCE VOLTAGE
Reference Voltage Output, V
REFOUT
(Loaded)
-
2.5
-
V
Reference Output Current, I
REFOUT
-
1
2
mA
Reference Temperature Coefficient
-
120
-
ppm/
o
C
REFERENCE VOLTAGE INPUT
Reference Voltage Input, V
REFIN
-
2.5
-
V
Total Reference Resistance, R
REFIN
-
2.5
-
k
Reference Input Current, I
REFIN
-
1
-
mA
DC BIAS VOLTAGE
DC Bias Voltage Output, V
DC
-
3.0
-
V
Electrical Specifications
AV
CC
= DV
CC1
= 5.0V, DV
CC2
= 3.0V; V
REFIN
= V
REFOUT
; f
S
= 40MSPS at 50% Duty Cycle;
C
L
= 10pF; T
A
= 25
o
C; Differential Analog Input; Typical Values are Test Results at 25
o
C,
Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HI5767