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Электронный компонент: HI5805BIB

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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
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Copyright
Intersil Corporation 1999
HI5805
12-Bit, 5MSPS A/D Converter
The HI5805 is a monolithic, 12-bit, Analog-to-Digital
Converter fabricated in Intersil's HBC10 BiCMOS process. It
is designed for high speed, high resolution applications
where wide bandwidth and low power consumption are
essential.
The HI5805 is designed in a fully differential pipelined
architecture with a front end differential-in-differential-out
sample-and-hold (S/H). The HI5805 has excellent dynamic
performance while consuming 300mW power at 5MSPS.
The 100MHz full power input bandwidth is ideal for
communication systems and document scanner
applications. Data output latches are provided which present
valid data to the output bus with a latency of 3 clock cycles.
The digital outputs have a separate supply pin which can be
powered from a 3.0V to 5.0V supply.
Pinout
HI5805
(SOIC)
TOP VIEW
Features
Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . .5MSPS
Low Power
Internal Sample and Hold
Fully Differential Architecture
Full Power Input Bandwidth . . . . . . . . . . . . . . . . . 100MHz
Low Distortion
Internal Voltage Reference
TTL/CMOS Compatible Digital I/O
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . 5V to 3.0V
Applications
Digital Communication Systems
Undersampling Digital IF
Document Scanners
Additional Reference Documents
- AN9214 Using Intersil High Speed A/D Converters
- AN9707 Using the HI5805EVAL1 Evaluation Board
Ordering Information
PART
NUMBER
SAMPLE
RATE
TEMP.
RANGE (
o
C)
PACKAGE
PKG.
NO.
HI5805BIB
5MSPS
-40 to 85
28 Ld SOIC (W) M28.3
HI5805EVAL1
25
Evaluation Board
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CLK
DV
CC1
V
IN+
V
DC
V
ROUT
V
RIN
A
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
D0
D2
D3
D4
DV
CC2
D
GND2
D6
D7
D8
D9
D1
D5
D
GND1
DV
CC1
D
GND1
AV
CC
A
GND
AV
CC
D10
D11
V
IN-
Data Sheet
February 1999
File Number
3984.6
117
Functional Block Diagram
Typical Application Schematic
V
DC
V
IN
+
V
IN
-
BIAS
4-BIT
FLASH
+
-
4-BIT
DAC
4-BIT
FLASH
STAGE 4
STAGE 3
STAGE 1
AV
CC
A
GND
DV
CC1
D
GND1
DIGIT
AL DELA
Y
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
4-BIT
FLASH
+
-
4-BIT
DAC
AND
DIGIT
AL ERR
OR CORRECTION
CLOCK
REF
DV
CC2
D
GND2
V
ROUT
CLK
V
RIN
X8
X8
S/H
V
RIN
(12)
HI5805
V
ROUT
(11)
V
IN
- (9)
CLK (1)
D
GND1
(5)
D
GND2
(21)
D
GND1
(3)
A
GND
(13)
(14) AV
CC
(22) DV
CC2
(17) D9
(18) D8
(19) D7
(20) D6
(23) D5
(24) D4
(25) D3
(26) D2
(27) D1
(LSB) (28) D0
AS CLOSE TO PART AS POSSIBLE
10
F AND 0.1
F CAPS ARE PLACED
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BNC
CLOCK
V
IN
+
0.1
F
10
F
0.1
F
10
F
+
+
A
GND
(7)
V
IN
+ (8)
V
IN
-
D
GND
A
GND
(2) DV
CC1
(4) DV
CC1
V
DC
(10)
(16) D10
D10
(MSB) (15) D11
D11
(6) AV
CC
+5V
+5V
HI5805
118
Absolute Maximum Ratings
Thermal Information
Supply Voltage, AV
CC
or DV
CC
to A
GND
or D
GND
. . . . . . . . . +6.0V
D
GND
to A
GND
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D
GND
to DV
CC
Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A
GND
to AV
CC
Operating Conditions
Temperature Range, HI5805BIB . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . .300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AV
CC
= DV
CC1
= DV
CC2
= DV
CC3
= +5.0V, f
S
= 5MSPS at 50% Duty Cycle, V
RIN
= 3.5V, C
L
= 10pF,
T
A
= -40
o
C to 85
o
C, Differential Analog Input, Typical Values are Test Results at 25
o
C,
Unless Otherwise Specified
PARAMETER
TEST CONDITION
HI5805BIB (-40
o
C TO 85
o
C)
UNITS
MIN
TYP
MAX
ACCURACY
Resolution
12
-
-
Bits
Integral Linearity Error, INL
f
IN
= DC
-
1
2
LSB
Differential Linearity Error, DNL
(Guaranteed No Missing Codes)
f
IN
= DC
-
0.5
1
LSB
Offset Error, V
OS
f
IN
= DC
-
19
-
LSB
Full Scale Error, FSE
f
IN
= DC
-
32
-
LSB
DYNAMIC CHARACTERISTICS
Minimum Conversion Rate
No Missing Codes
-
0.5
-
MSPS
Maximum Conversion Rate
No Missing Codes
5
-
-
MSPS
Effective Number of Bits, ENOB
f
IN
= 1MHz
10.0
11
-
Bits
Signal to Noise and Distortion Ratio, SINAD
f
IN
= 1MHz
-
68
-
dB
Signal to Noise Ratio, SNR
f
IN
= 1MHz
-
68
-
dB
Total Harmonic Distortion, THD
f
IN
= 1MHz
-
-80
-
dBc
2nd Harmonic Distortion
f
IN
= 1MHz
-
-86
dBc
3rd Harmonic Distortion
f
IN
= 1MHz
-
-83
-
dBc
Spurious Free Dynamic Range, SFDR
f
IN
= 1MHz
-
83
-
dBc
Intermodulation Distortion, IMD
f
1
= 1MHz, f
2
= 1.02MHz
-
-68
-
dBc
Transient Response
-
1
-
Cycle
Over-Voltage Recovery
0.2V Overdrive
-
2
-
Cycle
ANALOG INPUT
Maximum Peak-to-Peak Differential Analog Input Range
(V
IN
+ - V
IN
-)
-
2.0
-
V
Maximum Peak-to-Peak Single-Ended Analog Input Range
-
4.0
-
V
Analog Input Resistance, R
IN
(Notes 2, 3)
1
-
-
M
Analog Input Capacitance, C
IN
-
10
-
pF
Analog Input Bias Current, I
B
+ or I
B
-
(Note 3)
-10
-
+10
A
Differential Analog Input Bias Current I
B DIFF
= (I
B
+ - I
B
-)
-
0.5
-
A
Full Power Input Bandwidth, FPBW
-
100
-
MHz
Analog Input Common Mode Voltage Range (V
IN
+ + V
IN
-)/2
Differential Mode (Note 2)
1
2.3
4
V
=
RMS Signal
RMS Noise + Distortion
--------------------------------------------------------------
=
RMS Signal
RMS Noise
-------------------------------
HI5805
119
INTERNAL VOLTAGE REFERENCE
Reference Output Voltage, V
ROUT
(Loaded)
-
3.5
-
V
Reference Output Current
-
-
1
mA
Reference Temperature Coefficient
-
200
-
ppm/
o
C
REFERENCE VOLTAGE INPUT
Reference Voltage Input, V
RIN
-
3.5
-
V
Total Reference Resistance, R
L
-
7.8
-
k
Reference Current
-
450
-
A
DC BIAS VOLTAGE
DC Bias Voltage Output, V
DC
-
2.3
-
V
Max Output Current (Not To Exceed)
-
-
1
mA
DIGITAL INPUTS (CLK)
Input Logic High Voltage, V
IH
2.0
-
-
V
Input Logic Low Voltage, V
IL
-
-
0.8
V
Input Logic High Current, I
IH
V
CLK
= 5V
-
-
10.0
A
Input Logic Low Current, I
IL
V
CLK
= 0V
-
-
10.0
A
Input Capacitance, C
IN
-
7
-
pF
DIGITAL OUTPUTS (D0-D11)
Output Logic Sink Current, I
OL
V
O
= 0.4V (Note 2)
1.6
-
-
mA
DV
CC3
= 3.0V, V
O
= 0.4V
-
1.6
-
mA
Output Logic Source Current, I
OH
V
O
= 2.4V (Note 2)
-0.2
-
-
mA
DV
CC3
= 3.0V, V
O
= 2.4V
-
-0.2
-
mA
Output Capacitance, C
OUT
-
5
-
pF
TIMING CHARACTERISTICS
Aperture Delay, t
AP
-
5
-
ns
Aperture Jitter, t
AJ
-
5
-
ps (RMS)
Data Output Delay, t
OD
-
8
-
ns
Data Output Hold, t
H
-
8
-
ns
Data Latency, t
LAT
For a Valid Sample (Note 2)
-
-
3
Cycles
Clock Pulse Width (Low)
5MSPS Clock
90
100
110
ns
Clock Pulse Width (High)
5MSPS Clock
90
100
110
ns
POWER SUPPLY CHARACTERISTICS
Total Supply Current, I
CC
V
IN
+ - V
IN
- = 2V
-
60
70
mA
Analog Supply Current, AI
CC
V
IN
+ - V
IN
- = 2V
-
46
-
mA
Digital Supply Current, DI
CC1
V
IN
+ - V
IN
- = 2V
-
13
-
mA
Output Supply Current, DI
CC2
V
IN
+ - V
IN
- = 2V
-
1
-
mA
Power Dissipation
V
IN
+ - V
IN
- = 2V
-
300
350
mW
Offset Error PSRR,
V
OS
AV
CC
or DV
CC
= 5V
5%
-
2
-
LSB
Gain Error PSRR,
FSE
AV
CC
or DV
CC
= 5V
5%
-
30
-
LSB
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. With the clock off (clock low, hold mode).
Electrical Specifications
AV
CC
= DV
CC1
= DV
CC2
= DV
CC3
= +5.0V, f
S
= 5MSPS at 50% Duty Cycle, V
RIN
= 3.5V, C
L
= 10pF,
T
A
= -40
o
C to 85
o
C, Differential Analog Input, Typical Values are Test Results at 25
o
C,
Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITION
HI5805BIB (-40
o
C TO 85
o
C)
UNITS
MIN
TYP
MAX
HI5805
120
Timing Waveforms
NOTES:
4. S
N
: N-th sampling period.
5. H
N
: N-th holding period.
6. B
M, N
: M-th stage digital output corresponding to N-th sampled input.
7. D
N
: Final data output corresponding to N-th sampled input.
FIGURE 1. INTERNAL CIRCUIT TIMING
FIGURE 2. INPUT-TO-OUTPUT TIMING
ANALOG
INPUT
CLOCK
INPUT
INPUT
S/H
1ST
STAGE
2ND
STAGE
3RD
STAGE
4TH
STAGE
DATA
OUTPUT
S
N-1
H
N - 1
S
N
H
N
S
N + 1
H
N + 1
S
N + 2
H
N + 2
S
N + 3
H
N + 3
S
N+4
H
N + 4
S
N + 5
H
N + 5
S
N + 6
H
N + 6
B
1, N + 5
B
1, N + 4
B
1, N + 3
B
1, N + 2
B
1, N + 1
B
1, N
B
1, N - 1
B
2, N - 2
B
3, N - 2
B
4, N - 3
D
N - 3
B
2, N - 1
B
3, N - 1
B
4, N - 2
D
N - 2
t
LAT
D
N - 1
B
4, N - 1
B
2, N
B
3, N
B
2, N + 1
B
3, N + 1
B
4, N
D
N
D
N + 1
B
4, N + 1
B
2, N + 2
B
2, N + 3
B
3, N + 2
B
4, N + 2
D
N + 2
B
3, N + 3
B
2, N + 4
B
3, N + 4
B
4, N + 3
D
N + 3
t
OD
t
H
DATA N - 1
DATA N
CLOCK
INPUT
DATA
OUTPUT
0.8V
2.0V
1.5V
t
AP
ANALOG
INPUT
t
AJ
1.5V
HI5805