1
File Number
4655.3
HI5960
14-Bit, 125+MSPS, CommLink
TM
High
Speed D/A Converter
The HI5960 is a 14-bit, 125+MSPS (Mega Samples Per
Second), high speed, low power, D/A converter which is
implemented in an advanced CMOS process. Operating
from a single +3V to +5V supply, the converter provides
20mA of full scale output current and includes edge-
triggered CMOS input data latches. Low glitch energy and
excellent frequency domain performance are achieved using
a segmented current source architecture.
This device complements the CommLink HI5x60 and HI5x28
family of high speed converters, which includes 8, 10, 12,
and 14-bit devices.
Pinout
HI5960
TOP VIEW
Features
Throughput Rate . . . . . . . . . . . . . . . . . . . . . . .125+MSPS
Low Power . . . 175mW at 5V, 32mW at 3V (at 100MSPS)
Adjustable Full Scale Output Current . . . . . 2mA to 20mA
Internal 1.2V Bandgap Voltage Reference
Single Power Supply from +5V to +3V
Power Down Mode
CMOS Compatible Inputs
Excellent Spurious Free Dynamic Range
(77dBc, f
S
= 50MSPS, f
OUT
= 2.51MHz)
Excellent Multitone Intermodulation Distortion
Applications
Cellular Basestations
WLL, Basestation and Subscriber Units
Medical/Test Instrumentation
Wireless Communications Systems
Direct Digital Frequency Synthesis
High Resolution Imaging Systems
Arbitrary Waveform Generators
Ordering Information
PART
NUMBER
TEMP.
RANGE
(
o
C)
PACKAGE
PKG. NO.
CLOCK
SPEED
HI5960IB
-40 to 85 28 Ld SOIC
M28.3
125MHz
HI5960IA
-40 to 85 28 Ld TSSOP M28.173A 125MHz
HI5960SOICEVAL1
25
Evaluation Platform
125MHz
TSSOP Samples Available November 1999.
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D13 (MSB)
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK
DCOM
ACOM
AV
DD
COMP2
IOUTB
COMP1
FSADJ
REFIO
REFLO
SLEEP
DV
DD
IOUTA
ACOM
Data Sheet
November 1999
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Copyright
Intersil Corporation 1999
CommLinkTM is a trademark of Intersil Corporation.
2
Typical Applications Circuit
Functional Block Diagram
D11 (3)
D10 (4)
D9 (5)
D8 (6)
D7 (7)
D6 (8)
D5 (9)
D4 (10)
D11
D10
D9
D8
D7
D6
D5
D4
DCOM (26)
CLK (28)
(19) COMP1
(24) AV
DD
D/A OUT
(22) IOUTA
(21) IOUTB
50
(18) FSADJ
(16) REFLO
HI5960
DV
DD
(27)
0.1
F
50
10
F
(20) ACOM
50
(15) SLEEP
(17) REFIO
0.1
F
1.91k
FERRITE
10
H
0.1
F
(23) COMP2
0.1
F
D/A OUT
+
BEAD
R
SET
D3
D2
D1
D0
D3 (11)
D2 (12)
D1 (13)
D0 (LSB) (14)
0.1
F
10
H
+
BEAD
(25) ACOM
ACOM
DCOM
10
F
D13 (1)
D12 (2)
D13
D12
+5V OR +3V (V
DD
)
UPPER
VOLTAGE
REFERENCE
(LSB) D0
D1
D2
D3
D4
D5
D6
D9
CLK
D7
D8
5-BIT
DECODER
REFIO
LATCH
AV
DD
ACOM
DV
DD
DCOM
LATCH
CASCODE
CURRENT
SOURCE
SWITCH
MATRIX
BIAS
GENERATION
INT/EXT
FSADJ
REFERENCE
INT/EXT
SELECT
REFLO
31
40
40
31 MSB
SEGMENTS
9 LSBs
+
COMP2
COMP1
SLEEP
IOUTA
IOUTB
D10
D11
D12
(MSB) D13
HI5960
3
Pin Descriptions
PIN NO.
PIN NAME
DESCRIPTION
1-14
D13 (MSB) Through
D0 (LSB)
Digital Data Bit 13, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit).
15
SLEEP
Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep
pin has internal 20
A active pulldown current.
16
REFLO
Connect to analog ground to enable internal 1.2V reference or connect to AV
DD
to disable internal
reference.
17
REFIO
Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is
enabled. Use 0.
1
F cap to ground when internal reference is enabled.
18
FSADJ
Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output
Current = 32 x V
FSADJ
/R
SET
.
19
COMP1
For use in reducing bandwidth/noise. Recommended: connect 0.1
F to AV
DD
.
21
IOUTB
The complimentary current output of the device. Full scale output current is achieved when all input bits
are set to binary 0.
22
IOUTA
Current output of the device. Full scale output current is achieved when all input bits are set to binary 1.
23
COMP2
Connect 0.1
F capacitor to ACOM.
24
AV
DD
Analog Supply (+3V to +5V).
20, 25
ACOM
Connect to Analog Ground.
26
DCOM
Connect to Digital Ground.
27
DV
DD
Digital Supply (+3V to +5V).
28
CLK
Clock Input. Input data to the DAC passes through the "master" latches when the clock is low and is
latched into the "master" latches when the clock is high. Data presented to the "slave" latch passes
through when the clock is logic high and is latched into the "slave" latches when the clock is logic low.
Adequate setup time must be allowed for the MSBs to pass through the thermometer decoder before the
clock goes high. This master-slave arrangement comprises an edge-triggered flip-flop, with the DAC
being updated on the rising clock edge. It is recommended that the clock edge be skewed such that setup
time is larger than the hold time.
HI5960
4
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage DV
DD
to DCOM . . . . . . . . . . . . . . . . . . +5.5V
Analog Supply Voltage AV
DD
to ACOM . . . . . . . . . . . . . . . . . . +5.5V
Grounds, ACOM TO DCOM. . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (D9-D0, CLK, SLEEP) . . . . . . . . DV
DD
+ 0.3V
Reference Input Voltage Range . . . . . . . . . . . . . . . . . . AV
DD
+ 0.3V
Analog Output Current (I
OUT
) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
110
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AV
DD
= DV
DD
= +5V, V
REF
= Internal 1.2V, IOUTFS = 20mA, T
A
= 25
o
C for All Typical Values
PARAMETER
TEST CONDITIONS
T
A
= -40
o
C TO 85
o
C
UNITS
MIN
TYP
MAX
SYSTEM PERFORMANCE
Resolution
14
-
-
Bits
Integral Linearity Error, INL
"Best Fit" Straight Line (Note 8)
-5
2.5
+5
LSB
Differential Linearity Error, DNL
(Note 8)
-3
1.5
+3
LSB
Offset Error, I
OS
(Note 8)
-0.025
+0.025
% FSR
Offset Drift Coefficient
(Note 8)
-
0.1
-
ppm
FSR/
o
C
Full Scale Gain Error, FSE
With External Reference (Notes 2, 8)
-10
2
+10
% FSR
With Internal Reference (Notes 2, 8)
-10
1
+10
% FSR
Full Scale Gain Drift
With External Reference (Note 8)
-
50
-
ppm
FSR/
o
C
With Internal Reference (Note 8)
-
100
-
ppm
FSR/
o
C
Full Scale Output Current, I
FS
2
-
20
mA
Output Voltage Compliance Range
(Note 3, 8)
-0.3
-
1.25
V
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, f
CLK
(Note 3)
125
-
-
MHz
Output Settling Time, (t
SETT
)
0.05% (
8 LSB) (Note 8)
-
35
-
ns
Singlet Glitch Area (Peak Glitch)
R
L
= 25
(Note 8)
-
5
-
pVs
Output Rise Time
Full Scale Step
-
2.5
-
ns
Output Fall Time
Full Scale Step
-
2.5
-
ns
Output Capacitance
-
10
-
pF
Output Noise
IOUTFS = 20mA
-
50
-
pA/
Hz
IOUTFS = 2mA
-
30
-
pA/
Hz
AC CHARACTERISTICS
+5V Power Supply
Spurious Free Dynamic Range,
SFDR Within a Window
f
CLK
= 100MSPS, f
OUT
= 20.2MHz, 30MHz Span (Notes 4, 8)
-
77
-
dBc
f
CLK
= 100MSPS, f
OUT
= 5.04MHz, 8MHz Span (Notes 4, 8)
-
97
-
dBc
f
CLK
= 50MSPS, f
OUT
= 5.02MHz, 8MHz Span (Notes 4, 8)
-
97
-
dBc
HI5960
5
+5V Power Supply
Total Harmonic Distortion (THD) to
Nyquist
f
CLK
= 100MSPS, f
OUT
= 4.0MHz (Notes 4, 8)
-
-71
-
dBc
f
CLK
= 50MSPS, f
OUT
= 2.0MHz (Notes 4, 8)
-
-75
-
dBc
f
CLK
= 25MSPS, f
OUT
= 1.0MHz (Notes 4, 8)
-
-77
-
dBc
+5V Power Supply
Spurious Free Dynamic Range,
SFDR to Nyquist (f
CLK
/2)
f
CLK
= 125MSPS, f
OUT
= 40.4MHz (Notes 4, 8)
-
56
-
dBc
f
CLK
= 125MSPS, f
OUT
= 10.1MHz (Notes 4, 8)
-
67
-
dBc
f
CLK
= 125MSPS, f
OUT
= 5.02MHz, T = 25
o
C (Notes 4, 8)
68
74
-
dBc
f
CLK
= 125MSPS, f
OUT
= 5.02MHz, T = Min to Max (Notes 4, 8)
66
-
-
dBc
f
CLK
= 100MSPS, f
OUT
= 40.4MHz (Notes 4, 8)
-
55
-
dBc
f
CLK
= 100MSPS, f
OUT
= 20.2MHz (Notes 4, 8)
-
63
-
dBc
f
CLK
= 100MSPS, f
OUT
= 5.04MHz, T = 25
o
C (Notes 4, 8)
68
74
-
dBc
f
CLK
= 100MSPS, f
OUT
= 5.04MHz, T = Min to Max (Notes 4, 8)
66
-
dBc
f
CLK
= 100MSPS, f
OUT
= 2.51MHz (Notes 4, 8)
-
76
-
dBc
f
CLK
= 50MSPS, f
OUT
= 20.2MHz (Notes 4, 8)
-
65
-
dBc
f
CLK
= 50MSPS, f
OUT
= 5.02MHz, T = 25
o
C (Notes 4, 8)
68
74
-
dBc
f
CLK
= 50MSPS, f
OUT
= 5.02MHz, T = Min to Max (Notes 4, 8)
66
-
-
dBc
f
CLK
= 50MSPS, f
OUT
= 2.51MHz (Notes 4, 8)
-
77
-
dBc
f
CLK
= 50MSPS, f
OUT
= 1.00MHz (Notes 4, 8)
-
79
-
dBc
f
CLK
= 25MSPS, f
OUT
= 1.0MHz (Notes 4, 8)
-
79
-
dBc
+5V Power Supply
Multitone Power Ratio
f
CLK
= 20MSPS, f
OUT
= 2.0MHz to 2.99MHz, 8 Tones at 110kHz
Spacing (Notes 4, 8)
-
76
-
dBc
f
CLK
= 100MSPS, f
OUT
= 10MHz to 14.95MHz, 8 Tones at 530kHz
Spacing (Notes 4, 8)
-
76
-
dBc
+3V Power Supply
Spurious Free Dynamic Range,
SFDR Within a Window
f
CLK
= 100MSPS, f
OUT
= 20.2MHz, 30MHz Span (Notes 4, 8)
-
80
-
dBc
f
CLK
= 100MSPS, f
OUT
= 5.04MHz, 8MHz Span (Notes 4, 8)
-
95
-
dBc
f
CLK
= 50MSPS, f
OUT
= 5.02MHz, 8MHz Span (Notes 4, 8)
-
95
-
dBc
+3V Power Supply
Total Harmonic Distortion (THD) to
Nyquist
f
CLK
= 100MSPS, f
OUT
= 4.0MHz (Notes 4, 8)
-
-70
-
dBc
f
CLK
= 50MSPS, f
OUT
= 2.0MHz (Notes 4, 8)
-
-74
-
dBc
f
CLK
= 25MSPS, f
OUT
= 1.0MHz (Notes 4, 8)
-
-76
-
dBc
+3V Power Supply
Spurious Free Dynamic Range,
SFDR to Nyquist (f
CLK
/2)
f
CLK
= 125MSPS, f
OUT
= 40.4MHz (Notes 4, 8)
-
48
-
dBc
f
CLK
= 125MSPS, f
OUT
= 10.1MHz (Notes 4, 8)
-
66
-
dBc
f
CLK
= 125MSPS, f
OUT
= 5.02MHz (Notes 4, 8)
-
74
-
dBc
f
CLK
= 100MSPS, f
OUT
= 40.4MHz (Notes 4, 8)
-
49
-
dBc
f
CLK
= 100MSPS, f
OUT
= 20.2MHz (Notes 4, 8)
-
59
-
dBc
f
CLK
= 100MSPS, f
OUT
= 5.04MHz (Notes 4, 8)
-
72
-
dBc
f
CLK
= 100MSPS, f
OUT
= 2.51MHz (Notes 4, 8)
-
77
-
dBc
f
CLK
= 50MSPS, f
OUT
= 20.2MHz (Notes 4, 8)
-
56
-
dBc
f
CLK
= 50MSPS, f
OUT
= 5.02MHz, T = 25
o
C (Notes 4, 8)
68
73
-
dBc
f
CLK
= 50MSPS, f
OUT
= 5.02MHz, T = Min to Max (Notes 4, 8)
66
-
-
dBc
f
CLK
= 50MSPS, f
OUT
= 2.51MHz (Notes 4, 8)
-
76
-
dBc
f
CLK
= 50MSPS, f
OUT
= 1.00MHz (Notes 4, 8)
-
79
-
dBc
f
CLK
= 25MSPS, f
OUT
= 1.0MHz (Notes 4, 8)
-
78
-
dBc
Electrical Specifications
AV
DD
= DV
DD
= +5V, V
REF
= Internal 1.2V, IOUTFS = 20mA, T
A
= 25
o
C for All Typical Values (Continued)
PARAMETER
TEST CONDITIONS
T
A
= -40
o
C TO 85
o
C
UNITS
MIN
TYP
MAX
HI5960
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