1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
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Copyright
Intersil Corporation 1999
July 1998
HI7106
3
1
/
2
Digit, LCD/LED Display, A/D Converter
Features
Guaranteed Zero Reading for 0V Input on All Scales
True Polarity at Zero for Precise Null Detection
1pA Typical Input Current
True Differential Input and Reference,
Direct Display Drive
Low Noise - Less Than 15
V
P-P
On Chip Clock and Reference
Low Power Dissipation - Typically Less Than 10mW
No Additional Active Circuits Required
Enhanced Display Stability
Enhanced VCOM Reference Stability
Description
The Intersil HI7106 is a high performance, low power, 3
1
/
2
digit A/D converter. Included are seven segment decoders,
display drivers, a reference, and a clock. The HI7106 is
designed to interface with a liquid crystal display (LCD) and
includes a multiplexed backplane drive.
The HI7106 brings together a combination of high accuracy,
versatility, and true economy. It features auto-zero to less
than 10
V, zero drift of less than 1
V/
o
C, input bias current
of 10pA (Max), and rollover error of less than one count.
True differential inputs and reference are useful in all sys-
tems, but give the designer an uncommon advantage when
measuring load cells, strain gauges and other bridge type
transducers. Finally, the true economy of single power supply
operation enables a high performance panel meter to be built
with the addition of only 10 passive components and a display.
Ordering Information
PART NO.
TEMP.
RANGE (
o
C)
PACKAGE
PKG. NO.
HI7106CPL
0 to 70
40 Ld PDIP
E40.6
HI7106CM44
0 to 70
44 Ld MQFP
Q44.10x10
HI7106C/D
0 to 70
DIE
Pinouts
HI7106
(PDIP)
TOP VIEW
HI7106
(MQFP)
TOP VIEW
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
V+
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3
(1000) AB4
POL
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
C
REF
+
C
REF
-
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V-
G2 (10's)
C3
A3
G3
BP/GND
(1's)
(10's)
(100's)
(MINUS)
(100's)
OSC 2
NC
OSC 3
TEST
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17
OSC 1
V+
D1
C1
B1
A1 F1 G1 E1 D2 C2
28
27
26
25
24
23
22
21
20
19
18
B2 A2 F2 E2 D3
B3
F3
E3
AB4
POL
BP/GND
39 38 37 36 35 34
33
32
31
30
29
44 43 42 41 40
IN HI
IN LO
A-Z
B
UFF
INT
V-
NC
G2
C3
A3
G3
REF HI
REF LO
C
REF
+
C
REF
-
COMMON
File Number
4551
2
Absolute Maximum Ratings
Thermal Information
Supply Voltage
HI7106, V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
Analog Input Voltage (Either Input) (Note 1). . . . . . . . . . . . . V+ to V-
Reference Input Voltage (Either Input) . . . . . . . . . . . . . . . . . V+ to V-
Clock Input
HI7106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST to V+
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0
o
C to 70
o
C
Thermal Resistance (Typical, Note 2)
JA
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(MQFP - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Input voltages may exceed the supply voltages provided the input current is limited to
100
A.
2.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
(Note 3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYSTEM PERFORMANCE
Zero Input Reading
V
IN
= 0.0V, Full Scale = 200mV
-000.0
000.0
+000.0
Digital
Reading
Stability (Last Digit)
Fixed Input Voltage (Note 6)
-000.1
000.0
+000.1
Digital
Reading
Ratiometric Reading
V
lN
= V
REF
, V
REF
= 100mV
999
999/10
00
1000
Digital
Reading
Rollover Error
-V
IN
= +V
lN
200mV
Difference in Reading for Equal Positive and
Negative Inputs Near Full Scale
-
0.2
1
Counts
Linearity
Full Scale = 200mV or Full Scale = 2V Maximum
Deviation from Best Straight Line Fit (Note 6)
-
0.2
1
Counts
Common Mode Rejection Ratio
V
CM
= 1V, V
IN
= 0V, Full Scale = 200mV (Note 6)
-
50
-
V/V
Noise
V
IN
= 0V, Full Scale = 200mV
(Peak-To-Peak Value Not Exceeded 95% of Time)
-
15
-
V
Leakage Current Input
V
lN
= 0 (Note 6)
-
1
10
pA
Zero Reading Drift
V
lN
= 0, 0
o
C To 70
o
C (Note 6)
-
0.2
1
V/
o
C
Scale Factor Temperature Coefficient
V
IN
= 199mV, 0
o
C To 70
o
C
,
(Ext. Ref. 0ppm/
o
C) (Note 6)
-
1
5
ppm/
o
C
End Power Supply Character V+ Supply
Current
V
IN
= 0
-
0.6
1.8
mA
COMMON Pin Analog Common Voltage
25k
Between Common and
Positive Supply (With Respect to + Supply)
2.4
2.8
3.2
V
Temperature Coefficient of Analog Common
25k
Between Common and
Positive Supply (With Respect to + Supply)
-
80
-
ppm/
o
C
DISPLAY DRIVER
Peak-To-Peak Segment Drive Voltage
Peak-To-Peak Backplane Drive Voltage
V+ = to V- = 9V (Note 5)
4
5
6
V
NOTES:
3. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
4. Unless otherwise noted, specifications apply to both the HI7106 and ICL7107 at T
A
= 25
o
C, fCLOCK = 48kHz. HI7106 is tested in the
circuit of Figure 1.
5. Back plane drive is in phase with segment drive for `off' segment, 180 degrees out of phase for `on' segment. Frequency is 20 times
conversion rate. Average DC component is less than 50mV.
6. Not tested, guaranteed by design.
HI7106
3
Typical Application and Test Circuit
FIGURE 1. HI7106 TEST CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS
SELECTED FOR 200mV FULL SCALE
Design Information Summary Sheet
OSCILLATOR FREQUENCY
f
OSC
= 0.45/RC
C
OSC
> 50pF; R
OSC
> 50k
f
OSC
(Typ) = 48kHz
OSCILLATOR PERIOD
t
OSC
= RC/0.45
INTEGRATION CLOCK FREQUENCY
f
CLOCK
= f
OSC
/4
INTEGRATION PERIOD
t
INT
= 1000 x (4/f
OSC
)
60/50Hz REJECTION CRITERION
t
INT
/t
60Hz
or t
lNT
/t
60Hz
= Integer
OPTIMUM INTEGRATION CURRENT
I
INT
= 4
A
FULL SCALE ANALOG INPUT VOLTAGE
V
lNFS
(Typ) = 200mV or 2V
INTEGRATE RESISTOR
INTEGRATE CAPACITOR
INTEGRATOR OUTPUT VOLTAGE SWING
V
INT
MAXIMUM SWING:
(V- + 0.5V) < V
INT
< (V+ - 0.5V), V
INT
(Typ) = 2V
DISPLAY COUNT
CONVERSION CYCLE
t
CYC
= t
CL0CK
x 4000
t
CYC
= t
OSC
x 16,000
when f
OSC
= 48kHz; t
CYC
= 333ms
COMMON MODE INPUT VOLTAGE
(V- + 1V) < V
lN
< (V+ - 0.5V)
AUTO-ZERO CAPACITOR
0.01
F < C
AZ
< 1
F
REFERENCE CAPACITOR
0.1
F < C
REF
< 1
F
V
COM
Biased between Vi and V-.
V
COM
V+ - 2.8V
Regulation lost when V+ to V- <
6.8V
If V
COM
is externally pulled down to (V+ to V-)/2,
the V
COM
circuit will turn off.
HI7106 POWER SUPPLY: SINGLE 9V
V+ - V- = 9V
Digital supply is generated internally
V
GND
V+ - 4.5V
HI7106 DISPLAY: LCD
Type: Direct drive with digital logic supply amplitude.
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
V+
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3
AB4
POL
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
C
REF
+
C
REF
-
COM
IN HI
IN LO
A-Z
B
UFF
INT
V-
G2
C3
A3
G3
BP
DISPLAY
DISPLAY
C
1
C
2
C
3
C
4
R
3
R
1
R
4
C
5
+
-
IN
R
5
R
2
9V
HI7106
C
1
= 0.1
F
C
2
= 0.47
F
C
3
= 0.22
F
C
4
= 100pF
C
5
= 0.02
F
R
1
= 24k
R
2
= 47k
R
3
= 100k
R
4
= 1k
R
5
= 1M
+
-
R
INT
V
INFS
I
INT
-----------------
=
C
INT
t
INT
(
)
I
INT
(
)
V
INT
--------------------------------
=
V
INT
t
INT
(
)
I
INT
(
)
C
INT
--------------------------------
=
COUNT
1000
V
IN
V
REF
---------------
=
HI7106
4
Typical Integrator Amplifier Output Waveform (INT Pin)
Detailed Description
Analog Section
Figure 2 shows the Analog Section for the HI7106. Each
measurement cycle is divided into three phases. They are
(1) auto-zero (A-Z), (2) signal integrate (INT) and (3) de-inte-
grate (DE).
Auto-Zero Phase
During auto-zero three things happen. First, input high and
low are disconnected from the pins and internally shorted to
analog COMMON. Second, the reference capacitor is
charged to the reference voltage. Third, a feedback loop is
closed around the system to charge the auto-zero capacitor
C
AZ
to compensate for offset voltages in the buffer amplifier,
integrator, and comparator. Since the comparator is included
in the loop, the A-Z accuracy is limited only by the noise of
the system. In any case, the offset referred to the input is
less than 10
V.
Signal Integrate Phase
During signal integrate, the auto-zero loop is opened, the
internal short is removed, and the internal input high and low
are connected to the external pins. The converter then
integrates the differential voltage between IN HI and IN LO
for a fixed time. This differential voltage can be within a wide
common mode range: up to 1V from either supply. If, on the
other hand, the input signal has no return with respect to the
converter power supply, IN LO can be tied to analog
COMMON to establish the correct common mode voltage. At
the end of this phase, the polarity of the integrated signal is
determined.
AUTO ZERO PHASE
(COUNTS)
2999 - 1000
SIGNAL INTEGRATE
PHASE FIXED
1000 COUNTS
DE-INTEGRATE PHASE
0 - 1999 COUNTS
TOTAL CONVERSION TIME = 4000 x t
CLOCK
= 16,000 x t
OSC
FIGURE 2. ANALOG SECTION OF HI7106
DE-
DE+
C
INT
C
AZ
R
INT
BUFFER
A-Z
INT
-
+
A-Z
COMPARATOR
IN HI
COMMON
IN LO
31
32
30
DE-
DE+
INT
A-Z
34
C
REF
+
36
REF HI
C
REF
REF LO
35
A-Z
A-Z
33
C
REF
-
28
29
27
TO
DIGITAL
SECTION
A-Z AND DE( )
INTEGRATOR
INT
STRAY
STRAY
V+
10mA
V-
N
INPUT
HIGH
2.8V
6.2V
V+
1
INPUT
LOW
-
+
-
+
-
+
HI7106
5
De-Integrate Phase
The final phase is de-integrate, or reference integrate. Input
low is internally connected to analog COMMON and input
high is connected across the previously charged reference
capacitor. Circuitry within the chip ensures that the capacitor
will be connected with the correct polarity to cause the
integrator output to return to zero. The time required for the
output to return to zero is proportional to the input signal.
Specifically the digital reading displayed is:
.
Differential Input
The input can accept differential voltages anywhere within
the common mode range of the input amplifier, or specifically
from 0.5V below the positive supply to 1V above the
negative supply. In this range, the system has a CMRR of
86dB typical. However, care must be exercised to assure the
integrator output does not saturate. A worst case condition
would be a large positive common mode voltage with a near
full scale negative differential input voltage. The negative
input signal drives the integrator positive when most of its
swing has been used up by the positive common mode
voltage. For these critical applications the integrator output
swing can be reduced to less than the recommended 2V full
scale swing with little loss of accuracy. The integrator output
can swing to within 0.3V of either supply without loss of
linearity.
Differential Reference
The reference voltage can be generated anywhere within the
power supply voltage of the converter. The main source of
common mode error is a roll-over voltage caused by the
reference capacitor losing or gaining charge to stray capacity
on its nodes. If there is a large common mode voltage, the
reference capacitor can gain charge (increase voltage) when
called up to de-integrate a positive signal but lose charge
(decrease voltage) when called up to de-integrate a negative
input signal. This difference in reference for positive or
negative input voltage will give a roll-over error. However, by
selecting the reference capacitor such that it is large enough
in comparison to the stray capacitance, this error can be
held to less than 0.5 count worst case. (See Component
Value Selection.)
Analog COMMON
This pin is included primarily to set the common mode voltage
for battery operation or for any system where the input signals
are floating with respect to the power supply. The COMMON
pin sets a voltage that is approximately 2.8V more negative
than the positive supply. This is selected to give a minimum
end-of-life battery voltage of about 6V. However, analog COM-
MON has some of the attributes of a reference voltage. When
the total supply voltage is large enough to cause the zener to
regulate (>7V), the COMMON voltage will have a low voltage
coefficient (0.001%/V), low output impedance (
15
), and a
temperature coefficient typically less than 80ppm/
o
C. An exter-
nal reference can easily be added, as shown in Figure 3.
Analog COMMON is also used as the input low return during
auto-zero and de-integrate. If IN LO is different from analog
COMMON, a common mode voltage exists in the system
and is taken care of by the excellent CMRR of the converter.
However, in some applications IN LO will be set at a fixed
known voltage (power supply common for instance). In this
application, analog COMMON should be tied to the same
point, thus removing the common mode voltage from the
converter. The same holds true for the reference voltage. If
reference can be conveniently tied to analog COMMON, it
should be since this removes the common mode voltage
from the reference system.
Within the lC, analog COMMON is tied to an N-Channel FET
that can sink approximately 30mA of current to hold the
voltage 2.8V below the positive supply (when a load is trying
to pull the common line positive). However, there is only
10
A of source current, so COMMON may easily be tied to a
more negative voltage thus overriding the internal reference.
TEST
The TEST pin serves two functions. On the HI7106 it is cou-
pled to the internally generated digital supply through a
500
resistor. Thus it can be used as the negative supply for
externally generated segment drivers such as decimal points
or any other presentation the user may want to include on
the LCD display. Figures 4 and 5 show such an application.
No more than a 1mA load should be applied.
DISPLAY COUNT = 1000
V
IN
V
REF
---------------
FIGURE 3A.
FIGURE 3B.
FIGURE 3. USING AN EXTERNAL REFERENCE
HI7106
V
REF LO
REF HI
V+
V-
6.8V
ZENER
I
Z
HI7106
V
REF HI
REF LO
COMMON
V+
ICL8069
1.2V
REFERENCE
6.8k
20k
HI7106
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