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Электронный компонент: HI9P0508-5

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1
File Number
3142.2
HI-506, HI-507, HI-508, HI-509
Single 16 and 8/Differential 8-Channel and
4-Channel CMOS Analog Multiplexers
The HI-506/HI-507 and HI-508/HI-509 monolithic CMOS
multiplexers each include an array of sixteen and eight
analog switches respectively, a digital decoder circuit for
channel selection, voltage reference for logic thresholds, and
an enable input for device selection when several
multiplexers are present. The Dielectric Isolation (DI)
process used in fabrication of these devices eliminates the
problem of latchup. DI also offers much lower substrate
leakage and parasitic capacitance than conventional
junction isolated CMOS (see Application Notes AN520 and
AN521).
The switching threshold for each digital input is established by
an internal +5V reference, providing a guaranteed minimum
2.4V for logic "1" and maximum 0.8V for logic "0". This allows
direct interface without pullup resistors to signals from most
logic families: CMOS, TTL, DTL and some PMOS. For
protection against transient overvoltage, the digital inputs
include a series 200
resistor and diode clamp to each
supply.
The HI-506 is a single 16-Channel, the HI-507 is an
8-Channel differential, the HI-508 is a single 8-Channel and
the HI-509 is a 4-Channel differential multiplexer.
If input overvoltages are present, the HI-546/HI-547/HI-548/
HI-549 multiplexers are recommended.
Features
Low ON Resistance . . . . . . . . . . . . . . . . . . . . . . . . . 180
Wide Analog Signal Range
. . . . . . . . . . . . . . . . . . . . .
15V
TTL/CMOS Compatible
Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns
Maximum Power Supply . . . . . . . . . . . . . . . . . . . . . . . .44V
Break-Before-Make Switching
No Latch-Up
Replaces DG506A/DG506AA and DG507A/DG507AA
Replaces DG508A/DG508AA and DG509A/DG509AA
Applications
Data Acquisition Systems
Precision Instrumentation
Demultiplexing
Selector Switch
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG.
NO.
HI9P0506-9
-40 to 85
28 Ld SOIC
M28.3
HI3-0506-5
0 to 75
28 Ld PDIP
E28.6
HI4P0506-5
0 to 75
28 Ld PLCC
N28.45
HI1-0506-5
0 to 75
28 Ld CERDIP
F28.6
HI1-0506-4
-25 to 85
28 Ld CERDIP
F28.6
HI1-0506-2
-55 to 125
28 Ld CERDIP
F28.6
HI4P0507-5
0 to 75
28 Ld PLCC
N28.45
HI3-0507-5
0 to 75
28 Ld PDIP
E28.6
HI1-0507-2
-55 to 125
28 Ld CERDIP
F28.6
HI1-0508-5
0 to 75
16 Ld CERDIP
F16.3
HI3-0508-5
0 to 75
16 Ld PDIP
E16.3
HI1-0508-4
-25 to 85
16 Ld CERDIP
F16.3
HI1-0508-2
-55 to 125
16 Ld CERDIP
F16.3
HI4P0508-5
0 to 75
20 Ld PLCC
N20.35
HI9P0508-9
-40 to 85
16 Ld SOIC
M16.15
HI9P0508-5
0 to 75
16 Ld SOIC
M16.15
HI9P0509-5
0 to 75
16 Ld SOIC
M16.15
HI1-0509-4
-25 to 85
16 Ld CERDIP
F16.3
HI1-0509-5
0 to 75
16 Ld CERDIP
F16.3
HI3-0509-5
0 to 75
16 Ld PDIP
E16.3
HI4P0509-5
0 to 75
20 Ld PLCC
N20.35
HI1-0509-2
-55 to 125
16 Ld CERDIP
F16.3
Data Sheet
June 1999
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
2
Pinouts
HI-506
(PDIP, CERDIP, SOIC)
TOP VIEW
HI-507
(PDIP, CERDIP)
TOP VIEW
HI-506
(PLCC)
TOP VIEW
HI-507
(PLCC)
TOP VIEW
+V
SUPPLY
NC
NC
IN 16
IN 15
IN 14
IN 13
IN 12
IN 11
IN 10
IN 9
GND
NC
ADDRESS A
3
OUT
IN 8
IN 7
IN 6
IN 5
IN 3
IN 1
ENABLE
ADDRESS A
0
ADDRESS A
1
ADDRESS A
2
-V
SUPPLY
IN 4
IN 2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
+V
SUPPLY
OUT B
NC
IN 8B
IN 7B
IN 6B
IN 5B
IN 4B
IN 3B
IN 2B
IN 1B
GND
NC
NC
OUT A
IN 8A
IN 7A
IN 6A
IN 5A
IN 3A
IN 1A
ENABLE
ADDRESS A
0
ADDRESS A
1
ADDRESS A
2
-V
SUPPLY
IN 4A
IN 2A
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
IN 15
IN 14
IN 13
IN 12
IN 11
IN 10
IN 9
IN 16
NC
NC
+V
SUPPL
Y
OUT
-V
SUPPL
Y
IN 8
GND
NC
A
3
A
2
A
1
ENABLE
A
0
IN 7
IN 6
IN 5
IN 4
IN 3
IN 2
IN 1
11
10
5
6
7
8
9
23
24
25
22
21
20
19
14
15
16
17
18
12
13
3
2
1
4
28
27
26
IN 7B
IN 6B
IN 5B
IN 4B
IN 3B
IN 2B
IN 1B
IN 8B
NC
OUT B
+V
SUPPL
Y
OUT A
-V
SUPPL
Y
IN 8A
GND
NC
NC
A
2
A
1
ENABLE
A
0
IN 7A
IN 6A
IN 5A
IN 4A
IN 3A
IN 2A
IN 1A
11
10
5
6
7
8
9
23
24
25
22
21
20
19
14
15
16
17
18
12
13
3
2
1
4
28
27
26
HI-506, HI-507, HI-508, HI-509
3
HI-508
(PDIP, CERDIP, SOIC)
TOP VIEW
HI-509
(PDIP, CERDIP, SOIC)
TOP VIEW
HI-508
(PLCC)
TOP VIEW
HI-509
(PLCC)
TOP VIEW
Pinouts
(Continued)
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
A
0
ENABLE
-V
SUPPLY
IN 1
IN 2
IN 3
OUT
IN 4
A
1
GND
+V
SUPPLY
IN 5
IN 6
IN 7
IN 8
A
2
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
A
0
ENABLE
-V
SUPPLY
IN 1A
IN 2A
IN 3A
OUT A
IN 4A
A
1
+V
SUPPLY
IN 1B
IN 2B
IN 3B
IN 4B
OUT B
GND
-V
SUPPLY
IN 1
NC
IN 2
IN 3
ENABLE
A
0
NC
A
1
A
2
IN 4
OUT
NC
IN 8
IN 7
GND
+V
SUPPLY
NC
IN 5
IN 6
4
5
6
7
8
10
11
12
13
9
3
2
1
20
19
16
17
18
15
14
-V
SUPPLY
IN 1A
NC
IN 2A
IN 3A
ENABLE
A
0
NC
A
1
GND
IN 4A
OUT A
NC
OUT B
IN 4B
+V
SUPPLY
IN 1B
NC
IN 2B
IN 3B
4
5
6
7
8
10
11
12
13
9
3
2
1
20
19
16
17
18
15
14
HI-506, HI-507, HI-508, HI-509
4
Truth Tables
HI-506
A
3
A
2
A
1
A
0
EN
"ON" CHANNEL
X
X
X
X
L
None
L
L
L
L
H
1
L
L
L
H
H
2
L
L
H
L
H
3
L
L
H
H
H
4
L
H
L
L
H
5
L
H
L
H
H
6
L
H
H
L
H
7
L
H
H
H
H
8
H
L
L
L
H
9
H
L
L
H
H
10
H
L
H
L
H
11
H
L
H
H
H
12
H
H
L
L
H
13
H
H
L
H
H
14
H
H
H
L
H
15
H
H
H
H
H
16
HI-507
A
2
A
1
A
0
EN
"ON" CHANNEL
X
X
X
L
None
L
L
L
H
1
L
L
H
H
2
L
H
L
H
3
L
H
H
H
4
H
L
L
H
5
H
L
H
H
6
H
H
L
H
7
H
H
H
H
8
HI-508
A
2
A
1
A
0
EN
"ON" CHANNEL
X
X
X
L
None
L
L
L
H
1
L
L
H
H
2
L
H
L
H
3
L
H
H
H
4
H
L
L
H
5
H
L
H
H
6
H
H
L
H
7
H
H
H
H
8
HI-509
A
1
A
0
EN
"ON" CHANNEL PAIR
X
X
L
None
L
L
H
1
L
H
H
2
H
L
H
3
H
H
H
4
HI-506, HI-507, HI-508, HI-509
5
Functional Diagrams
HI-506
HI-507
HI-508
HI-509
DECODER/
DRIVER
OUT
IN 1
IN 2
IN 16
DIGITAL
PROTECTION
A
0
A
1
A
2
A
3
EN
INPUT
LEVEL
SHIFT
5V
REF
DECODER/
DRIVER
OUT B
IN 8A
IN 1A
IN 1B
DIGITAL
PROTECTION
A
0
A
1
A
2
EN
INPUT
LEVEL
SHIFT
5V
REF
OUT A
IN 8B
DECODER/
DRIVER
OUT
IN 1
IN 2
IN 8
DIGITAL
PROTECTION
A
0
A
1
A
2
EN
INPUT
LEVEL
SHIFT
5V
REF
DECODER/
DRIVER
OUT B
IN 4A
IN 1A
IN 1B
DIGITAL
PROTECTION
A
0
A
1
EN
INPUT
LEVEL
SHIFT
5V
REF
OUT A
IN 4B
HI-506, HI-507, HI-508, HI-509