151
TM
March 1997
HM-6514/883
1024 x 4 CMOS RAM
Features
This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
Low Power Standby. . . . . . . . . . . . . . . . . . . 125
W Max
Low Power Operation . . . . . . . . . . . . . .35mW/MHz Max
Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min
TTL Compatible Input/Output
Common Data Input/Output
Three-State Output
Standard JEDEC Pinout
Fast Access Time . . . . . . . . . . . . . . . . . 120/200ns Max
18 Pin Package for High Density
Gated Inputs - No Pull Up or Pull Down Resistors
Required
On-Chip Address Register
Description
The HM-6514/883 is a 1024 x 4 static CMOS RAM fabri-
cated using self-aligned silicon gate technology. The device
utilizes synchronous circuitry to achieve high performance
and low power operation.
On chip latches are provided for addresses allowing efficient
interfacing with microprocessor systems. The data output
can be forced to a high impedance state for use in expanded
memory arrays.
Gated inputs allow lower operating current and also eliminates
the need for pull up or pull down resistors. The HM-6514/883 is
fully static RAM and may be maintained in any state for an
indefinite period of time.
Data retention supply voltage and supply current are guaran-
teed over temperature.
Ordering Information
Pinout
HM-6514/883
(CERDIP)
TOP VIEW
120ns
200ns
300ns
TEMPERATURE RANGE
PACKAGE
PKG. NO.
HM1-6514S/883
HM1-6514B/883
HM1-6514/883
-55
o
C to 125
o
C
CERDIP
F18.3
PIN
DESCRIPTION
A
Address Input
E
Chip Enable
W
Write Enable
D
Data Input
Q
Data Output
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1
VCC
A8
A9
DQ0
DQ1
DQ2
DQ3
A7
W
A6
A5
A4
A3
A0
A1
E
A2
GND
FN2996.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
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Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002. All Rights Reserved
152
Functional Diagram
64
A
6
6
4
L
G
A
A9
A8
A7
A6
A5
A4
64 x 64
MATRIX
G
A2
A1
A0
A3
E
W
LATCHED
ADDRESS
REGISTER
A
4
4
A
L
16 16 16 16
1 OF 4
DQ
LATCHED
ADDRESS
REGISTER
GATED
ROW
DECODER
LSB
LSB
GATED
COLUMN
I/O SELECT
HM-6514/883
153
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
JA
JC
CERDIP Package . . . . . . . . . . . . . . . .
75
o
C/W
15
o
C/W
Maximum Storage Temperature Range . . . . . . . . .-65
o
C to +150
o
C
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175
o
C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300
o
C
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6910 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range. . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V
Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . VCC -2.0V to VCC
Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max
TABLE 1. HM-6514/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER
SYMBOL
(NOTE 1)
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Output Low Voltage
VOL
VCC = 4.5V
IOL = 3.2mA
1, 2, 3
-55
o
C
T
A
+125
o
C
-
0.4
V
Output High Voltage
VOH
VCC = 4.5V
IOH = -1.0mA
1, 2, 3
-55
o
C
T
A
+125
o
C
2.4
-
V
Input Leakage Current
II
VCC = 5.5V,
VI = GND or VCC
1, 2, 3
-55
o
C
T
A
+125
o
C
-1.0
+1.0
A
Input/Output Leakage
Current
IIOZ
VCC = 5.5 V,
VIO = GND or VCC
1, 2, 3
-55
o
C
T
A
+125
o
C
-1.0
+1.0
A
Data Retention Supply
Current
ICCDR
VCC = 2.0V,
E = VCC -0.3V,
IO = 0mA
1, 2, 3
-55
o
C
T
A
+125
o
C
-
25
A
Operating Supply
Current
ICCOP
VCC = 5.5V, (Note 2)
E = 1MHz
1, 2, 3
-55
o
C
T
A
+125
o
C
-
7
mA
Standby Supply
Current
ICCSB
VCC = 5.5V,
E = VCC-0.3V,
IO = 0mA
1, 2, 3
-55
o
C
T
A
+125
o
C
-
50
A
NOTES:
1. All voltages referenced to device GND.
2. Typical derating 1.5mA/MHz increase in ICCOP.
HM-6514/883
154
TABLE 2. HM-6514/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER
SYMBOL
(NOTES 1, 2)
CONDITIONS
GROUP
A SUB-
GROUPS
TEMPERA-
TURE
LIMITS
UNITS
HM-6514S/883
HM-6514B/883
HM-6514/883
MIN
MAX
MIN
MAX
MIN
MAX
Chip Enable
Access Time
(1) TELQV
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
-
120
-
200
-
300
ns
Address Access
Time
(2) TAVQV
VCC = 4.5 and
5.5V, Note 3
9, 10, 11
-55
o
C
T
A
+125
o
C
-
120
-
220
-
320
ns
Chip Enable
Pulse Negative
Width
(5) TELEH
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
120
-
200
-
300
-
ns
Chip Enable
Pulse Positive
Width
(6) TEHEL
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
50
-
90
-
120
-
ns
Address Setup
Time
(7) TAVEL
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
0
-
20
-
20
-
ns
Address Hold
Time
(8) TELAX
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
40
-
50
-
50
-
ns
Write Enable
Pulse Width
(9) TWLWH
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
120
-
200
-
300
-
ns
Write Enable
Pulse Setup
Time
(10) TWLEH
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
120
-
200
-
300
-
ns
Write Enable
Pulse Hold Time
(11) TELWH
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
120
-
200
-
300
-
ns
Data Setup Time
(12) TDVWH
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
50
-
120
-
200
-
ns
Data Hold Time
(13) TWHDX
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
0
-
0
-
0
-
ns
Write Data Delay
Time
(14) TWLDV
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
70
-
80
-
100
-
ns
Early Output
High-Z Time
(15) TWLEL
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
0
-
0
-
0
-
ns
Late Output
High-Z Time
(16) TEHWH
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
0
-
0
-
0
-
ns
Read or Write
Cycle Time
(17) TELEL
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
170
-
290
-
420
-
ns
NOTES:
1. All voltages referenced to device GND.
2. Input pulse levels: 0.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate
equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
3. TAVQV = TELQV + TAVEL.
HM-6514/883
155
TABLE 3. HM-6514/883 ELECTRICAL PERFORMANCE SPECIFICATIONS
PARAMETER
SYMBOL
CONDITIONS
NOTE
TEMPERATURE
HM-6514/883
UNITS
LIMITS
MIN
MAX
Input Capacitance
CI
VCC = Open, f = 1MHz, All
Measurements Referenced
to Device Ground
1
T
A
= +25
o
C
-
8
pF
Input/Output
Capacitance
CIO
VCC = Open, f = 1MHz, All
Measurements Referenced
to Device Ground
1
T
A
= +25
o
C
-
10
pF
Chip Enable Output
Disable Time
TELQX
VCC = 4.5 and 5.5V
1
-55
o
C
T
A
+125
o
C
5
-
Chip Enable Output
Disable Time
TEHQZ
VCC = 4.5 and 5.5V
HM-6514S/883
1
-55
o
C
T
A
+125
o
C
-
50
ns
VCC = 4.5 and 5.5V
HM-6514B/883
1
-55
o
C
T
A
+125
o
C
-
80
ns
VCC = 4.5 and 5.5V
HM-6514/883
1
-55
o
C
T
A
+125
o
C
-
100
ns
High Level Output
Voltage
VOH2
VCC = 4.5V, IO = -100
A
1
-55
o
C
T
A
+125
o
C
VCC -0.4
-
V
NOTES:
1. The parameters listed in Table 3 are controlled via design, or process parameters are characterized upon initial design and after major
process and/or design changes.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
SUBGROUPS
Initial Test
100%/5004
-
Interim Test
100%/5004
1, 7, 9
PDA
100%/5004
1
Final Test
100%/5004
2, 3, 8A, 8B, 10, 11
Group A
Samples/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Groups C & D
Samples/5005
1, 7, 9
HM-6514/883
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