1
File Number
3025.3
HS-5104ARH
Radiation Hardened Low Noise Quad
Operational Amplifier
The HS-5104ARH is a radiation hardened, monolithic quad
operational amplifier that provides highly reliable
performance in harsh radiation environments. Its excellent
noise characteristics coupled with an unique array of
dynamic specifications make this amplifier well-suited for a
variety of satellite system applications. Dielectrically
isolated, bipolar processing makes this device immune to
Single Event Latch-Up.
The HS-5104ARH shows almost no change in offset voltage
after exposure to 100kRAD(Si) gamma radiation, with only a
minor increase in current. Complementing these specifications
is a post radiation open loop gain in excess of 40K.
This quad operational amplifier is available in an industry
standard pinout, allowing for immediate interchangeability
with most other quad operational amplifiers.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95690. A "hot-link" is provided
on our homepage for downloading.
http://www.intersil.com/spacedefense/space.htm
Features
Electrically Screened to SMD # 5962-95690
QML Qualified per MIL-PRF-38535 Requirements
Radiation Environment
- Gamma Dose (
) . . . . . . . . . . . . . . . . . 1 x 10
5
RAD(Si)
Low Noise
- At 1kHz . . . . . . . . . . . . . . . . . . . . . . . . 4.3nV/
Hz (Typ)
- At 1kHz . . . . . . . . . . . . . . . . . . . . . . . . 0.6pA/
Hz (Typ)
Low Offset Voltage . . . . . . . . . . . . . . . . . . . . 3.0mV (Max)
High Slew Rate . . . . . . . . . . . . . . . . . . . . . . 2.0V/
s (Typ)
Gain Bandwidth Product . . . . . . . . . . . . . . . 8.0MHz (Typ)
Applications
High Q, Active Filters
Voltage Regulators
Integrators
Signal Generators
Voltage References
Space Environments
Pinouts
HS-5104ARH (SBDIP) CDIP2-T14
TOP VIEW
HS-5104ARH (FLATPACK) CDFP3-F14
TOP VIEW
Ordering Information
ORDERING NUMBER
INTERNAL
MKT. NUMBER
TEMP. RANGE
(
o
C)
5962R9569001V9A
HS0-5104ARH-Q
25
5962R9569001VCC
HS1-5104ARH-Q
-55 to 125
5962R9569001VXC
HS9-5104ARH-Q
-55 to 125
HS1-5104ARH/PROTO
HS1-5104ARH/PROTO
-55 to 125
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V+
OUT 1
-IN1
+IN1
+IN2
-IN2
OUT 2
V-
OUT 3
OUT 4
-IN3
+IN3
+IN4
-IN4
V+
OUT 1
-IN1
+IN1
+IN2
-IN2
OUT 2
V-
OUT 3
OUT 4
-IN3
+IN3
+IN4
-IN4
14
13
12
11
10
9
8
2
3
4
5
6
7
1
Data Sheet
August 1999
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
2
Burn-In Circuit
NOTES:
1. R1 = R2 = R3 = R4 = 1MW, 5%, 1/4W (Min)
2. C1 = C2 = 0.01
F/Socket (Min) or 0.1
F/Row (Min)
3. D1 = D2 = IN4002 or Equivalent/Board
4. |(V+) - (V-)| = 31V
1V
Irradiation Circuit
NOTES:
5. +V = 15V
6. -V = -15V
7. Group E Sample Size = 4 Die Per Wafer
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1
4
2
3
C1
D1
+V
C2
D2
-V
R2
R1
R3
R4
+
-
+
-
+
-
+
-
+
+15V
-15V
(ONE OF FOUR)
-
HS-5104ARH
3
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Die Characteristics
DIE DIMENSIONS:
95 mils x 99 mils x 19 mils
1 mils
(2420
m x 2530
m x 483
m
25.4
m)
INTERFACE MATERIALS:
Glassivation:
Type: Nitride (SI3N4) over Silox (SIO2, 5% Phos.)
Silox Thickness: 12k
2k
Nitride Thickness: 3.5k
1.5k
Top Metallization:
Type: Al, 1% Cu
Thickness: 16k
2k
Substrate:
Bipolar Dielectric Isolation
Backside Finish:
Silicon
ASSEMBLY RELATED INFORMATION:
Substrate Potential (Powered Up):
Unbiased
ADDITIONAL INFORMATION:
Worst Case Current Density:
<2.0 x 10
5
A/cm
2
Transistor Count:
175
Metallization Mask Layout
HS-5104ARH
+IN2
V+
+IN1
-IN1
OUT1
OUT4
-IN4
-IN3
OUT3
OUT2
-IN2
+IN4
V-
+IN3
HS-5104ARH
PDF 
ZIP