FN2485.7

HSP45116

Numerically Controlled
Oscillator/Modulator

The Intersil HSP45116 combines a high performance
quadrature Numerically Controlled Oscillator (NCO) and a
high speed 16-bit Complex Multiplier/Accumulator (CMAC)
on a single IC. This combination of functions allows a
complex vector to be multiplied by the internally generated
(cos, sin) vector for quadrature modulation and
demodulation. As shown in the Block Diagram, the
HSP45116 is divided into three main sections. The
Phase/Frequency Control Section (PFCS) and the
Sine/Cosine Section together form a complex NCO. The
CMAC multiplies the output of the Sine/ Cosine Section with
an external complex vector.

The inputs to the Phase/Frequency Control Section consist
of a microprocessor interface and individual control lines.
The phase resolution of the PFCS is 32 bits, which results in
frequency resolution better than 0.008Hz at 33MHz. The
output of the PFCS is the argument of the sine and cosine.
The spurious free dynamic range of the complex sinusoid is
greater than 90dBc.

The output vector from the Sine/Cosine Section is one of the
inputs to the Complex Multiplier/Accumulator. The CMAC
multiplies this (cos, sin) vector by an external complex vector
and can accumulate the result. The resulting complex vectors
are available through two 20-bit output ports which maintain
the 90dB spectral purity. This result can be accumulated
internally to implement an accumulate and dump filter.

A quadrature down converter can be implemented by
loading a center frequency into the Phase/Frequency
Control Section. The signal to be down converted is the
Vector Input of the CMAC, which multiplies the data by the
rotating vector from the Sine/Cosine Section. The resulting
complex output is the down converted signal.

Features

· NCO and CMAC on One Chip

· 15MHz, 25.6MHz, 33MHz Versions

· 32-Bit Frequency Control

· 16-Bit Phase Modulation

· 16-Bit CMAC

· 0.008Hz Tuning Resolution at 33MHz

· Spurious Frequency Components < -90dBc

· Fully Static CMOS

Applications

· Frequency Synthesis

· Modulation - AM, FM, PSK, FSK, QAM

· Demodulation, PLL

· Phase Shifter

· Polar to Cartesian Conversions

Block Diagram

Ordering Information

PART NUMBER

TEMP.

RANGE (

PACKAGE

PKG. NO.

HSP45116VC-15

0 to 70

160 Ld MQFP Q160.28x28

HSP45116VC-25

0 to 70

160 Ld MQFP Q160.28x28

HSP45116GC-15

0 to 70

145 Ld CPGA G145.A

HSP45116GC-25

0 to 70

145 Ld CPGA G145.A

HSP45116GC-33

0 to 70

145 Ld CPGA G145.A

HSP45116GI-15

-40 to 85

145 Ld CPGA G145.A

HSP45116GI-25

-40 to 85

145 Ld CPGA G145.A

HSP45116GI-33

-40 to 85

145 Ld CPGA G145.A

HSP45116GM-15/883

-55 to 125

145 Ld CPGA G145.A

HSP45116GM-25/883

-55 to 125

145 Ld CPGA G145.A

HSP45116AVC-52

0 to 70

160 Ld MQFP Q160.28x28

This part has its own data sheet under HSP45116A,
Document # FN4156.

PHASE/

FREQUENCY

CONTROL

SECTION

SINE/

COSINE

SECTION

CMAC

SINE/

COSINE

ARGUMENT

SIN

COS

VECTOR INPUT

VECTOR OUTPUT

MICROPROCESSOR

INTERFACE

INDIVIDUAL

CONTROL SIGNALS

Data Sheet

May 1999

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Intersil (and design) is a trademark of Intersil Americas Inc.

Pinouts

145 PIN PGA

TOP VIEW

GND

IMIN

INDEX

RIN

ACC

CLK

MOD

ENOF

REG

PACO

DET

OEREXT

OEI

OEIEXT

DET

OER

TICO

PACI

BINFMT

PEAK

ENPH

REG

MOD

LOAD

CLROFR

ENI

ENCF

REG

ENTIREG

MODPI

/2PI

RBYTILD

RIN

PMSEL

ENPHAC

IMIN

GND

IMIN

RIN

IMIN

RIN

OUT-

MUX

OUT-

MUX

HSP45116

145 PIN PGA

BOTTOM VIEW

Pinouts

(Continued)

GND

IMIN

INDEX

RIN

ACC

CLK

MOD

ENOF

REG

PACO

DET

OEREXT

OEI

OEIEXT

DET

OER

TICO

PACI

BINFMT

PEAK

ENPH

REG

MOD

LOAD

CLROFR

ENI

ENCF

REG

ENTIREG

MODPI

/2PI

RBYTILD

RIN

PMSEL

ENPHAC

IMIN

GND

IMIN

RIN

IMIN

RIN

OUT-

MUX

OUT-

MUX

HSP45116

160LEAD MQFP

TOP VIEW

Pinouts

(Continued)

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39

119

120

118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81

RO9
V

RO8
RO7

RO6
RO5

GND

RO10

RO18
RO17
RO16
RO15

RO13
RO12
RO11
GND

RO14

GND

IO6
IO5
IO4
IO3

IO2
IO1
V

IO0
RO19

GND

RO2
RO1
RO0

DET1
DET0

GND

RO4
RO3

ROF

ENCF

REG

ENPHAC

ENT

I
REG

ENI

I/2P

AD1

AD0

OUT

REXT

ACO

MOD1

TICO

GND

RBYTILD

MOD0

PACI

LOAD

PMSEL

PEAK

RIN0

SH1
SH0

ACC

ENPHREG
ENOFREG

BINFMT

RIN6

RIN7

RIN8

RIN9

RIN11

RIN5
RIN4
RIN3
RIN2

GND

RIN12

RIN17

RIN18

IMIN0

RIN16
RIN15
RIN14

GND

RIN13

RIN10

IO7

IO8

IO9

GND

IO1

GND

IO1

IMI

GND

IMI

GND

IMI

RIN1

HSP45116

Pin Description

NAME

NUMBER

TYPE

DESCRIPTION

A1, A9, A15, G1,

J15, Q1, Q7, Q15

+5V Power supply input.

GND

A8, A14, B1, H1,

H15, P15, Q2, Q8

Power supply ground input.

C0-15

N8-11, P8-13,

Q9-14

Control input bus for loading phase and frequency data into the PFCS. C15 is the MSB.

AD0-1

N7, P7

Address pins for selecting destination of C0-15 data.

Chip Select (active low).

Write Enable. Data is clocked into the register selected by AD0-1 on the rising edge of WR when
the CS line is low.

CLK

Clock. All registers, except the control registers clocked with WR, are clocked (when enabled)
by the rising edge of CLK.

ENPHREG

Phase Register Enable (active low). Registered on chip by CLK. When active, after being
clocked onto chip, ENPHREG enables the clocking of data into the phase register.

ENOFREG

Frequency Offset Register Enable (active Low). Registered on chip by CLK. When active, after
being clocked onto chip, ENOFREG enables clocking of data into the frequency offset register.

ENCFREG

Center Frequency Register Enable (active low). Registered on chip by CLK. When active, after
being clocked onto chip, ENCFREG enables clocking of data into the center frequency register.

ENPHAC

Phase Accumulator Register Enable (active low). Registered on chip by CLK. When active, after
being clocked onto chip, ENPHAC enables clocking of the phase accumulator register.

ENTIREG

Time Interval Control Register Enable (active low). Registered on chip by CLK. When active,
after being clocked onto chip, ENTIREG enables clocking of data into the time accumulator
register.

ENI

Real and Imaginary Data Input Register (RIR, IIR) Enable (active low). Registered on chip by
CLK. When active, after being clocked onto chip, ENI enables clocking of data into the real and
imaginary input data register.

MODPI/2PI

Modulo

Select. When low, the Sine and Cosine ROMs are addressed modulo 2

(360

degrees). When high, the most significant address bit is held low so that the ROMs are
addressed modulo

(180 degrees). This input is registered on chip by clock.

CLROFR

Frequency Offset Register Output Zero (active low). Registered on chip by CLK. When active,
after being clocked onto chip, CLROFR zeros the data path from the frequency offset register to
the frequency adder. New data can still be clocked into the frequency offset register; CLROFR
does not affect the contents of the register.

LOAD

Phase Accumulator Load Control (active low). Registered on chip by CLK. Zeroes feedback
path in the phase accumulator without clearing the phase accumulator register.

MOD0-1

M3, N3

External Modulation Control Bits. When selected with the PMSEL line, these bits add a 0, 90,
180, or 270 degree offset to the current phase in the phase accumulator. The lower 14 bits of
the phase control path are set to zero.

These bits are loaded into the phase register when ENPHREG is low.

PMSEL

Phase Modulation Select Line. This line determines the source of the data clocked into the phase
register. When high, the phase control register is selected. When low, the external modulation pins
(MOD0-1) are selected for the most significant two bits and the least significant two bits and the
least significant 14 bits are set to zero. This control is registered by CLK.

RBYTILD

ROM Bypass, Timer Load. Active low, registered by CLK. This input bypasses the sine/ cosine
ROM so that the 16-bit phase adder output and lower 16 bits of the phase accumulator go
directly to the CMAC's sine and cosine inputs, respectively. It also enables loading of the timer
accumulator register by zeroing the feedback in the accumulator.

PACI

Phase Accumulator Carry Input (active low). A low on this pin causes the phase accumulator to
increment by one, in addition to the values in the phase accumulator register and frequency
adder.

HSP45116

PACO

L13

Phase Accumulator Carry Output. Active low and registered by CLK. A low on this output
indicates that the phase accumulator has overflowed, i.e., the end of one sine/cosine cycle has
been reached.

TICO

Time Interval Accumulator Carry Output. Active low, registered by CLK. This output goes low
when a carry is generated by the time interval accumulator. This function is provided to time out
control events such as synchronizing register clocking to data timing.

RIN0-18

C1, C2, D1, D2, E1-

3, F1-3, G2, G3,

H2, H3, J1-3, K1,

Real Input Data Bus. This is the external real component into the complex multiplier. The bus is
clocked into the real input data register by CLK when ENI is asserted; two's complement.

IMIN0-18

A2-7, B2-7, C3-8,

Imaginary Input Data Bus. This is the external imaginary component into the complex multiplier.
The bus is clocked into the real input data register by CLK when ENI is asserted; two's
complement.

SH0-1

K3, L1

Shift Control Inputs. These lines control the input shifters of the RIN and IIN inputs of the
complex multiplier. The shift controls are common to the shifters on both of the busses.

ACC

Accumulate/Dump Control. This input controls the complex accumulators and their holding
registers. When high, the accumulators accumulate and the holding registers are disabled.
When low, the feedback in the accumulators is zeroed to cause the accumulators to load.

The holding registers are enabled to clock in the results of the accumulation. This input is
registered by CLK.

BINFMT

This input is used to convert the two's complement output to offset binary (unsigned) for
applications using D/A converters. When low, bits RO19 and IO19 are inverted from the internal
two's complement representation. This input is registered by CLK.

PEAK

This input enables the peak detect feature of the block floating point detector. When high, the
maximum bit growth in the output holding registers is encoded and output on the DET0-1 pins.
When the PEAK input is asserted, the block floating point detector output will track the maximum
growth in the holding registers, including the data in the holding registers at the time that PEAK
is activated.

OUTMUX0-1

N12, N13

These inputs select the data to be output on RO0-19 and IO0-19.

RO0-19

C15, D14, D15,

E14, E15, F13-15,

G13-15, H13, H14,

J13, J14, K13-15,

L15, M15

Real Output Data Bus. These Three-state outputs are controlled by OER and OEREXT.
OUTMUX0-1 select the data output on the bus.

IO0-19

A10-13, B8-15, C9-

14, D13, E13

Imaginary Output Data Bus. These Three-state outputs are controlled by OEI and OEIEXT.
OUTMUX0-1 select the data output on the bus.

DET0-1

N15, L14

These output pins indicate the number of bits of growth in the accumulators. While PEAK is low,
these pins indicate the peak growth. The detector examines bits 15-18, real and imaginary
accumulator holding registers and bits 30-33 of the real and imaginary CMAC holding registers.
The bits indicate the largest growth of the four registers.

OER

P14

Three-state control for bits RO0-15. Outputs are enabled when the line is low.

OEREXT

M13

Three-state control for bits RO16-19. Outputs are enabled when the line is low.

OEI

M14

Three-state control for bits IO0-15. Outputs are enabled when the line is low.

OEIEXT

N14

Three-state control for bits IO16-19. Outputs are enabled when the line is low.

Pin Description

(Continued)

NAME

NUMBER

TYPE

DESCRIPTION

HSP45116

Functional Block Diagram

SI
N

R.RBYT

I
L

R.
PM

SEL

R.ENPHREG

CL
K

ACI

PHASE

INP

GIS

PHEN

R.ENPHREG

INP

REG

I
ST
ER

LSE

SET

REGI

CENT

EQUENCY

GIS

R.PM

UENCY

ADDER

PHASE

GIS

R.
CL
RO

SEN

CL
K

R.
ENC

REG

R.L

R.ENOF

RE
G

(
1:

ENCODE

(
15:

PHASE

ACCUM

UL
A

ADDER

PHASE

ADDER

SIN/CO

16
M
S

16
LS

ACO

R.M

DPI/2

R.ENPHAC

PHASE

CCUM

UL
A

GIS

PH
A

ACCUM

UL
A

DE
C

DER

R.ENCF

REG

R.ENOF

REG

R.CL

ROF

R.L

R.ENPHAC

R.M

DPI/2

SE
L

ENCF

REG

CL
ROF

ENPHREG

ENPHAC

I/2
P

ENO

REG

CL
K

INCREM

R.ENT

I
REG

CARR

Y OUT

ACCUM

UL
A

GIS

R.RBYT

I
L

ADDER

AD(

:
0

)

ENTI

REG

R.ENT

I
RE
G

ACC

R.ENI

ENI

R.BINF

BINF

R.SH(

:
0

)

SH(

:
0

)

PE
AK

R.
PEAK

I
NE

/COS

IN
E

NE
RA
T

I
M

A
CCUM

UL
A

OUT

(
1

)

REXT

IE
X

O
P

ACO

RIN(

:
0

)

IM
IN(1

8:0

)

CL
K

PHASE

R.AC

R.
E

R.BI

NF
M

.
S

:0)

R.
PEAK

R.ACC

EQU

NCY

CL
K

ACI

0 1

MUX

1 0

MUX

0 1

MUX

0 1

MUX

1 0

MUX

RIN(

:
0

)

IM
IN(1

8:0

)

HSP4

51
1

Functional Block Diagram

(Continued)

ADDER

R1
.ACC

SHI

.
S

:0)

R.ENI

SI
N

COS

COM

IP
L

I
E

ADDER

COM

ACCUM

UL
A

ACCUM

UL
A

R.
PEAK

W
T

DET

(
1

:
0

)

:0)

(19

-
1

)

O(
15:

R.BINF

OUT

(
1

)

I
O

9-1

)
IO(

15
:0)

R.BINF

IE
X

R1.ACC

R2.ACC

UND

RIN0

-
1

I
M

I
N0
-
1

R.RBYT

I
L

R.
E

R.SH(1:0)

SI
N

COS

R.ACC

R.
PEAK

R.SH(

:
0

)

R.ENI

TMU

)

e T
a

e 4

CL
K

REG

CL
K

RE
G

CL
K

REG

CL
K

REG

CL
K

REG

CL
K

REG

CL
K

REG

CL
K

REG

CL
K

REG

CL
K

REG

CL
K

REG

CL
K

REG

CL
K

REG

CL
K

:0)

e T
a

l
e 4

1 0

MUX

CL
K

RE
G

PHASE

I
N

(
18:

IM
IN(1

HSP4

51
1

Functional Description

The Numerically Controlled Oscillator/Modulator (NCOM)
produces a digital complex sinusoid waveform whose
amplitude, phase and frequency are controlled by a set of
input command words. When used as a Numerically
Controlled Oscillator (NCO), it generates 16-bit sine and
cosine vectors at a maximum sample rate of 33MHz. The
NCOM can be preprogrammed to produce a constant (CW)
sine and cosine output for Direct Digital Synthesis (DDS)
applications. Alternatively, the phase and frequency inputs
can be updated in real time to produce a FM, PSK, FSK, or
MSK modulated waveform. The Complex Multiplier/
Accumulator (CMAC) can be used to multiply this waveform
by an input signal for AM and QAM signals. By stepping the
phase input, the output of the ROM becomes an FFT twiddle
factor; when data is input to the Vector Inputs (see Block
Diagram), the NCOM calculates an FFT butterfly.

As shown in the Block Diagram, the NCOM consists of three
parts: Phase and Frequency Control Section (PFCS),
Sine/Cosine Generator, and CMAC. The PFCS stores the
phase and frequency inputs and uses them to calculate the
phase angle of a rotating complex vector. The Sine/Cosine
Generator performs a lookup on this phase and outputs the
appropriate values for the sine and cosine. The sine and
cosine form one set of inputs to the CMAC, which multiplies
them by the input vector to form the modulated output.

Phase and Frequency Control Section

The phase and frequency of the internally generated sine
and cosine are controlled by the PFCS (Block Diagram). The
PFCS generates a 32-bit word that represents the current
phase of the sine and cosine waves being generated; the
Sine/ Cosine Argument. Stepping this phase angle from 0
through full scale (2

- 1) corresponds to the phase angle of

a sinusoid starting at 0

and advancing around the unit circle

counterclockwise. The PFCS automatically increments the
phase by a preprogrammed amount on every rising edge of
the external clock. The value of the phase step (which is the
sum of the Center and Offset Frequency Registers) is:

The PFCS is divided into two sections: the Phase
Accumulator uses the data on C0-15 to compute the phase
angle that is the input to the Sine/Cosine Section
(Sine/Cosine Argument); the Time Accumulator supplies a
pulse to mark the passage of a preprogrammed period of
time.

The Phase Accumulator and Time Accumulator work on the
same principle: a 32-bit word is added to the contents of a
32-bit accumulator register every clock cycle; when the sum
causes the adder to overflow, the accumulation continues
with the 32 bits of the adder going into the accumulator

register. The overflow bit is used as an output to indicate the
timing of the accumulation overflows. In the Time
Accumulator, the overflow bit generates TICO, the Time
Accumulator carry out (which is the only output of the Time
Accumulator). In the Phase Accumulator, the overflow is
inverted to generate the Phase Accumulator Carry Out,
PACO.

The output of the Phase Accumulator goes to the Phase
Adder, which adds an offset to the top 16 bits of the phase.
This 32-bit number forms the argument of the sine and
cosine, which is passed to the Sine/Cosine Generator.

Both accumulators are loaded 16 bits at a time over the
C0-15 bus. Data on C0-15 is loaded into one of the three
input registers when CS and WR are low. The data in the
Most Significant Input Register and Least Significant Input
Register forms a 32-bit word that is the input to the Center
Frequency Register, Offset Frequency Register and Time
Accumulator. These registers are loaded by enabling the
proper register enable signal; for example, to load the
Center Frequency Register, the data is loaded into the LS
and MS Input Registers, and ENCFREG is set to zero; the
next rising edge of CLK will pass the registered version of
ENCFREG, R.ENCFREG, to the clock enable of the Center
Frequency Register; this register then gets loaded on the
following rising edge of CLK. The contents of the Input
Registers will be continuously loaded into the Center
Frequency Register as long as R.ENCFREG is low.

The Phase Register is loaded in a similar manner. Assuming
PMSEL is high, the contents of the Phase Input Register is
loaded into the Phase Register on every rising clock edge
that R.ENPHREG is low. If PMSEL is low, MOD0-1 supply
the two most significant bits into the Phase Register (MOD1
is the MSB) and the least significant 14 bits are loaded with
0. MOD0-1 are used to generate a Quad Phase Shift Keying
(QPSK) signal (Table 2).

The Phase Accumulator consists of registers and adders
that compute the value of the current phase at every clock. It
has three inputs: Center Frequency, which corresponds to
the carrier frequency of a signal; Offset Frequency, which is
the deviation from the Center Frequency; and Phase, which

Phase Step =

Signal Frequency

Clock Frequency

----------------------------------------------

TABLE 1. AD0-1 DECODING

AD1

AD0

FUNCTION

Load least significant bits
of frequency input.

Load most significant bits
of frequency input.

Load phase register.

Reserved.

No Operation.

HSP45116

is a 16-bit number that is added to the current phase for PSK
modulation schemes. These three values are used by the
Phase Accumulator and Phase Adder to form the phase of
the internally generated sine and cosine.

The sum of the values in Center and Offset Frequency
Registers corresponds to the desired phase increment
(modulo 2

) from one clock to the next. For example,

loading both registers with zero will cause the Phase
Accumulator to add zero to its current output; the output of
the PFCS will remain at its current value; i.e., the output of
the NCOM will be a DC signal. If a hexadecimal 00000001 is
loaded into the Center Frequency Control Register, the
output of the PFCS will increment by one after every clock.
This will step through every location in the Sine/Cosine
Generator, so that the output will be the lowest frequency
above DC that can be generated by the NCOM, i.e., the
clock frequency divided by 2

. If the input to the Center

Frequency Control Register is hex 80000000, the PFCS will
step through the Generator with half of the maximum step
size, so that frequency of the output waveform will be half of
the sample rate.

The operation of the Offset Frequency Control Register is
identical to that of the Center Frequency Control Register;
having two separate registers allows the user to generate an
FM signal by loading the carrier frequency in the Center
Frequency Control Register and updating the Offset
Frequency Control Register with the value of the frequency
offset - the difference between the carrier frequency and the
frequency of the output signal. A logic low on CLROFR
disables the output of the Offset Frequency Register without
clearing the contents of the register.

Initializing the Phase Accumulator Register is done by putting
a low on the LOAD line. This zeroes the feedback path to the
accumulator, so that the register is loaded with the current
value of the phase increment summer on the next clock.

The final phase value going to the Generator can be
adjusted using MODPI/2PI to force the range of the phase to
be 0

to 180

(modulo

) or 0

to 360

(modulo 2

). Modulo

is the mode used for modulation, demodulation, direct

digital synthesis, etc. Modulo

is used to calculate FFTs.

This is explained in greater detail in the Applications Section.

The Phase Register adds an offset to the output of the
Phase Accumulator. Since the Phase Register is only 16
bits, it is added to the top 16 bits of the Phase Accumulator.

The Time Accumulator consists of a register which is
incremented on every clock. The amount by which it
increments is loaded into the Input Registers and is latched
into the Time Accumulator Register on rising edges of CLK
while ENTIREG is low. The output of the Time Accumulator
is the accumulator carry out, TICO. TICO can be used as a
timer to enable the periodic sampling of the output of the
NCOM. The number programmed into this register equals
2

x CLK period/desired time interval. TICO is disabled and

its phase is initialized by zeroing the feedback path of the
accumulator with RBYTILD.

Sine/Cosine Section

The Sine/Cosine Section (Figure 1) converts the output of
the PFCS into the appropriate values for the sine and
cosine. It takes the most significant 20 bits of the PFCS
output and passes them through a look up table to form the
16-bit sine and cosine inputs to the CMAC.

The 20-bit word maps into 2

radians so that the angular

resolution is 2

. An address of zero corresponds to

0 radians and an address of hex FFFFF corresponds to
2

- (2

) radians. The outputs of the Generator Section

are 2's complement sine and cosine values. The sine and
cosine outputs range from hexadecimal 8001, which
represents negative full scale, to 7FFF, which represents
positive full scale. Note that the normal range for two's
complement numbers is 8000 to 7FFF; the output range of
the SIN/COS generator is scaled by one so that it is
symmetric about 0.

The sine and cosine values are computed to reduce the
amount of ROM needed. The magnitude of the error in the
computed value of the complex vector is less than -90.2dB.
The error in the sine or cosine alone is approximately 2dB
better.

If RBYTILD is low, the output of the PFCS goes directly to
the inputs of the CMAC. If the real and imaginary inputs of
the CMAC are programmed to hex 7FFF and 0 respectively,
then the output of the PFCS will appear on output bits 0
through 15 of the NCOM with the output multiplexers set to
bring out the most significant bits of the CMAC output
(OUTMUX = 00). The most significant 16 bits out of the

TABLE 2. MOD0-1 DECODE

MOD1

MOD0

PHASE SHIFT (DEGREES)

270

180

CLK

SINE/COSINE

GENERATOR

SIN/CO

REG

CLK

R.RBYTILD

MUX

COS

SIN

FIGURE 1. SINE/COSINE SECTION

HSP45116

PFCS appears on IOUT0-15 and the least significant bits
come out on ROUT0-15.

Complex Multiplier/Accumulator

The CMAC (Figure 2) performs two types of functions:
complex multiplication/accumulation for modulation and
demodulation of digital signals, and the operations
necessary to implement an FFT butterfly. Modulation and
demodulation are implemented using the complex multiplier
and its associated accumulator; the rest of the circuitry
in this section, i.e., the complex accumulator, input shifters
and growth detect logic are used along with the complex
multiplier/accumulator for FFTs. The complex multiplier
performs the complex vector multiplication on the output of
the Sine/Cosine Section and the vector represented by the
real and imaginary inputs RIN and IIN. The two vectors are
combined in the following manner:

ROUT = COS x RIN - SIN x IIN

IOUT = COS x IIN + SIN x RIN

RIN and IIN are latched into the input registers and passed
through the shift stages. Clocking of the input registers is
enabled with a low on ENI. The amount of shift on the
latched data is programmed with SH0-1 (Table 3). The
output of the shifters is sent to the CMAC and the auxiliary
accumulators.

The 33-bit real and imaginary outputs of the Complex
Multiplier are latched in the Multiplier Registers and then go
through the Accumulator Section of the CMAC. If the ACC
line is high, the feedback to the accumulators is enabled; a
low on ACC zeroes the feedback path, so that the next set of
real and imaginary data out of the complex multiplier is
stored in the CMAC Output Registers.

The data in the CMAC Output Registers goes to the
Multiplexer, the output of which is determined by the
OUTMUX0-1 lines (Table 4). BINFMT controls whether the
output of the Multiplexer is presented in two's complement or
unsigned format; BINFMT = 0 inverts ROUT19 and IOUT19
for unsigned output, while BINFMT = 1 selects two's
complement.

The Complex Accumulator duplicates the accumulator in the
CMAC. The input comes from the data shifters, and its 20-bit
complex output goes to the Multiplexer. ACC controls
whether the accumulator is enabled or not. OUTMUX0-1
determines whether the accumulator output appears on
ROUT and IOUT.

TABLE 3. INPUT SHIFT SELECTION

SH1

SH0

SELECTED BITS

RIN0-15, IMIN0-15

RIN1-16, IMIN1-16

RIN2-17, IMIN2-17

RIN3-18, IMIN3-18

TABLE 4. OUTPUT MULTIPLEXER SELECTION

OUT

MUX

OUT

MUX

RO16-19

RO0-15

IO16-19

IO0-15

Real CMAC
31-34

Real CMAC
15-30

Imag CMAC
31-34

Imag CMAC
15-30

Real CMAC
31-34

0, Real
CMAC 0-14

Imag CMAC
31-34

0, Imag
CMAC 0-14

Real ACC
16-19

Real ACC
0-15

Imag ACC
16-19

Imag ACC
0-15

Reserved

HSP45116

The Growth Detect circuitry outputs a two bit value that
signifies the amount of growth on the data in the CMAC and
Complex Accumulator. Its output, DET0-1, is encoded as
shown in Table 5. If PEAK is low, the highest value of
DET0-1 is latched in the Growth Detect Output Register.

The relative weighting of the bits at the inputs and outputs of
the CMAC is shown in Figure 3. Note that the binary point of
the sine, cosine, RIN and IIN is to the right of the most
significant bit, while the binary point of RO and IO is to the
right of the fifth most significant bit. These CMAC external
input and output busses are aligned with each other to
facilitate cascading NCOMs for FFT applications.

FIGURE 3. BIT WEIGHTING

TABLE 5. GROWTH ENCODING

DET 1

DET 0

NUMBER OF BITS

OF GROWTH ABOVE 2

SIN/COS INPUT

-2

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

-11

-12

-13

-14

-15

Radix Point

COMPLEX MULTIPLIER/ACCUMULATOR INPUT (RIN, IIN)

SH = 00

-2

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

-11

-12

-13

-14

-15

Radix Point

COMPLEX MULTIPLIER/ACCUMULATOR OUTPUT (RO, IO)

OUTMUX = 00

-2

. 2

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

-11

-12

-13

-14

-15

Radix Point

COMPLEX MULTIPLIER/ACCUMULATOR OUTPUT (RO, IO)

OUTMUX = 01

-2

-16

-17

-18

-19

-20

-21

-22

-23

-24

-25

-26

-27

-28

-29

-30

COMPLEX ACCUMULATOR OUTPUT (RO, IO)

OUTMUX = 10

-2

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

-11

-12

-13

-14

-15

Radix Point

HSP45116

Applications

The NCOM can be used for Amplitude, Phase and Frequency
modulation, as well as in variations and combinations of these
techniques, such as QAM. It is most effective in applications
requiring multiplication of a rotating complex sinusoid by an
external vector. These include AM and QAM modulators and
digital receivers. The NCOM implements AM and QAM
modulation on a single chip, and is a element in demodulation,
where it performs complex down conversion. It can be
combined with the Intersil HSP43220 Decimating Digital Filter
to form the front end of a digital receiver.

Modulation/Demodulation

Figure 4 shows a block diagram of an AM modulator. In this
example, the phase increment for the carrier frequency is
loaded into the center frequency register, and the modulating
input is clocked into the real input of the CMAC, with the
imaginary input set to 0. The modulated output is obtained at
the real output of the CMAC. With a sixteen bit, two's
complement signal input, the output will be a 16-bit real
number, on ROUT0-15 (with OUTMUX = 00).

By replacing the real input with a complex vector, a similar
setup can generate QAM signals (Figure 5). In this case, the
carrier frequency is loaded into the center frequency register as
before, but the modulating vector now carries both amplitude
and phase information. Since the input vector and the internally
generated sine and cosine waves are both 16 bits, the number
of states is only limited by the characteristics of the
transmission medium and by the analog electronics in the
transmitter and receiver.

The phase and amplitude resolution for the Sine/Cosine section
(16-bit output), delivers a spectral purity of greater than 90dBc.
This means that the unwanted spectral components due to
phase uncertainty (phase noise) will be greater than 90dB
below the desired output (dBc, decibels below the carrier). With
a 32-bit phase accumulator in the Phase/Frequency Control
Section, the frequency tuning resolution equals the clock
frequency divided by 2

. For example, a 25MHz clock gives a

tuning resolution of 0.006Hz.

The NCOM also works with the HSP43220 Decimating
Digital Filter to implement down conversion and low pass
filtering in a digital receiver (Figure 6). The NCOM performs
complex down conversion on the wideband input signal by
multiplying the input vector and the internally generated
complex sinusoid. The resulting signal has components at
twice the center frequency and at DC. Two HSP43220s, one
each on the real and imaginary outputs of the HSP45116,
perform low pass filtering and decimation on the down
converted data, resulting in a complex baseband signal.

FIGURE 4. AMPLITUDE MODULATION

CLK

NCOM

MODULATED OUTPUT

PFCS

CENT

EQUENCY

SIN

I
N

/
C

INE

NERA

CMAC

RIN

SIGNAL INPUT

D/A

FIGURE 5. QUADRATURE AMPLITUDE MODULATION (QAM)

CLK

NCOM

PFCS

CENT

EQUENCY

I
NE

/COS

INE

GENERA

CMAC

D/A

RIN

IMIN

FIGURE 6. CHANNELIZED RECEIVER CHIP SET

HSP43220

DDF

HSP45116

NCOM

COS (wt)

SIN (wt)

SAMPLED

INPUT

DATA

10MHz

DDF

OUTPUT

NCOM

OUTPUT

INPUT

20MHz

HSP45116

Absolute Maximum Ratings

Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage Applied . . . . . GND -0.5V to V

+0.5V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Operating Conditions

Operating Voltage Range. . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V
Operating Temperature Range . . . . . . . . . . . . . . . . . . . 0

C to 70

Thermal Resistance (Typical, Note 1)

(

C/W)

(

C/W)

MQFP Package . . . . . . . . . . . . . . . . . .

22.0

N/A

PGA Package. . . . . . . . . . . . . . . . . . . .

23.1

Maximum Junction Temperature

MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

PGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Maximum Storage Temperature Range . . . . . . . . . . -65

C to 150

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300

(MQFP - Lead Tips Only)

Die Characteristics

Component Count . . . . . . . . . . . . . . . . . . . . . . . 103,000 Transistors

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

MAX

UNITS

Logical One Input Voltage

= 5.25V

2.0

Logical Zero Input Voltage

= 4.75V

0.8

High Level Clock Input

IHC

= 5.25V

3.0

Low Level Clock Input

ILC

= 4.75V

0.8

Output HIGH Voltage

= -400mA, V

= 4.75V

2.6

Output LOW Voltage

= 2.0mA, V

= 4.75V

0.4

Input Leakage Current

= V

or GND, V

= 5.25V

-10

I/O Leakage Current

OUT

= V

or GND, V

= 5.25V

-10

Standby Power Supply Current

CCSB

= V

or GND V

= 5.25V, Note 4

500

Operating Power Supply Current

CCOP

f = 15MHz, V

= V

or GND, V

= 5.25V,

Notes 2 and 4

182

Capacitance

= 25

C, Note 3

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

MAX

UNITS

Input Capacitance

FREQ = 1MHz, V

= Open, All measurements

are referenced to device ground

Output Capacitance

NOTES:

2. Power supply current is proportional to operating frequency. Typical rating for I

CCOP

is 10mA/MHz.

3. Not tested, but characterized at initial design and at major process/design changes.

4. Output load per test load circuit with switch open and C

= 40pF.

HSP45116

AC Electrical Specifications

= 5.0V

5%, T

= 0

C to 70

C (Note 5)

PARAMETER

SYMBOL

NOTES

-15 (15MHz)

-25 (25.6MHz)

-33 (33MHz)

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

CLK Period

CLK High

CLK Low

WR Low

WR High

Setup Time; AD0-1, CS to WR Going High

AWS

Hold Time; AD0, AD1, CS from WR Going High

AWH

Setup Time C0-15 from WR Going High

CWS

Hold Time C0-15 from WR Going High

CWH

Setup time WR High to CLK High

Setup Time MOD0-1 to CLK Going High

MCS

Hold Time MOD0-1 from CLK Going High

MCH

Setup Time PACI to CLK Going High

PCS

Hold Time PACI from CLK Going High

PCH

Setup ENPHREG, ENCFREG, ENOFREG,
ENPHAC, ENTIREG, CLROFR, PMSEL, LOAD, ENI,
ACC, BINFMT, PEAK, MODPI/2PI, SH0-1, RBYTILD
from CLK Going High

ECS

Hold Time ENPHREG, ENCFREG, ENOFREG,
ENPHAC, ENTIREG, CLROFR, PMSEL, LOAD, ENI,
ACC, BINFMT, PEAK, MODPI/2PI, SH0-1, RBYTILD
from CLK Going High

ECH

Setup Time RIN0-18, IMIN0-18 to CLK
Going High

Hold Time RIN0-18, IMIN0-18 from CLK
Going High

CLK to Output Delay RO0-19, IO0-19

CLK to Output Delay DET0-1

DEO

CLK to Output Delay PACO

CLK to Output Delay TICO

Output Enable Time OER, OEI, OEREXT, OEIEXT

OUTMUX0-1 to Output Delay

Output Disable Time

Output Rise, Fall Time

NOTES:

5. AC testing is performed as follows: Input levels (CLK Input) 4.0V and 0V; input levels (all other inputs) 0V and 3.0V; timing reference levels (CLK)

2.0V; all others 1.5V. Output load per test load circuit with switch closed and C

= 40pF. Output transition is measured at V

1.5V and V

1.5V.

6. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design

changes.

7. Applicable only when outputs are being monitored and ENCFREG, ENPHREG, or ENTIREG is active.

HSP45116

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FIGURE 8. CONTROL BUS TIMING

FIGURE 9. OUTPUT ENABLE, DISABLE TIMING

FIGURE 10. MULTIPLEXER TIMING

FIGURE 11. OUTPUT RISE AND FALL TIMES

Waveforms

(Continued)

AWH

AWS

AWH

AWS

CWH

CWS

CLK

C0-15

AD0-1

HIGH

IMPEDANCE

1.5V

1.7V
1.3V

HIGH

IMPEDANCE

1.5V

RO0-19

IO0-19

OER

OEREXT

OEIEXT

OEI

OUTMUX0-1

RO0-19

IO0-19

2.0V

0.8V

HSP45116

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HSP45116-15