1
FN9009.4
ISL6520
Single Synchronous Buck Pulse-Width
Modulation (PWM) Controller
The ISL6520 makes simple work out of implementing a
complete control and protection scheme for a DC/DC
stepdown converter. Designed to drive N-channel MOSFETs
in a synchronous buck topology, the ISL6520 integrates the
control, output adjustment, monitoring and protection
functions into a single 8-pin package.
The ISL6520 provides simple, single feedback loop, voltage-
mode control with fast transient response. The output
voltage can be precisely regulated to as low as 0.8V, with a
maximum tolerance of
1.5% over temperature and line
voltage variations. A fixed frequency oscillator reduces
design complexity, while balancing typical application cost
and efficiency.
The error amplifier features a 15MHz gain-bandwidth
product and 8V/
s slew rate which enables high converter
bandwidth for fast transient performance. The resulting
PWM duty cycles range from 0% to 100%.
Protection from over-current conditions is provided by
monitoring the r
DS(ON)
of the upper MOSFET to inhibit PWM
operation appropriately. This approach simplifies the
implementation and improves efficiency by eliminating the
need for a current sense resistor.
Features
Operates from +5V Input
0.8V to V
IN
Output Range
- 0.8V Internal Reference
- 1.5% Over Line Voltage and Temperature
Drives N-Channel MOSFETs
Simple Single-Loop Control Design
- Voltage-Mode PWM Control
Fast Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Cycle
Lossless, Programmable Over-Current Protection
- Uses Upper MOSFET's r
DS(on)
Small Converter Size
- 300kHz Fixed Frequency Oscillator
- Internal Soft Start
- 8 Ld SOIC or 16Ld 4x4mm QFN
QFN Package:
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
Power Supplies for Microprocessors
- PCs
- Embedded Controllers
Subsystem Power Supplies
- PCI/AGP/GTL+ Buses
- ACPI Power Control
Cable Modems, Set Top Boxes, and DSL Modems
DSP and Core Communications Processor Supplies
Memory Supplies
Personal Computer Peripherals
Industrial Power Supplies
5V-Input DC/DC Regulators
Low-Voltage Distributed Power Supplies
Ordering Information
PART
NUMBER
PART
MARKING
TEMP.
RANGE (C)
PACKAGE
PKG.
DWG. #
ISL6520CB
6520CB
0 to 70
8 Ld SOIC
M8.15
ISL6520CBZ
(Note)
6520CBZ
0 to 70
8 Ld SOIC (Pb-free) M8.15
ISL6520IB
6520IB
-40 to 85
8 Ld SOIC
M8.15
ISL6520IBZ
(Note)
6520IBZ
-40 to 85
8 Ld SOIC (Pb-free) M8.15
ISL6520CR ISL6520CR
0 to 70
16 Ld 4x4mm QFN L16.4x4
ISL6520IR
ISL6520IR
-40 to 85
16 Ld 4x4mm QFN L16.4x4
ISL6520EVAL1
Evaluation Board
* Add "-T" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Data Sheet
October 4, 2005
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
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Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2
FN9009.4
October 4, 2005
Block Diagram
Typical Application
Pinouts
SOIC
TOP VIEW
QFN
TOP VIEW
5
6
8
7
4
3
2
1
UGATE
GND
PHASE
FB
VCC
COMP/SD
BOOT
LGATE
12
11
10
9
1
2
3
4
16 15 14 13
5
6
7
8
NC
COMP/OCSET
NC
FB
GND
BOOT
UGATE
GND
NC
NC
NC
PHASE
NC
LGA
T
E
NC
VC
C
NC
+
-
+
-
+
-
OSCILLATOR
I
NHIBIT
PWM
COMPARATOR
ERROR
AMP
VCC
PWM
GND
FB
COMP/OCSET
0.8V
OC
COMPARATOR
GATE
CONTROL
LOGIC
BOOT
UGATE
PHASE
20
A
FIXED 300kHz
+
-
LGATE
VCC
SOFTSTART
POR AND
SAMPLE
AND
HOLD
V
CC
+V
O
FB
COMP/OCSET
UGATE
PHASE
BOOT
VCC
GND
LGATE
5
7
6
3
2
1
8
4
ISL6520
R
S
R
OFFSET
C
I
C
F
R
F
R
OCSET
L
OUT
D
BOOT
C
BOOT
C
BULK
C
DCPL
C
HF
C
OUT
ISL6520
3
FN9009.4
October 4, 2005
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V
Absolute Boot Voltage, V
BOOT
. . . . . . . . . . . . . . . . . . . . . . . +15.0V
Upper Driver Supply Voltage, V
BOOT
- V
PHASE
. . . . . . . . . . . +6.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Recommended Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V 10%
Ambient Temperature Range - ISL6520C . . . . . . . . . . . 0
o
C to 70
o
C
Ambient Temperature Range - ISL6520I . . . . . . . . . . -40
o
C to 85
o
C
Junction Temperature Range. . . . . . . . . . . . . . . . . . -40
o
C to 125
o
C
Thermal Resistance
JA
(
o
C/W)
JC
(
o
C/W)
SOIC Package (Note 1) . . . . . . . . . . . . . .
95 . . N/A
QFN Package (Note 2, 3). . . . . . . . . . . . . .
45 . . 7
Maximum Junction Temperature
(Plastic Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature
(Soldering 10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See
Tech Brief TB379.
3. For
JC
, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VCC SUPPLY CURRENT
Nominal Supply
I
VCC
UGATE and LGATE Open
2.6
3.2
3.8
mA
POWER-ON RESET
Rising VCC POR Threshold
POR
4.19
4.30
4.5
V
VCC POR Threshold Hysteresis
-
0.25
-
V
OSCILLATOR
Frequency
f
OSC
ISL6520C, V
CC
= 5V
250
300
340
kHz
ISL6520I, V
CC
= 5V
230
300
340
kHz
Ramp Amplitude
V
OSC
-
1.5
-
V
P-P
REFERENCE
Reference Voltage Tolerance
ISL6520C
-1.5
-
+1.5
%
ISL6520I
-2.5
+2.5
%
Nominal Reference Voltage
V
REF
-
0.800
-
V
ERROR AMPLIFIER
DC Gain
Guaranteed By Design
-
88
-
dB
Gain-Bandwidth Product
GBWP
-
15
-
MHz
Slew Rate
SR
-
8
-
V/
s
GATE DRIVERS
Upper Gate Source Current
I
UGATE-SRC
-
-1
-
A
Upper Gate Sink Current
I
UGATE-SNK
-
1
-
A
Lower Gate Source Current
I
LGATE-SRC
-
-1
-
A
Lower Gate Sink Current
I
LGATE-SNK
-
2
-
A
PROTECTION / DISABLE
OCSET Current Source
I
OCSET
ISL6520C
17
20
22
A
ISL6520I
14
20
24
A
Disable Threshold
V
DISABLE
-
0.8
-
V
ISL6520
4
FN9009.4
October 4, 2005
Functional Pin Description
VCC
This is the main bias supply for the ISL6520, as well as the
lower MOSFET's gate. Connect a well-decoupled 5V supply
to this pin.
FB
This pin is the inverting input of the internal error amplifier. Use
this pin, in combination with the COMP/OCSET pin, to
compensate the voltage-control feedback loop of the converter.
GND
This pin represents the signal and power ground for the IC.
Tie this pin to the ground island/plane through the lowest
impedance connection available.
PHASE
Connect this pin to the upper MOSFET source. This pin is
used to monitor the voltage drop across the upper MOSFET
for over-current protection. This pin is also monitored by the
continuously adaptive shoot-through protection circuitry to
determine when the upper MOSFET has turned off.
UGATE
Connect this pin to the upper MOSFET's gate. This pin
provides the PWM-controlled gate drive for the upper
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the upper
MOSFET has turned off. Do not insert any circuitry between
this pin and the gate of the upper MOSFET, as it may
interfere with the internal adaptive shoot-through protection
circuitry and render it ineffective.
BOOT
This pin provides ground referenced bias voltage to the
upper MOSFET driver. A bootstrap circuit is used to create a
voltage suitable to drive a logic-level N-channel MOSFET.
COMP/OCSET
This is a multiplexed pin. During a short period of time following
power-on reset (POR), this pin is used to determine the over-
current threshold of the converter. Connect a resistor (R
OCSET
)
from this pin to the drain of the upper MOSFET (V
CC
).
R
OCSET
, an internal 20
A current source (I
OCSET
), and the
upper MOSFET on-resistance (r
DS(ON)
) set the converter over-
current (OC) trip point according to the following equation:
Internal circuitry of the ISL6520 will not recognize a voltage
drop across R
OCSET
larger than 0.5V. Any voltage drop
across R
OCSET
that is greater than 0.5V will set the
overcurrent trip point to:
An over-current trip cycles the soft-start function.
During soft-start, and all the time during normal converter
operation, this pin represents the output of the error amplifier.
Use this pin, in combination with the FB pin, to compensate the
voltage-control feedback loop of the converter.
Pulling OCSET to a level below 0.8V will disable the
controller. Disabling the ISL6520 causes the oscillator to
stop, the LGATE and UGATE outputs to be held low, and the
softstart circuitry to re-arm.
LGATE
Connect this pin to the lower MOSFET's gate. This pin provides
the PWM-controlled gate drive for the lower MOSFET. This pin
is also monitored by the adaptive shoot-through protection
circuitry to determine when the lower MOSFET has turned off.
Do not insert any circuitry between this pin and the gate of the
lower MOSFET, as it may interfere with the internal adaptive
shoot-through protection circuitry and render it ineffective.
Functional Description
Initialization
The ISL6520 automatically initializes upon receipt of power.
The Power-On Reset (POR) function continually monitors the
bias voltage at the VCC pin. The POR function initiates the
Over-Current Protection (OCP) sampling and hold operation
after the supply voltage exceeds its POR threshold. Upon
completion of the OCP sampling and hold operation, the POR
function initiates the Soft Start operation.
Over Current Protection
The over-current function protects the converter from a
shorted output by using the upper MOSFET's on-resistance,
r
DS(ON)
, to monitor the current. This method enhances the
converter's efficiency and reduces cost by eliminating a
current sensing resistor.
The over-current function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor
(R
OCSET
) programs the over-current trip level (see Typical
Application diagram).
Immediately following POR, the ISL6520 initiates the Over-
Current Protection sampling and hold operation. First, the
internal error amplifier is disabled. This allows an internal
20
A current sink to develop a voltage across R
OCSET
. The
ISL6520 then samples this voltage at the COMP pin. This
sampled voltage, which is referenced to the VCC pin, is held
internally as the Over-Current Set Point.
When the voltage across the upper MOSFET, which is also
referenced to the VCC pin, exceeds the Over-Current Set
Point, the over-current function initiates a soft-start sequence.
Figure 1 shows the inductor current after a fault is introduced
while running at 15A. The continuous fault causes the
ISL6520 to go into a hiccup mode with a typical period of
25ms. The inductor current increases to 18A during the Soft
I
PEAK
I
OCSET
xR
OCSET
r
DS ON
(
)
-------------------------------------------------
=
I
PEAK
0.5V
r
DS ON
(
)
----------------------
=
ISL6520
5
FN9009.4
October 4, 2005
Start interval and causes an over-current trip. The converter
dissipates very little power with this method. The measured
input power for the conditions of Figure 1 is only 1.5W.
The over-current function will trip at a peak inductor current
(I
PEAK)
determined by:
where I
OCSET
is the internal OCSET current source (20
A
typical). The OC trip point varies mainly due to the
MOSFET's r
DS(ON)
variations. To avoid over-current tripping
in the normal operating load range, find the R
OCSET
resistor
from the equation above with:
1. The maximum r
DS(ON)
at the highest junction
temperature.
2. The minimum I
OCSET
from the specification table.
3. Determine I
PEAK
for
,
where
I is the output inductor ripple current.
For an equation for the ripple current see the section under
component guidelines titled `Output Inductor Selection'.
Soft Start
The POR function initiates the soft start sequence after the
overcurrent set point has been sampled. Soft start clamps the
error amplifier output (COMP pin) and reference input (non-
inverting terminal of the error amp) to the internally generated
Soft Start voltage. Figure 2 shows a typical start up interval
where the COMP/OCSET pin has been released from a
grounded (system shutdown) state. Initially, the COMP/OCSET
is used to sample the oversurrent setpoint by disabling the error
amplifier and drawing 20
A through R
OCSET
. Once the over-
current level has been sampled, the soft start function is
initiated. The clamp on the error amplifier (COMP/OCSET pin)
initially controls the converter's output voltage during soft start.
The oscillator's triangular waveform is compared to the ramping
error amplifier voltage. This generates PHASE pulses of
increasing width that charge the output capacitor(s). When the
internally generated Soft Start voltage exceeds the feedback
(FB pin) voltage, the output voltage is in regulation. This
method provides a rapid and controlled output voltage rise. The
entire startup sequence typically take about 11ms.
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible, using ground
plane construction or single point grounding.
Figure 3 shows the critical power components of the converter.
To minimize the voltage overshoot, the interconnecting wires
indicated by heavy lines should be part of a ground or power
plane in a printed circuit board. The components shown in
Figure 3 should be located as close together as possible.
FIGURE 1. OVERCURRENT OPERATION
TIME (5ms/DIV.)
OUTPUT INDUCTOR
5A/DIV.
CURRENT
I
PEAK
I
OCSET
x R
OCSET
r
DS ON
(
)
-----------------------------------------------------
=
I
PEAK
I
OUT MAX
(
)
I
( )
2
----------
+
>
FIGURE 2. START UP SEQUENCE
V
OUT
500mV/DIV.
COMP/OCSET
1V/DIV.
TIME (2ms/DIV.)
L
O
C
O
LGATE
UGATE
PHASE
Q
1
Q
2
V
IN
V
OUT
RETURN
ISL6520
C
IN
LO
AD
FIGURE 3. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
ISL6520
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