ISL6529, ISL6529A

Dual RegulatorSynchronous Rectified

Buck PWM and Linear Power Controllers

The ISL6529, ISL6529A provide the power control and
protection for two output voltages in high-performance
graphics cards and other embedded processor applications.
The dual-output controllers drive two N-Channel MOSFETs
in a synchronous rectified buck converter topology and one
N-Channel MOSFET in a linear configuration. The ISL6529,
ISL6529A provide both a regulated high current, low voltage
supply and an independent, lower current supply integrated
in a 14-lead SOIC package. The controllers are ideal for
graphic card applications where regulation of both the
graphics processing unit (GPU) and memory supplies is
required.

The synchronous rectified buck converters incorporate
simple, single feedback loop, voltage-mode control with fast
transient response. Both the switching regulator and linear
regulator provide a maximum static regulation tolerance of

2% over line, load, and temperature ranges. Each output is

user-adjustable by means of external resistors.

An integrated soft-start feature brings both supplies into
regulation in a controlled manner. Each output is monitored
via the FB pins for undervoltage events. If either output
drops below 51.5% of the nominal output level, both
converters are shut down.

Features

· Provides two regulated voltages

- One synchronous rectified buck PWM controller
- One linear controller

· Both controllers drive low cost N-Channel MOSFETs
· 12V direct drive saves external components
· Small converter size

- 600kHz constant frequency operation
- Small external component count

· Excellent output voltage regulation

- Both outputs: ±1% over temperature - ISL6529AC
- Both outputs: ±2% over temperature - ISL6529C

· 5V down conversion
· PWM and linear output voltage range: down to 0.8V
· Simple single-loop voltage-mode PWM control design
· Fast PWM converter transient response

- High-bandwidth error amplifier
- Full 0-100% duty ratio

· Linear controller drives N-Channel MOSFET pass transistor
· Fully-adjustable outputs
· Undervoltage fault monitoring on both outputs

· QFN Package:

- Compliant to JEDEC PUB95 MO-220

QFN - Quad Flat No Leads - Package Outline

- Near Chip Scale Package footprint, which improves

PCB efficiency and has a thinner profile

Pb-Free Available (RoHS Compliant)

Applications

· GraphicsGPU and memory supplies
· ASIC power supplies
· Embedded processor and I/O supplies
· DSP supplies

Related Literature

· Technical Brief TB363 Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices
(SMDs)

Ordering Information

PART NUMBER*

TEMP.

RANGE (°C)

PACKAGE

PKG.

DWG. #

ISL6529ACB

0 to 70

14 Ld SOIC

M14.15

ISL6529ACBZ (Note)

0 to 70

14 Ld SOIC (Pb-free) M14.15

ISL6529ACR

0 to 70

16 Ld 5x5 QFN

L16.5x5B

ISL6529ACRZ (Note)

0 to 70

16 Ld 5x5 QFN
(Pb-free)

L16.5x5B

ISL6529CB

0 to 70

14 Ld SOIC

M14.15

ISL6529CBZ (Note)

0 to 70

14 Ld SOIC (Pb-free) M14.15

ISL6529CR

0 to 70

16 Ld 5x5 QFN

L16.5x5B

ISL6529CRZ (Note)

0 to 70

16 Ld 5x5 QFN
(Pb-free)

L16.5x5B

ISL6529EVAL1

Evaluation Board

*Add "-T" suffix for tape and reel.

NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both
SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Data Sheet

April 12, 2005

FN9070.5

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Intersil (and design) is a trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

FN9070.5

April 12, 2005

ISL6529, ISL6529A

Absolute Maximum Ratings

Thermal Information

UGATE, LGATE, DRIVE2,. . . . . . . . . . . . . . . GND - 0.3V to 12VCC
5VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +7V
12VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14V
FB, FB2, COMP, . . . . . . . . . . . . . . . . . GND - 0.3V to 5VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 4kV

Operating Conditions

Supply Voltage on 5VCC . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%
Supply Voltage on 12VCC . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%
Supply Voltage to drain of Upper MOSFETs . . . +3.3V to +5V ±10%
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . 0°C to 125°C

Thermal Resistance

(°C/W)

SOIC Package (Note 1) . . . . . . . . . . . .

QFN Package (Notes 2, 3). . . . . . . . . .

Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See

Tech Brief TB379.

For

, the "case temp" location is the center of the exposed metal pad on the package underside.

Electrical Specifications

Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams, and Typical Application Schematic

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

VCC SUPPLY CURRENT

Nominal Supply Current 12VCC

UGATE, LGATE and DRIVE2 Open

2.7

3.0

Nominal Supply Current 5VCC

UGATE, LGATE and DRIVE2 Open

3.5

4.5

POWER-ON RESET

Rising 5VCC Threshold

12VCC = 12V

4.25

4.4

4.5

Falling 5VCCThreshold

12VCC = 12V

3.75

3.82

4.0

Rising 12VCC Threshold

5VCC = 5V

9.6

10.3

10.8

Falling 12VCCThreshold

5VCC = 5V

9.3

9.6

10.2

OSCILLATOR AND SOFT-START

Free Running Frequency

OSC

550

600

650

kHz

Ramp Amplitude

OSC

1.5

P-P

Soft-Start Interval

3.1

3.45

3.75

REFERENCE VOLTAGE

Reference Voltage

REF

0.800

System Accuracy

ISL6529C

-2.0

+2.0

ISL6529AC

-1.0

+1.0

PWM CONTROLLER ERROR AMPLIFIER

DC Gain

= 10K, C

= 10pF

Gain-Bandwidth Product

GBWP

= 10K, C

= 10pF

MHz

Slew Rate

= 10K, C

= 10pF

FB Input Current

= 0.8V

150

COMP High Output Voltage

OUT

High

3.0

4.5

COMP Low Output Voltage

OUT

Low

0.5

1.0

COMP High Output, Source Current

OUT

High

-2.5

-6.8

FN9070.5

April 12, 2005

Functional Pin Descriptions

LGATE (Pin 1), (Pin 16 QFN)

Lower gate drive output. Connect to gate of the low-side
MOSFET.

PGND (Pin 2), (Pin 1 QFN)

This pin is the power ground return for the lower gate driver.

GND (Pin 3), (Pin 2 QFN)

Signal ground for the IC. All voltage levels are measured
with respect to this pin. Place via close to pin to minimize
impedance path to ground plane.

5VCC (Pin 4), (Pin 3 QFN)

Provide a well decoupled 5V bias supply for the IC to this
pin. The voltage at this pin is monitored for Power-On Reset
(POR) purposes.

DRIVE2 (Pin 5), (Pin 4 QFN)

Connect this pin to the gate terminal of an external
N-Channel MOSFET transistor. This pin provides the gate
voltage for the linear regulator pass transistor. It also
provides a means of compensating the error amplifier for
applications where the user needs to optimize the regulator
transient response.

COMP Low Output, Sink Current

OUT

Low

2.5

3.5

Undervoltage Level (V

REF

)

51.5

PWM CONTROLLER GATE DRIVERS

UGATE and LGATE Maximum Voltage

HGATE

12VCC = 12V

UGATE and LGATE Minimum Voltage

LGATE

12VCC = 12V

0.5

UGATE and LGATE Source Current

GATE

12VCC = 12V

-1

UGATE and LGATE Sink Current

GATE

12VCC = 12V

UGATE and LGATE OUTPUT IMPEDANCE

DS(on)

12VCC = 12V

3.1

4.3

LINEAR REGULATOR (DRIVE2)

DC Gain

= 10K, C

= 10pF

Gain-Bandwidth Product

GBWP

= 10K, C

= 10pF

MHz

Slew Rate

= 10K, C

= 10pF

/µ

FB2 Input Current

FB2

= 0.8V

150

Drive2 High Output Voltage

OUT

High

9.5

10.3

Drive2 Low Output Voltage

OUT

Low

0.1

1.0

Drive2 High Output Source Current

OUT

High

-0.7

-1.4

Drive2 Low Output Sink Current

OUT

Low

0.85

1.2

Over-Voltage Level (V

FB2

REF

)

Percent of Nominal

160

Under-Voltage Level (V

FB2

REF

)

Percent of Nominal

51.5

REGULATOR ISOLATION

Change in Linear Regulator Output Voltage
(Note 4)

Vout

Linear Output = 2.5V, 6A Load Change on PWM

<0.5

Change in PWM Regulator Output Voltage

(Note 4)

Vout

PWM Output = 1.5V, 1A Load Change on Linear

<0.5

NOTE:

4. Measured in the evaluation board.

Electrical Specifications

Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams, and Typical Application Schematic (Continued)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

5VCC

GND

DRIVE2

FB2

UGATE

COMP

LGATE

13
12

12VCC

PGND

NC = NO INTERNAL

CONNECTION

ISL6529, ISL6529A

FN9070.5

April 12, 2005

FB2 (Pin 6), (Pin 5 QFN)

Connect the output of the linear regulator to this pin
through a properly sized resistor divider. The voltage at this
pin is regulated to 0.8V. This pin is also monitored for
undervoltage events.

Pulling and holding FB2 above 1.28V shuts down both
regulators. Releasing FB2 initiates soft-start on both regulators.

NC (Pins 7, 8, 11, and 12), (Pins 6, 7, 8, 11, 13 and
15 QFN)

No internal connection.

FB (Pin 9), (Pin 9 QFN) and COMP (Pin 10), (Pin 10
QFN)

FB and COMP are the available external pins of the error
amplifier. The FB pin is the inverting input of the error amplifier
and the COMP pin is the error amplifier output. These pins are
used to compensate the voltage-mode control feedback loop of
the standard synchronous rectified buck converter.

12VCC(Pin 13), (Pin 12 QFN)

Provides bias voltage for the gate drivers.The voltage at this
pin is monitored for Power-On Reset (POR) purposes.

UGATE (Pin 14), (Pin 14 QFN)

Connect UGATE to the upper MOSFET gate. This pin
provides the gate drive for the MOSFET.

Description

Operation Overview

The ISL6529 monitors and precisely controls two output
voltage levels. Refer to the Block Diagram, Simplified Power
System Diagram, and Typical Application Schematic on pp.
23. The controller is intended for use in graphics cards or
embedded processor applications with 5V and 12V bias input
available. The IC integrates both a standard buck PWM
controller and a linear controller. The PWM controller is
designed to regulate the high current GPU voltage (V

OUT1

The PWM controller regulates the output voltage to a level
programmed by a resistor divider. The linear controller is
designed to regulate the lower current local memory voltage
(V

OUT2

) through an external N-Channel MOS pass transistor.

Initialization

The ISL6529 automatically initializes upon application of
input power. Special sequencing of the input supplies is not
necessary. The POR function continually monitors the input
bias supply voltage at the 5VCC and 12VCC pins. The POR
function initiates soft-start operation after these supply
voltages exceed their POR threshold voltages.

Soft-Start

The POR function initiates the digital soft-start sequence.
Both the linear regulator error amplifier and PWM error
amplifier reference inputs are forced to track a voltage level
proportional to the soft-start voltage. As the soft-start voltage
slews up, the PWM comparator regulates the output relative
to the tracked soft-start voltage, slowly charging the output
capacitor(s). Simultaneously, the linear output follows the
smooth ramp of the soft-start function into normal regulation.

Figure 1 shows the soft-start sequence of an ISL6529
evaluation board powered by an ATX supply. Note the
uniform linear output voltage rise of the two ISL6529 output
voltages. Once the voltage on 5VCC crosses the POR
thresholds, both outputs begin their soft-start sequence. The
triangle waveform from the PWM oscillator is compared to
the rising error amplifier output voltage. As the error amplifier
voltage increases, the pulse-width on the PWM increases to
reach its steady-state duty cycle. The error amplifier
reference of the linear controller also rises relative to the
soft-start reference.

Figure 2 shows the controlled stepped output voltage rise
and associated charging current of a 390

F polymer

capacitor. By providing many small steps of current that
effectively charge the output capacitor, the potentially large
peak current resulting from a sudden, uncontrolled voltage
rise is eliminated.

The clock for the DAC producing the 30mV steps is
approximately 18.5kHz, so there is a 18.5kHz ripple current
component that lasts for the approximate 2.8ms start-up
interval. A few clock cycles are used for initialization to
insure that soft-start begins near zero volts.

FIGURE 1. ATX SUPPLY POWERING AN ISL6529

EVALUATION BOARD

5VCC INPUT

3.3V INPUT

1.5V OUTPUT

2.4V OUTPUT

ISL6529, ISL6529A

FN9070.5

April 12, 2005

Undervoltage Protection

The FB and FB2 pins are monitored during converter
operation by two separate undervoltage (UV) comparators. If
the FB voltage drops below 51.5% of the reference voltage
(0.41V), a fault signal is generated. The internal fault logic
shuts down both regulators simultaneously when the fault
signal triggers a restart.

Figure 3 illustrates the protection feature responding to a UV
event on V

OUT1

. At time t0, VOUT1 has dropped below

51.5% of the nominal output voltage. Both outputs are quickly
shut down and the internal soft-start function begins
producing soft-start ramps. The delay interval, t0 to t3, seen
by the output is equivalent to three soft-start cycles. After a
short delay interval of 10.5ms, the fourth internal soft-start
cycle initiates a normal soft-start ramp of the output, at time t3.
Both outputs are brought back into regulation by time t4, as
long as the UV event has cleared.

Had the cause of the UV still been present after the delay
interval, the UV protection circuitry becomes active
approximately 875ms into the soft-start interval. A fault
signal could then be generated and the outputs once again
shut down. The resulting hiccup mode style of protection
would continue to repeat indefinitely.

Output Voltage Selection

The output voltage of the PWM converter can be programmed
to any level between V

(i.e. +3.3V) and the internal

reference, 0.8V . An external resistor divider is used to scale
the output voltage relative to the reference voltage and feed it
back to the inverting input of the error amplifier (see Figure 4).

CAPACITOR CURRENT

1.5V OUTPUT

FIGURE 2. TOP SCOPE TRACES ARE VOLTAGE RAMP AND

CAPACITOR CURRENT. LOWER TRACES ARE
TIME AND VOLTAGE EXPANSION OF UPPER
SCOPE TRACES.

FIGURE 3. UNDERVOLTAGE PROTECTION RESPONSE

TIME

OUT2

(2.5V)

(0.5V/DIV)

OUT1

(1.5V)

INTERNAL SOFT-START FUNCTION

OUT2

(2.5V)

DELAY INTERVAL

ISL6529, ISL6529A

FN9070.5

April 12, 2005

However, since the value of R1 affects the values of the rest
of the compensation components, it is advisable to keep its
value less than 5k

. Depending on the value chosen for R1,

R4 can be calculated based on the following equation:

If the output voltage desired is 0.8V, simply route VOUT1
back to the FB pin through R1, but do not populate R4.

The linear regulator output voltage is also set by means of
an external resistor divider as shown in Figure 5. The two
resistors used to set the output voltage should not exceed a
parallel equivalent value, referred to as R

, of 5k

. This

restriction is due to the manner of implementation of the soft-
start function. The following relationship must be met:

To ensure the parallel combination of the feedback resistors
meets this criteria, choose a target value for R

of less than

and then apply the following equations:

where V

OUT2

is the desired linear regulator output voltage

and V

REF

is the internal reference voltage, 0.8V. For an

output voltage of 0.8V, simply populate R5 with a value less
than 5k

and do not populate R6.

Converter Shutdown

Pulling and holding the FB2 pin above a typical threshold of
1.28V will shut down both regulators. Upon release of the
FB2 pin, the regulators enter into a soft-start cycle which
brings both outputs back into regulation.

PWM Controller Feedback Compensation

A simplified representation of the voltage-mode control loop
used for output regulation by the converter is shown in
Figure 6. The output voltage, V

OUT

, is fed back to the

negative input of the error amplifier which is regulated to the
reference voltage level, V

REF

. The error amplifier output,

E/A

, is compared with the triangle wave produced by the

oscillator, V

OSC

, to provide a pulse-width modulated (PWM)

signal from the PWM comparator. This signal is then used to
switch the MOSFET and produce a PWM waveform with an
amplitude of V

at the PHASE node. The square-wave

PHASE voltage is then smoothed by the output filter, L

OUT

and C

OUT

, to produce a DC voltage level.

The modulator transfer function is defined as V

OUT

E/A

The internal PWM comparator and driver circuits equate to a
DC gain block dominated by the supply voltage, V

, divided

by the peak-to-peak magnitude of the triangle wave,

OSC

The output filter components, L

OUT

and C

OUT

, shape the

overall modulator small-signal transfer function by
contributing a double pole break frequency at F

and a

zero at F

ESR

FIGURE 4. OUTPUT VOLTAGE SELECTION OF THE PWM

OUT1

+5V

+3.3V

OUT1

OUT

ISL6529

UGATE

12VCC

COMP

5VCC

+12V

LGATE

ISL6529A

R1 0.8V

OUT1

0.8V

--------------------------------------

(EQ. 1)

R5 R6

---------------------- 5k

(EQ. 2)

DRIVE2

FB2

OUT2

ISL6529

OUT2

+3.3V

FIGURE 5. OUTPUT VOLTAGE SELECTION OF THE LINEAR

OUT2

0.8

1 R5

--------

R12

For frequency compensation considerations

set R5 to 4.64k and adjust R6 for the required voltage.

ISL6529A

OUT2

REF

------------------- R

(EQ. 3)

R5 V

REF

OUT2

REF

----------------------------------------

(EQ. 4)

ISL6529, ISL6529A

FN9070.5

April 12, 2005

Modulator Break Frequency Equations

The compensation network consists of the error amplifier
and the impedance networks Z

and Z

. They provide the

link between the modulator transfer function and a
controllable closed loop transfer function of V

OUT

REF

. The

goal of component selection for the compensation network is
to provide a loop gain with high 0dB crossing frequency
(f

0dB

) and adequate phase margin. Phase margin is the

difference between the closed loop phase at f

0dB

and 180

degrees .

Compensation Break Frequency Equations

Follow this procedure for selecting compensation
components by locating the poles and zeros of the
compensation network:

1. Set the loop gain (R2/R1) to provide a converter

bandwidth of one quarter of the switching frequency.

2. Place the first

compensation zero, F

, below the output

filter double pole (~75% F

3. Position the second compensation zero, F

, at the

output filter double pole, F

4. Locate the first compensation pole, F

, at the output

filter ESR zero, F

ESR

5. Position the second compensation pole at half the

converter switching frequency, F

6. Check gain against error amplifier's open-loop gain.
7. Estimate phase margin; repeat if necessary.

FIGURE 6. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

OUT

REF

OUT

ESR

OSC

ERROR

AMP

PWM

DRIVER

(PARASITIC)

0.8V

COMP

OUT

ISL6529

COMP

DETAILED COMPENSATION COMPONENTS

PHASE

E/A

OSC

----------------------------------------

ESR

ESR C

-----------------------------------------

(EQ. 5)

(EQ. 6)

2 C1

-----------------------------------

R1 R3

(

)

-------------------------------------------------------

C1 C2

----------------------

-------------------------------------------------------

3 C3

-----------------------------------

(EQ. 10)

(EQ. 11)

(EQ. 8)

(EQ. 9)

Zeros:

Poles:

INTERNAL 0.8V

REFERENCE

ISS

= C

+ C

REGULATED OUTPUT

LOAD

1/gfs

ESR

GATE

SOURCE

DRAIN

SAMPLE

OUTPUT

SIMPLIFIED MODEL

OF THE MOSFET

R12

AMPLIFIER

ERROR

ISL6529

DRIVE2

C16

INPUT VOLTAGE

FIGURE 7. FIGURE A. SIMPLIFIED DIAGRAM OF THE LINEAR VOLTAGE REGULATOR

ISL6529, ISL6529A

FN9070.5

April 12, 2005

Figure

shows an asymptotic plot of the DC-DC converter's

gain vs. frequency. The actual modulator gain has a high
gain peak dependent on the quality factor (Q) of the output
filter, which is not shown in Figure

. Using the above

procedure should yield a compensation gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F

with the capabilities of the error amplifier.

The compensation gain uses external impedance networks
Z

and Z

to provide a stable, high bandwidth (BW)

overall loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.

Linear Regulator Compensation

The linear regulator in the ISL6529 is not internally
compensated and therefore allows the user to optimize
regulator performance with regard to transient load
response. Although the compensation network shown in the
application examples in this data sheet provide conservative
compensation for a variety of loads, performance can be
enhanced with attention to load requirements.

Low ESR capacitors can cause stability concerns in discrete
IC regulators. Even regulators that are internally
compensated can become unstable when these capacitors
are placed across their output. There have been suggestions
to add series resistance to these capacitors to stabilize the
regulator. This approach seems self defeating and throws
away a desirable quality.

Component Considerations

Many unsuspected poles and zeros develop with the
selection of external components and operating conditions
like output MOSFET transistors, output filter capacitors and
load current. These elements will be discussed beginning
with the influence of the MOSFET series output resistance,
the 1/gfs term shown in Figure 7. At low load currents and
low transconductance, the effective output resistance can be
as high as several kilohms. The low MOSFET gfs with
accompanying high series resistance and large values of
output capacitance form a low frequency pole that for many
cases becomes the dominate pole in the system and often
results in a stable no load system. As the load current is
increased, the MOSFET series output resistance is reduced
and moves the output pole into a higher frequency region,
adding phase shift that can result in a marginally stable or
unstable system.

Low output capacitor ESR can result in stability problems as
mentioned above. In contrast, high output capacitor ESR
can improve the system stability. The capacitor and its series
resistance function as a zero, often canceling other poles in
the loop. Figure 9 shows a system simulation with a 300

100m

high ESR output capacitor. A single 10pF capacitor

from input to output of the error amplifier stabilizes the
system for load currents through the 1mA to 3A range.

Contrast this with Figure 10 that shows a Bode plot of
simulations of this regulator operating with a 100

F, 5m

low ESR output capacitor. Note the phase approaching 180°
at high current. This is in contrast to the response previously
shown with the 300

F high ESR capacitor. The 300

output capacitor and its ESR provide phase lead to cancel or
offset the pole formed with the MOSFET output resistance
and 300

F capacitance. Also notice that system stability

varies widely with load current. A system can oscillate at no
load and be stable at full load, The converse is also possible.
Oscillation can also occur at load currents between the
current extremes.

FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

100

-20

-40

-60

10M

100K

10K

100

OPEN LOOP

ERROR AMP GAIN

ESR

COMPENSATION

(

FREQUENCY (Hz)

GAIN

MODULATOR

GAIN

LOOP GAIN

VIN

VOSC

------------------

log

R2
R1

---------

log

100

10K

100K

10M

FREQUENCY (Hz)

-50

-150

-100

-200

GAI

PHASE

DEGREES

1mA

55mA

1mA

BODE PLOT OF COMPENSATED REGULATOR AT 3 OUTPUT CURRENTS

OUTPUT CAPACITOR

300

F, 100m

FIGURE 9. LOOP RESPONSE WITH ONLY C16 = 10pF

COMPENSATION

ISL6529, ISL6529A

FN9070.5

April 12, 2005

The Compensation Network

To provide for system stability with a low ESR output
capacitor, where pole cancellation by the capacitor is outside
the frequencies of interest, a phase lead network must be
used to compensate for the phase lag resulting from
MOSFET output resistance and the output capacitor.

Figure 11 shows the type II compensation network
configuration and a simplified straight line representation of
the network response. By using the equations in Figure 11,

the values of R12 and C4 can be adjusted to the frequency
where phase lead begins. The second equation shows the
upper frequency where phase advance is complete. After
capacitor C4 becomes effectively an ac short, the mid band
gain is set by the R12/R5 ratio as shown on Figure 11.

Several simulations illustrate the compensation with the
more difficult 5m

, 100

F output capacitor. Figure 10

previously showed the Bode plots where the phase
response comes dangerously near the oscillatory 180° state
at unity gain. A type II network applied across the error
amplifier inverting input to the output can be configured to
perform this function.

Figure 12 shows the Bode plot of only the compensation
network with the system to illustrate the phase boost in the
system. Essentially the phase lead region must be moved to
advance the phase where it is close to an oscillatory state.
Increasing the value of C4 moves the response lower, aiding
the lagging phase at low frequencies and low load current.
This operation will reduce phase compensation at higher

-50

-150

-100

-200

100

10K

100K

10M

GAI

PHASE DEGRE

FREQUENCY (Hz)

BODE PLOT OF REGULATOR (N0 COMP) AT 3 OUTPUT CURRENTS

55mA

1mA

55mA

1mA

55mA

1mA

FIGURE 10. LOOP RESPONSE WITH ONLY 100µF, 5m

OUTPUT CAPACITOR

100

1,000

10,000

100,000

1,000,000

10,000,000

-90

-45

E (DEGRE

ES)

GAI

(
d

)

-135

10 100

10K

100K

10M

FREQUENCY (Hz)

R12 C4

-----------------------------------

R12

-----------

log

R12

C16 C4

-------------------------

----------------------------------------------------------

INTERNAL 0.8V

REFERENCE

REGULATED

R12

C16

TO MOSFET

DRIVE 2

ISL6529

OUTPUT

FIGURE 11. SCHEMATIC AND BODE PLOT OF

COMPENSATION NETWORK

-50

-150

-100

-200

GAI

HASE DEGRE

100

10K

100K

10M

FREQUENCY (Hz)

BODE PLOT OF REGULATOR (COMP ONLY) AT 3 OUTPUT CURRENTS

1mA

54mA

1mA

COMPENSATION:

C16 = 10pF
C4 = 470pF
R16 = 200K

FIGURE 12. LOOP RESPONSE WITH COMPENSATION

NETWORK ONLY

135°

-50

-150

-100

-200

GAI

PHAS

E DE

GREE

100

10K

100K

10M

FREQUENCY (Hz)

BODE PLOT OF COMPENSATED REGULATOR AT 3 OUTPUT CURRENTS

54mA

1mA

54mA

1mA

COMPENSATION:

C16 = 10pF
C4 = 470pF
R16 = 200K

FIGURE 13. INVERTING INPUT TO OUTPUT GAIN AND

PHASE WITH COMPENSATION AND 100µF, 5m

OUTPUT CAPACITOR

ISL6529, ISL6529A

FN9070.5

April 12, 2005

frequencies and high load current. Figure 13 shows the
results of the complete system with output capacitor and
compensation network for 45° of phase margin.

Because of the large variety of capacitors, varying ESRs and
PC board layouts, Table 1, based upon system simulations
is provided as a starting point guide to aid in the selection of
compensation networks for output capacitors values of 1

F, 100

F and 1000

F with ESR values of 5m

, 30m

and 100m

for each capacitor value. The frequencies

associated with the compensation elements are also shown
to aid in component selection.

Parallel capacitors of the same value and type can be
treated as a combination. For example three 100

F, 10m

capacitors may be treated as one 300

F, 3.3m

capacitor.

Mixed capacitors require more attention. For example the
compensation for a 1000

F, low ESR capacitor will suffice

for a shunting 10

F, low ESR capacitor.

TABLE 1. COMPENSATION NETWORKS FOR LINEAR REGULATOR

CAP
ESR

DETAIL

OUTPUT CAPACITOR

100

1000

Comp

Network

C16 = 10pF

R12 = 47K

C4 = 200pF

C16 = 10pF

R12 = 47K

C4 = 470pF

C16 = 10pF
R12 = 200K
C4 = 470pF

C16 = 10pF
R12 = 470K
C4 = 470pF

Low Fq Zero (C4 & R12)

17kHz

7.2kHz

1.7kHz

720Hz

High Fq

Pole (C16 & R12)

338kHz

80kHz

34kHz

MidbandGain R12/R5

20dB

33dB

40dB

OUTPUT CAP

& ESR Zero Fq

32MHz

3.2MHz

320kHz

32kHz

30m

Comp

Network

C16 = 10pF

R12 = 47K

C4 = 200pF

C16 = 10pF

R12 = 47K

C4 = 470pF

C16 = 10pF
R12 = 200K
C4 = 470pF

C16 = 10pF

Low Fq

Zero (C4 & R12)

17kHz

1.7kHz

High Fq

Pole (C16 & R12)

338kHz

80kHz

Midband Gain R12/R5

20dB

33dB

OUTPUT Cap

& ESR Zero Fq

5.3MHz

530kHz

53kHz

5.3kHz

100m

Comp

Network

C16 = 10pF

R12 = 47K

C4 = 200pF

C16 = 10pF

R12 = 47K

C4 = 470pF

C16 = 10pF

C16= 10pF

Low Fq

Zero (C4 & R12)

17kHz

High Fq

Pole (C16 & R12)

338kHz

Midband Gain R12/R5

20dB

OUTPUT Cap

& ESR Zero Fq

1.6MHz

160kHz

16kHz

1.6kHz

ISL6529, ISL6529A

FN9070.5

April 12, 2005

The final test for a system is transient load current
performance. Ringing or oscillation indicates that the
compensation network must be adjusted to assure stable
operation with component and environmental variations.
Figures 14 and 15 are scope shots that show the regulator
with only with a 1500

F, 100m

capacitor with high

frequency ringing with no compensation. A 27pF capacitor,
C16 was added in Figure 15. The output step is about
260mV for the 3A load current for an ESR in the order of
90m

. After the load current is removed, the output network

parasitics ring for about 5

Application Guidelines

Layout Considerations

Layout is very important in high frequency switching
converter design. With power devices switching efficiently at
600kHz, the resulting current transitions from one device to
another cause voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device over-voltage stress. Careful component
layout and printed circuit board design minimizes the voltage
spikes in the converters.

As an example, consider the turn-off transition of the PWM
MOSFET. Prior to turn-off, the MOSFET is carrying the full
load current. During turn-off, current stops flowing in the
MOSFET and is picked up by the lower MOSFET and
parasitic diode. Any parasitic inductance in the switched
current path generates a large voltage spike during the
switching interval. Careful component selection, tight layout
of the critical components, and short, wide traces minimizes
the magnitude of voltage spikes.

There are two sets of critical components in a DC-DC converter
using the ISL6529, ISL6529A. The switching components are
the most critical because they switch large amounts of energy,
and therefore tend to generate large amounts of noise. Next
are the small signal components which connect to sensitive
nodes or supply critical bypass current and signal coupling.

A multi-layer printed circuit board is recommended. Figure
16 shows the connections of the critical components in the
converter. Note that capacitors C

and C

OUT

could each

represent numerous physical capacitors. Dedicate one solid
layer, usually a middle layer of the PC board, for a ground
plane and make all critical component ground connections
through vias to this layer. Dedicate another solid layer as a
power plane and break this plane into smaller islands of
common voltage levels. Keep the metal runs from the
PHASE terminal to the output inductor short. The power
plane should support the input and output power nodes. Use
copper filled polygons on the top and bottom circuit layers for
the phase node. Use the remaining printed circuit layers for
small signal wiring. The wiring traces from the UGATE pin to
the MOSFET gate should be kept short and wide enough to
easily handle the 1A of drive current.

The switching components should be placed close to the
ISL6529, ISL6529A first. Minimize the length of the
connections between the input capacitors, C

, and the

power switches by placing them nearby. Position both the
ceramic and bulk input capacitors as close to the upper
MOSFET drain as possible. Position the output inductor and
output capacitors between the upper MOSFET and lower
diode and the load.

FIGURE 14. 3A TRANSIENT LOAD APPLIED TO THE

REGULATOR NO COMPENSATION

FIGURE 15. 3A TRANSIENT LOAD APPLIED TO THE

REGULATOR 27pF COMPENSATION

OUTPUT VOLTAGE

200mV/DIV

LOAD CURRENT, 1A/DIV

OUTPUT VOLTAGE

200mV/DIV

ISL6529, ISL6529A

FN9070.5

April 12, 2005

The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Position the bypass capacitors, C

, close to

the VCC pin with a via directly to the ground plane. Place the
PWM converter compensation components close to the FB
and COMP pins. The feedback resistors for both regulators
should also be located as close as possible to the relevant
FB pin with vias tied straight to the ground plane as required.

Component Selection Guidelines

Output Capacitor Selection

Output capacitors are required to filter the output and supply
the load transient current. The filtering requirements are a
function of switching frequency and output current ripple.
The load transient requirements are a function of the
transient load current slew rate (di/dt) and magnitude. These
requirements are generally met with a mix of capacitors and
careful layout.

PWM Regulator Output Capacitors

Modern digital ICs can produce high transient load slew
rates. High frequency capacitors initially supply the transient
current and slow the load rate-of-change seen by the bulk
capacitors. The bulk filter capacitor selection is generally
determined by the effective series resistance (ESR) and
voltage rating requirements rather than actual capacitance
requirements.

High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.

Specialized low-ESR capacitors intended for switching-
regulator applications are recommended for the bulk
capacitors. The bulk capacitor's ESR determines the output
ripple voltage and the initial voltage drop following a high
slew-rate transient edge. Aluminum electrolytic, tantalum,
and special polymer capacitor ESR values are related to the
case size with lower ESR available in larger case sizes.
However, the equivalent series inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient
loading. Unfortunately, ESL is not a specified parameter.
Work with your capacitor supplier and measure the
capacitor's impedance with frequency to select a suitable
component. In most cases, multiple electrolytic capacitors of
small case size perform better than a single large case
capacitor.

PWM Output Inductor Selection

The PWM converter requires an output inductor. The output
inductor is selected to meet the output voltage ripple
requirements and sets the converter response time to a load
transient. The inductor value determines the converter's
ripple current and the ripple voltage is also a function of the
ripple current. The ripple voltage and current are
approximated by the following equations:

Increasing the value of inductance reduces the output ripple
current and voltage ripple. However, increasing the
inductance value will slow the converter response time to a
load transient.

One of the parameters limiting the converter's response to a
load transient is the time required to slew the inductor
current. Given a sufficiently fast control loop design, the
ISL6529 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time

OUT1

+5 VCC

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

OUT

OUT1

+3.3 V

KEY

COMP

ISL6529

UGATE

DRIVE2

GND

5VCC

FIGURE 16. PRINTED CIRCUIT BOARD POWER PLANES

AND ISLANDS

OUT2

FB2

VIA CONNECTION TO GROUND PLANE

OUT2

LO
A

+3.3 V

PHASE

+12 VCC

PGND

12VCC

LGATE

OUT

--------------------------------

OUT

----------------

OUT

ESR

(EQ. 11)

(EQ. 12)

ISL6529, ISL6529A

FN9070.5

April 12, 2005

interval required to slew the inductor current from an initial
current value to the final current level. During this interval the
difference between the inductor current and the load current
must be supplied by the output capacitor(s). Minimizing the
response time can minimize the output capacitance
required.

The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:

where I

TRAN

is the transient load current step, t

RISE

is the

response time to the application of load, and t

FALL

is the

response time to the removal of load.

With a +3.3V input source, the worst case response time can
be either at the application or removal of load and dependent
upon the output voltage setting. Be sure to check both of
these equations at the minimum and maximum output levels
for the worst case response time.

Input Capacitor Selection

The important parameters for the bulk input capacitors are
the voltage rating and the RMS current rating. For reliable
operation, select bulk input capacitors with voltage and
current ratings above the maximum input voltage and largest
RMS current required by the circuit. The capacitor voltage
rating should be at least 1.25 times greater than the
maximum input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 of the summation of the DC load current.

Use a mix of input bypass capacitors to control the voltage
overshoot across the switching MOSFETs. Use ceramic
capacitance for the high frequency decoupling and bulk
capacitors to supply the RMS current. Small ceramic
capacitors can be placed very close to the upper MOSFET
to suppress the voltage induced in the parasitic circuit
impedances. Connect them directly to ground with a via
placed very close to the ceramic capacitor footprint.

For a through-hole design, several aluminum electrolytic
capacitors may be needed. For surface mount designs,
tantalum or special polymer capacitors can be used, but
caution must be exercised with regard to the capacitor surge
current rating. These capacitors must be capable of handling
the surge-current at power-up.

TRANSISTOR SELECTION/CONSIDERATIONS
The ISL6529, ISL6529A require three external transistors.
One N-Channel MOSFET is used as the upper switch in a
standard buck topology PWM converter. Another MOSFET
is used as the lower synchronous switch. The linear
controller drives the gate of an N-Channel MOS transistor
used as the series pass element. The chosen MOSFET
r

DS(ON)

determines the maximum drop out voltage of the

regulator. For all practical purposes, the MOSFET appears
as a variable resistor. All he MOSFET transistors should be
selected based upon r

DS(ON)

, gate supply requirements,

and thermal management considerations.

Upper MOSFET SWITCH Selection

In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss
components; conduction loss and switching loss. The
conduction losses account for a large portion of the power
dissipation of the upper MOSFET. Switching losses also
contribute to the overall MOSFET power loss.

where I

is the maximum load current, D is the duty cycle of

the converter (defined as V

), t

is the switching

interval, and F

is the PWM switching frequency.

The lower MOSFET has only conduction losses since it
switches with zero voltage across the device. Conduction
loss is:

These equations assume linear voltage-current transitions
and are approximations. The gate-charge losses are
dissipated by the ISL6529 and do not heat the MOSFET.
However, large gate-charge increases the switching interval,
t

, which increases the upper MOSFET switching losses.

Ensure that the MOSFET is within its maximum junction
temperature at high ambient temperature by calculating the
temperature rise according to package thermal-resistance
specifications. A separate heatsink may be necessary
depending upon MOSFET power, package type, ambient
temperature, air flow, and load current requirements.

The gate drive to the switching transistors ranges from
slightly below 12V to ground. Because of the large voltage
swing, logic-level transistors are not necessary in this
application.

RISE

TRAN

OUT

--------------------------------

FALL

TRAN

OUT

-------------------------------

(EQ. 13)

(EQ. 14)

ConductionUpper

DS on

(

)

Switching

1
2

---I

(EQ. 15)

(EQ. 16)

ConductionLower

DS on

(

)

1 D

(

)

(EQ. 17)

ISL6529, ISL6529A

FN9070.5

April 12, 2005

However, if logic-level transistors or transistors with low
V

GS(on)

are used, close attention to layout guidelines should

be exercised, as the low gate threshold could lead to some
shoot-through despite counteracting circuitry present aboard
the ISL6529.

N-Channel MOSFET Transistor Selection

The main criteria for selection of the linear regulator pass
transistor is package selection for efficient removal of heat.
Select a package and heatsink that maintains the junction
temperature below the rating with a maximum expected
ambient temperature.

The power dissipated in the linear regulator is:

where I

is the maximum output current and V

OUT

is the

nominal output voltage of the linear regulator.

References

Intersil documents are available on the web at
http://www.intersil.com.

[1] Technical Brief, Intersil Corporation, TB417,

http://www.intersil.com/data/tb/tb417.pdf

ISL6529 Converter Application Circuit

LINEAR

OUT

(

)

(EQ. 18)

FIGURE 17. POWER SUPPLY APPLICATION CIRCUIT FOR A GRAPHICS CONTROLLER

+3.3V

C12

1500

47nF

10.7k

5VCC

VOUT2

GND

(1A)

VOUT1

(6A)

DRIVE2

FB2

UGATE

COMP

ISL6529

4.64k

2.15k

C14

+5V

1000

470

4.7

470

C10

1.0k

1.2nF

MTD3055V

919AS-4R7M

Fairchild
TOKO

12VCC

PGND

LGATE

+12V

C15
1

TOKO

919AS-1R0N

6.8k

R12

470pF

47nF

Q1, Q2 IRF7313

2.5V

1.6V

R13

1.0k

ISL6529A

ISL6529, ISL6529A

FN9070.5

April 12, 2005

ISL6529, ISL6529A

Quad Flat No-Lead Plastic Package (QFN)

Micro Lead Frame Plastic Package (MLFP)

L16.5x5B

16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

(COMPLIANT TO JEDEC MO-220VHHB ISSUE C)

SYMBOL

MILLIMETERS

NOTES

MIN

NOMINAL

MAX

0.80

0.90

1.00

0.05

1.00

0.20 REF

0.28

0.33

0.40

5, 8

5.00 BSC

4.75 BSC

2.95

3.10

3.25

7, 8

5.00 BSC

4.75 BSC

2.95

3.10

3.25

7, 8

0.80 BSC

0.25

0.35

0.60

0.75

L1 -

0.15

0.60

Rev. 1 10/02

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land Pattern

Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P &

are present when

Anvil singulation method is used and not present for saw
singulation.

10. Depending on the method of lead termination at the edge of the

package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9070.5

April 12, 2005

ISL6529, ISL6529A

Small Outline Plastic Packages (SOIC)

NOTES:

1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of

Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension "D" does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.

4. Dimension "E" does not include interlead flash or protrusions. Interlead

flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. "L" is the length of terminal for soldering to a substrate.
7. "N" is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width "B", as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

INDEX

AREA

-B-

0.25(0.010)

C A

B S

-A-

-C-

SEATING PLANE

0.10(0.004)

h x 45

0.25(0.010)

M14.15

(JEDEC MS-012-AB ISSUE C)

14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE

SYMBOL

INCHES

MILLIMETERS

NOTES

MIN

MAX

MIN

MAX

0.0532

0.0688

1.35

1.75

0.0040

0.0098

0.10

0.25

0.013

0.020

0.33

0.51

0.0075

0.0098

0.19

0.25

0.3367

0.3444

8.55

8.75

0.1497

0.1574

3.80

4.00

0.050 BSC

1.27 BSC

0.2284

0.2440

5.80

6.20

0.0099

0.0196

0.25

0.50

0.016

0.050

0.40

1.27

Rev. 0 12/93

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ISL6529CR

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ISL6529CR