8-136
File Number
4314.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
LittleFETTM is a trademark of Intersil Corporation. PSPICE is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
RF1K49221
2.5A, 60V, 0.130 Ohm, ESD Rated, Dual
N-Channel LittleFETTM Power MOSFET
The RF1K49221 Dual N-Channel power MOSFET is
manufactured using an advanced MegaFET process. This
process, which uses feature sizes approaching those of LSI
integrated circuits, gives optimum utilization of silicon,
resulting in outstanding performance. It is designed for use
in applications such as switching regulators, switching
converters, motor drivers, relay drivers, and low voltage bus
switches. This device can be operated directly from
integrated circuits.
The RF1K49221 incorporates ESD protection and is
designed to withstand 2kV (Human Body Model) of ESD.
Formerly developmental type TA49221.
Features
2.5A, 60V
r
DS(ON)
= 0.130
2kV ESD Protected
Temperature Compensating PSPICE
Model
Thermal Impedance PSPICE Model
Peak Current vs Pulse Width Curve
UIS Rating Curve
Related Literature
- TB334 "Guidelines for Soldering Surface Mount
Components to PC Boards"
Symbol
Packaging
JEDEC MS-012AA
Ordering Information
PART NUMBER
PACKAGE
BRAND
RF1K49221
MS-012AA
RF1K49221
NOTE: When ordering, use the entire part number. For ordering in
tape and reel, add the suffix 96 to the part number, i.e. RF1K4922196.
G1(2)
D1(8)
S1(1)
D1(7)
D2(6)
D2(5)
S2(3)
G2(4)
BRANDING DASH
1
2
3
4
5
Data Sheet
August 1999
8-137
Absolute Maximum Ratings
T
A
= 25
o
C Unless Otherwise Specified
RF1K49221
UNITS
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
60
V
Drain to Gate Voltage (R
GS
= 20k
)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
60
V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
20
V
Drain Current
Continuous (Pulse Width = 5s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
DM
2.5
Refer to Peak Current Curve
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Refer to UIS Curve
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
0.016
W
W/
o
C
Electrostatic Discharge Rating MIL-STD-883, Category B(2) . . . . . . . . . . . . . . . . . . . . . ESD
2
kV
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
-55 to 150
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
300
260
o
C
o
C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 125
o
C.
Electrical Specifications
T
A
= 25
o
C, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
BV
DSS
I
D
= 250
A, V
GS
= 0V, (Figure 12)
60
-
-
V
Gate to Source Threshold Voltage
V
GS(TH)
V
GS
= V
DS
, I
D
= 250
A, (Figure 11)
1
-
3
V
Zero Gate Voltage Drain Current
I
DSS
V
DS
= 60V,
V
GS
= 0V
T
A
= 25
o
C
-
-
1
A
T
A
= 150
o
C
-
-
50
A
Gate to Source Leakage Current
I
GSS
V
GS
=
20V, T
A
= 25
o
C
-
-
10
A
V
GS
=
10V, T
A
= 85
o
C
-
-
25
A
Drain to Source On Resistance
r
DS(ON)
I
D
= 2.5A,
(Figures 9, 10)
V
GS
= 10V
-
-
0.130
V
GS
= 4.5V
-
-
0.350
Turn-On Time
t
ON
V
DD
= 30V, I
D
2.5A,
R
L
= 12
, V
GS
= 10V,
R
GS
= 25
,
(Figure 14)
-
-
50
ns
Turn-On Delay Time
t
d(ON)
-
10
-
ns
Rise Time
t
r
-
25
-
ns
Turn-Off Delay Time
t
d(OFF)
-
68
-
ns
Fall Time
t
f
-
32
-
ns
Turn-Off Time
t
OFF
-
-
150
ns
Total Gate Charge
Q
g(TOT)
V
GS
= 0V to 20V
V
DD
= 48V, I
D
2.5A,
R
L
= 19.2
I
g(REF)
= 1.0mA
(Figure 14)
-
24
29
nC
Gate Charge at 10V
Q
g(10)
V
GS
= 0V to 10V
-
13
16
nC
Threshold Gate Charge
Q
g(TH)
V
GS
= 0V to 2V
-
0.8
1.0
nC
Input Capacitance
C
ISS
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
(Figure 13)
-
365
-
pF
Output Capacitance
C
OSS
-
140
-
pF
Reverse Transfer Capacitance
C
RSS
-
40
-
pF
Thermal Resistance Junction to Ambient
R
JA
Pulse Width = 1s
Device mounted on FR-4 material
-
-
62.5
o
C/W
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Source to Drain Diode Voltage
V
SD
I
SD
= 2.5A
-
-
1.25
V
Reverse Recovery Time
t
rr
I
SD
= 2.5A, dI
SD
/dt = 100A/
s
-
-
58
ns
RF1K49221
8-138
Typical Performance Curves
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
T
A
, AMBIENT TEMPERATURE (
o
C)
PO
WER DISSIP
A
TION MUL
TIPLIER
0
0
25
50
75
100
150
0.2
0.4
0.6
0.8
1.0
1.2
125
1.5
0.5
0
25
50
75
100
125
150
1.0
2.0
I
D
, DRAIN CURRENT (A)
T
A
, AMBIENT TEMPERATURE (
o
C)
3.0
2.5
t, RECTANGULAR PULSE DURATION (s)
10
-5
10
-1
10
0
10
2
0.001
10
0.1
1
10
-2
10
3
Z
JA
, NORMALIZED
THERMAL IMPED
ANCE
0.01
10
-4
10
-3
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
JA
x R
JA
+ T
A
P
DM
t
1
t
2
10
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
1
10
200
0.01
1
50
10
0.1
0.1
I
D
, DRAIN CURRENT (A)
100
LIMITED BY r
DS(ON)
AREA MAY BE
OPERATION IN THIS
V
DSS(MAX)
= 60V
T
J
= MAX RATED
T
A
= 25
o
C
DC
5ms
100ms
1s
10ms
t, PULSE WIDTH (s)
100
10
1
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
I
DM
, PEAK CURRENT (A)
T
A
= 25
o
C
V
GS
= 10V
V
GS
= 20V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
I
=
I
25
150 - T
A
125
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
RF1K49221
8-139
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
Typical Performance Curves
(Continued)
1
10
100
10
0.1
15
1
I
AS
, A
V
ALANCHE CURRENT (A)
t
AV
, TIME IN AVALANCHE (ms)
STARTING T
J
= 150
o
C
STARTING T
J
= 25
o
C
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R = 0
If R
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
0
4
8
12
0
1.5
3.0
4.5
6.0
7.5
16
20
I
D
, DRAIN CURRENT (A)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
PULSE DURATION = 80
s
T
A
= 25
o
C
V
GS
= 4.5V
V
GS
= 5V
V
GS
= 6V
V
GS
= 10V
V
GS
= 20V
V
GS
= 8V
V
GS
= 7V
DUTY CYCLE = 0.5% MAX
0
4
6
8
10
2
0
4
8
12
16
20
I
D(ON)
, ON-ST
A
TE DRAIN CURRENT (A)
V
GS
, GATE TO SOURCE VOLTAGE (V)
PULSE TEST
PULSE DURATION = 250
s
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
150
o
C
-55
o
C
25
o
C
100
200
300
400
500
0
6
4
7
5
V
GS
, GATE TO SOURCE VOLTAGE (V)
r
DS(ON)
, DRAIN T
O
SOURCE
3
8
9
10
PULSE DURATION = 250
s, V
DD
= 15V
I
D
= 1.25A
I
D
= 2.5A
I
D
= 5.0A
I
D
= 0.625A
ON RESIST
ANCE (m
)
DUTY CYCLE = 0.5% MAX
0
0.5
1.0
1.5
2.0
-80
-40
0
40
80
120
160
NORMALIZED DRAIN T
O
SOURCE
T
J
, JUNCTION TEMPERATURE (
o
C)
ON RESIST
ANCE
PULSE DURATION = 250
s
V
GS
= 10V, I
D
= 2.5A
DUTY CYCLE = 0.5% MAX
-80
-40
0
40
80
120
160
0.4
0.6
0.8
1.0
1.2
NORMALIZED GA
TE
T
J
, JUNCTION TEMPERATURE (
o
C)
V
GS
= V
DS
, I
D
= 250
A
THRESHOLD V
O
L
T
A
G
E
RF1K49221
8-140
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
Typical Performance Curves
(Continued)
1.2
1.1
1.0
0.9
0.8
-80
-40
0
40
80
120
160
T
J
, JUNCTION TEMPERATURE (
o
C)
NORMALIZED DRAIN T
O
SOURCE
BREAKDO
WN V
O
L
T
A
G
E
I
D
= 250
A
500
400
200
0
0
5
10
15
20
25
C, CAP
A
CIT
ANCE (pF)
300
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
100
C
ISS
C
OSS
C
RSS
V
GS
= 0V, f = 1MHz
C
ISS
= C
GS
+ C
GD
C
RSS
= C
GD
C
OSS
= C
DS
+ C
GD
60
45
30
15
0
20
I
g REF
(
)
I
g ACT
(
)
------------------------
t, TIME (ms)
80
I
g REF
(
)
I
g ACT
(
)
------------------------
10.0
7.5
5.0
2.5
0
V
DS
, DRAIN T
O
SO
UR
C
E V
O
LTA
G
E
(
V
)
V
GS
, GA
TE T
O
SOURCE V
O
L
T
A
GE (V)
V
DD
= BV
DSS
V
DD
= 0.75 BV
DSS
V
DD
= 0.50 BV
DSS
V
DD
= 0.25 BV
DSS
PLATEAU VOLTAGES IN
DESCENDING ORDER:
V
DD
= BV
DSS
V
DD
= BV
DSS
R
L
= 24W
I
g(REF)
= 0.30mA
V
GS
= 10V
t
P
V
GS
0.01
L
I
AS
+
-
V
DS
V
DD
R
G
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
0V
DUT
V
DD
V
DS
BV
DSS
t
P
I
AS
t
AV
0
RF1K49221
8-141
Soldering Precautions
The soldering process creates a considerable thermal stress
on any semiconductor component. The melting temperature
of solder is higher than the maximum rated temperature of
the device. The amount of time the device is heated to a high
temperature should be minimized to assure device reliability.
Therefore, the following precautions should always be
observed in order to minimize the thermal stress to which
the devices are subjected.
1. Always preheat the device.
2. The delta temperature between the preheat and soldering
should always be less than 100
o
C. Failure to preheat the
device can result in excessive thermal stress which can
damage the device.
3. The maximum temperature gradient should be less than 5
o
C
per second when changing from preheating to soldering.
4. The peak temperature in the soldering process should be
at least 30
o
C higher than the melting point of the solder
chosen.
5. The maximum soldering temperature and time must not
exceed 260
o
C for 10 seconds on the leads and case of
the device.
6. After soldering is complete, the device should be allowed
to cool naturally for at least three minutes, as forced cool-
ing will increase the temperature gradient and may result
in latent failure due to mechanical stress.
7. During cooling, mechanical stress or shock should be
avoided.
FIGURE 17. SWITCHING TIME TEST CIRCUIT
FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
Test Circuits and Waveforms
(Continued)
V
GS
0V
R
GS
R
L
DUT
+
-
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
0
0
R
L
V
GS
+
-
V
DS
V
DD
DUT
I
G(REF)
V
DD
Q
g(TH)
V
GS
= 2V
Q
g(10)
V
GS
= 10V
Q
g(TOT)
V
GS
= 20V
V
DS
V
GS
I
g(REF)
RF1K49221
8-142
PSPICE Electrical Model
SUBCKT RF1K49221 2 1 3 ;
rev 4/8/97
CA 12 8 5.60e-10
CB 15 14 5.30e-10
CIN 6 8 3.40e-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DESD1 91 9 DESD1MOD
DESD2 91 7 DESD2MOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 67.29
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 1.12e-9
LSOURCE 3 7 4.50e-10
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 28.58e-3
RGATE 9 20 15.34
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RLDRAIN 2 5 10
RLGATE 1 9 11.2
RLSOURCE 3 7 4.5
RSOURCE 8 7 RSOURCEMOD 28.85e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*30),2.5))}
.MODEL DBODYMOD D (IS = 1.95e-13 RS = 2.58e-2 TRS1 = 2.00e-3 TRS2 =-4.39e-7 CJO = 5.15e-10 TT = 5.23e-8 M=0.5)
.MODEL DBREAKMOD D (RS = 6.24e-1 TRS1 =-3.03e-4 TRS2 = 4.27e-6
.MODEL DESD1MOD D (BV=32.3 TBV1=0 TBV2=0 RS=0 TRS1=0 TRS2=0
.MODEL DESD2MOD D (BV=32.5 TBV1=0 TBV2=0 RS=25 TRS1=5.18e-4 TRS2=-1.52e-6)
.MODEL DPLCAPMOD D (CJO = 1.80e-10 IS = 1e-30 N = 10 M=0.5)
.MODEL MMEDMOD NMOS (VTO=2.755 KP=0.21 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=15.34)
.MODEL MSTROMOD NMOS (VTO=3.165 KP=3.75 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MWEAKMOD NMOS (VTO=2.520 KP=0.040 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=153.4 RS=0.1)
.MODEL RBREAKMOD RES (TC1 = 1.10e-3 TC2 = -1.09e-6)
.MODEL RDRAINMOD RES (TC1 = 1.15e-2 TC2 = 4.09e-5
.MODEL RSLCMOD RES (TC1=3.03e-3 TC2=4.52e-6)
.MODEL RSOURCEMOD RES (TC1=0 TC2=0)
.MODEL RVTHRESMOD RES (TC=-7.20e-4 TC2=-7.11e-6)
.MODEL RVTEMPMOD RES (TC1 = -3.01e-3 TC2 = 1.81e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -7.80 VOFF= -4.80)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.80 VOFF= -7.80)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.10 VOFF= 4.10)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 4.10 VOFF= 1.10)
.ENDS
NOTE:For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options;IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
1
GATE
RGATE
EVTEMP
18
22
9
+
12
13
8
14
13
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
RIN
CIN
MWEAK
RDRAIN
DBREAK
EBREAK
DBODY
DRAIN
RSOURCE
SOURCE
RBREAK
RVTEMP
VBAT
IT
EVTHRES
ESG
DPLCAP
ESLC
RSLC1
RSLC2
6
6
8
10
5
51
50
5
51
16
21
11
17
18
8
14
5
8
6
8
7
3
17
18
19
2
+
+
+
+
+
+
+
19
8
22
MMED
MSTRO
RVTHRES
LSOURCE
RLSOURCE
LDRAIN
RLDRAIN
LGATE
RLGATE
91
DESD1
DESD2
20
8
RF1K49221
8-143
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
RF1K49221
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