FN8125.0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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X5001

CPU Supervisor

FEATURES

· 200ms power-on reset delay
· Low V

detection and reset assertion

--Five standard reset threshold voltages
--Adjust low V

reset threshold voltage using

special programming sequence

--Reset signal valid to V

= 1V

· Selectable nonvolatile watchdog timer

--0.2, 0.6, 1.4 seconds
--Off selection
--Select settings through software

· Long battery life with low power consumption

--<50µA max standby current, watchdog on
--<1µA max standby current, watchdog off

· 2.7V to 5.5V operation
· SPI mode 0 interface
· Built-in inadvertent write protection

--Power-up/power-down protection circuitry
--Watchdog change latch

· High reliability
· Available packages

--8-lead TSSOP
--8-lead SOIC
--8 pin PDIP

DESCRIPTION

This device combines three popular functions, Power-
on Reset, Watchdog Timer, and Supply Voltage
Supervision in one package. This combination lowers
system cost, reduces board space requirements, and
increases reliability.

The watchdog timer provides an independent protec-
tion mechanism for microcontrollers. During a system
failure, the device will respond with a RESET signal
after a selectable time out interval. The user selects the
interval from three preset values. Once selected, the
interval does not change, even after cycling the power.

The user's system is protected from low voltage condi-
tions by the device's low V

detection circuitry. When

falls below the minimum V

trip point, the system

is reset. RESET is asserted until V

returns to proper

operating levels and stabilizes. Five industry standard
V

TRIP

thresholds are available, however, Intersil's

unique circuits allow the threshold to be reprogrammed
to meet custom requirements or to fine-tune the thresh-
old for applications requiring higher precision.

The device utilizes Intersil's proprietary Direct Write

cell for the watchdog timer control bits and the V

TRIP

storage element, providing a minimum endurance of
100,000 write cycles and a minimum data retention of
100 years.

BLOCK DIAGRAM

Watchdog

Timer

Data

Command

Decode &

Control

Logic

SCK

CS/WDI

Watchdog

Transition

Detector

Reset &

Watchdog

Timebase

Power-on/

Generation

TRIP

RESET

REset

Low Voltage

Data Sheet

April 6, 2005

FN8125.0

April 6, 2005

PIN CONFIGURATION

PIN DESCRIPTION

Pin

(SOIC/PDIP)

Pin

TSSOP

Name

Function

CS/WDI

Chip Select Input.

CS HIGH, deselects the device and the SO output pin is at

a high impedance state. Unless a nonvolatile write cycle is underway, the device

will be in the standby power mode. CS LOW enables the device, placing it in the

active power mode. Prior to the start of any operation after power-up, a HIGH to

LOW transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watch-

dog timer. The absence of a HIGH to LOW transition within the watchdog time

out period results in RESET/RESET going active.

Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data

out on this pin. The falling edge of the serial clock (SCK) clocks the data out.

Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and

memory data on this pin. The rising edge of the serial clock (SCK) latches the

input data. Send all opcodes (Table 1), addresses and data MSB first.

SCK

Serial Clock. The Serial Clock controls the serial bus timing for data input and

output. The rising edge of SCK latches in the opcode, address, or watchdog bits

present on the SI pin. The falling edge of SCK changes the data output on the

SO pin.

TRIP

Program Enable. When V

is LOW, the V

TRIP

point is fixed at the last

valid programmed level. To readjust the V

TRIP

level, requires that the V

pin be

pulled to a high voltage (15-18V).

Ground

Supply Voltage

RESET

Reset Output.

RESET is an active LOW, open drain output which goes active

whenever V

falls below the minimum V

sense level. It will remain active un-

til V

rises above the minimum V

sense level for 200ms. RESET goes active

if the watchdog timer is enabled and CS/WDI remains either HIGH or LOW long-

er than the selectable watchdog time out period. A falling edge of CS/WDI will

reset the watchdog timer. RESET goes active on power-up at 1V and remains

active for 200ms after the power supply stabilizes.

3-5,10-12

No internal connections

8-Lead SOIC/PDIP

X5001

CS/WDI

2
3

RESET

7
6

SCK
SI

SCK

SI
V

CS/WDI

1
2

3
4

8
7

6
5

8-Lead TSSOP

RESET

X5001

FN8125.0

April 6, 2005

PRINCIPLES OF OPERATION

Power-on Reset
Application of power to the X5001 activates a power-
on reset circuit. This circuit goes active at 1V and pulls
the RESET/RESET pin active. This signal prevents
the system microprocessor from starting to operate
with insufficient voltage or prior to stabilization of the
oscillator. When V

exceeds the device V

TRIP

value

for 200ms (nominal) the circuit releases RESET,
allowing the processor to begin executing code.

Low Voltage Monitoring
During operation, the X5001 monitors the V

level

and asserts RESET if supply voltage falls below a pre-
set minimum V

TRIP

. The RESET signal prevents the

microprocessor from operating in a power fail or
brownout condition. The RESET signal remains active
until the voltage drops below 1V. It also remains active
until Vcc returns and exceeds V

TRIP

for 200ms.

Watchdog Timer
The watchdog timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microproces-
sor must toggle the CS/WDI pin periodically to prevent
a RESET signal. The CS/WDI pin must be toggled
from HIGH to LOW prior to the expiration of the watch-
dog time out period. The state of two nonvolatile control
bits in the watchdog register determine the watchdog
timer period.

Vcc Threshold Reset Procedure
The X5001 is shipped with a standard V

threshold

TRIP

) voltage. This value will not change over normal

operating and storage conditions. However, in applica-
tions where the standard V

TRIP

is not exactly right, or if

higher precision is needed in the V

TRIP

value, the

X5001 threshold may be adjusted. The procedure is
described below, and requires the application of a high
voltage control signal.

Setting the V

TRIP

Voltage

This procedure is used to set the V

TRIP

to a higher

voltage value. For example, if the current V

TRIP

is 4.4V

and the new V

TRIP

is 4.6V, this procedure will directly

make the change. If the new setting is to be lower than
the current setting, then it is necessary to reset the trip
point before setting the new value.

To set the new V

TRIP

voltage, apply the desired V

TRIP

threshold voltage to the V

pin and tie the W

pin to

the programming voltage V

. Then a V

TRIP

programming

command sequence is sent to the device over the SPI
interface. This V

TRIP

programming sequence consists of

pulling CS LOW, then clocking in data 03h, 00h and 01h.
This is followed by bringing CS HIGH then LOW and
clocking in data 02h, 00h, and 01h (in order) and bringing
CS HIGH. This initiates the V

TRIP

programming

sequence. V

is brought LOW to end the operation.

Resetting the V

TRIP

Voltage

This procedure is used to set the V

TRIP

to a "native"

voltage level. For example, if the current V

TRIP

is 4.4V

and the new V

TRIP

must be 4.0V, then the V

TRIP

must

be reset. When V

TRIP

is reset, the new V

TRIP

is some-

thing less than 1.7V. This procedure must be used to
set the voltage to a lower value.

To reset the V

TRIP

voltage, apply greater than 3V to

the V

pin and tie the W

pin to the programming

voltage V

. Then a V

TRIP

command sequence is sent

to the device over the SPI interface. This V

TRIP

pro-

gramming sequence consists of pulling CS LOW, then
clocking in data 03h, 00h and 01h. This is followed by
bringing CS HIGH then LOW and clocking in data 02h,
00h, and 03h (in order) and bringing CS HIGH. This
initiates the V

TRIP

programming sequence. V

brought LOW to end the operation.

X5001

FN8125.0

April 6, 2005

Figure 4. V

TRIP

Programming Sequence

SPI INTERFACE

The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families.

The device monitors the CS/WDI line and asserts
RESET output if there is no activity within user select-
able time out period. The device also monitors the V

supply and asserts the RESET if V

falls below a

preset minimum (V

TRIP

). The device contains an 8-bit

watchdog timer register to control the watchdog time
out period. The current settings are accessed via the
SI and SO pins.

All instructions (Table 1) and data are transferred MSB
first. Data input on the SI line is latched on the first ris-
ing edge of SCK after CS goes LOW. Data is output
on the SO line by the falling edge of SCK. SCK is
static, allowing the user to stop the clock and then start
it again to resume operations where left off.

TRIP

Programming

Apply 5V to V

Decrement V

RESET pin

goes active?

Measured V

TRIP

Desired V

TRIP

DONE

Execute

Sequence

Reset V

TRIP

Set V

= V

Applied =

Desired V

TRIP

Execute

Sequence

Set V

TRIP

New V

Applied =

Old V

Applied + Error

= V

- 50mV)

Execute

Sequence

Reset V

TRIP

New V

Applied =

Old V

Applied - Error

Error < 0

Error = 0

YES

Error > 0

X5001

FN8125.0

April 6, 2005

Watchdog Timer Register

Watchdog Timer Control Bits
The watchdog timer control bits, WD

and WD

select the watchdog time out period. These nonvola-
tile bits are programmed with the set watchdog timer
(SWDT) instruction.

Write Watchdog Register Operation
Changing the watchdog timer register is a two step
process. First, the change must be enabled with by
setting the watchdog change latch (see below). This
instruction is followed by the set watchdog timer
(SWDT) instruction, which includes the data to be writ-
ten (Figure 5). Data bits 3 and 4 contain the watchdog
settings and data bits 0, 1, 2, 5, 6 and 7 must be "0".

Watchdog Change Latch
The watchdog change latch must be SET before a
Write watchdog timer operation is initiated. The
Enable Watchdog Change (EWDC) instruction will set
the latch and the Disable Watchdog Change (DWDC)
instruction will reset the latch (See Figure 6) This latch
is automatically reset upon a power-up condition and
after the completion of a valid nonvolatile write cycle.

Read Watchdog Timer Register Operation
If there is not a nonvolatile write in progress, the read
watchdog timer instruction returns the setting of the
watchdog timer control bits. The other bits are
reserved and will return'0' when read. See Figure 3.

If a nonvolatile write is in progress, the read watchdog
timer register Instruction returns a HIGH on SO. When
the nonvolatile write cycle is completed, a separate read
watchdog timer instruction should be used to determine
the current status of the watchdog control bits.

RESET Operation
The RESET (X5001) output is designed to go LOW
whenever V

has dropped below the minimum trip

point and/or the watchdog timer has reached its pro-
grammable time out limit.

The RESET output is an open drain output and
requires a pull up resistor.

Operational Notes
The device powers-up in the following state:

The device is in the low power standby state.
A HIGH to LOW transition on CS is required to enter

an active state and receive an instruction.

SO pin is high impedance.
The watchdog change latch is reset.
The RESET signal is active for t

PURST

Data Protection
The following circuitry has been included to prevent
inadvertent writes:

A EWDC instruction must be issued to enable a

change to the watchdog timeout setting.

CS must come HIGH at the proper clock count in

order to implement the requested changes to the
watchdog timeout setting.

Table 1. Instruction Set Definition

Note:

Instructions are shown with MSB in leftmost position. Instructions are transferred MSB first.

Watchdog Control Bits

Watchdog Time Out

(Typical)

WD1

WD0

1.4 seconds

600 milliseconds

200 milliseconds

disabled

Instruction Format

Instruction Name and Operation

0000 0110

EWDC: Enable Watchdog Change Operation

0000 0100

DWDC: Disable Watchdog Change Operation

0000 0001

SWDT: Set Watchdog Timer control bits:
Instruction followed by contents of register: 000(WD

) (WD

)000

See Watchdog Timer Settings and Figure 7

0000 0101

RWDT: Read Watchdog Timer control bits

X5001

FN8125.0

April 6, 2005

ABSOLUTE MAXIMUM RATINGS

Temperature under bias ................... -65°C to +135°C
Storage temperature ........................ -65°C to +150°C
Voltage on any pin with

respect to V

...................................... -1.0V to +7V

D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds)........ 300°C

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this specifi-
cation) is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect
device reliability.

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Symbol

Parameter

Limits

Unit

Test Conditions

Min.

Typ

Max.

CC1

write current

(Active)

SCK = V

x 0.1/V

x 0.9 @ 5MHz,

SO = Open

CC2

read current

(Active)

0.4

SCK = V

x 0.1/V

x 0.9 @ 5MHz,

SO = Open

SB1

standby current

WDT=OFF

µA

CS = V

, V

= V

or V

, V

= 5.5V

SB2

standby current

WDT=ON

µA

CS = V

, V

= V

or V

, V

= 5.5V

SB3

standby current

WDT=ON

µA

CS = V

, V

= V

or V

, V

= 3.6V

Input leakage current

0.1

µA

= V

to V

Output leakage current

0.1

µA

OUT

= V

to V

(1)

Input LOW voltage

-0.5

x 0.3

(1)

Input HIGH voltage

x 0.7

+ 0.5

OL1

Output LOW voltage

0.4

> 3.3V, I

= 2.1mA

OL2

Output LOW voltage

0.4

2V < V

< 3.3V, I

= 1mA

OL3

Output LOW voltage

0.4

2V, I

= 0.5mA

OH1

Output HIGH voltage

-0.8

> 3.3V, I

= -1.0mA

OH2

Output HIGH voltage

-0.4

2V < V

3.3V, I

= -0.4mA

OH3

Output HIGH voltage

-0.2

2V, I

= -0.25mA

OLRS

Reset output LOW

voltage

0.4

= 1mA

RECOMMENDED OPERATING CONDITIONS

Note:

PT= Package, Temperature

Temperature

Min.

Max.

Commercial

0°C

+70°C

Voltage Option

Supply Voltage Limits

-1.8

1.8V to 3.6V

-2.7 or -2.7A

2.7V to 5.5V

-4.5 or -4.5A

4.5V to 5.5V

X5001

FN8125.0

April 6, 2005

POWER-UP TIMING

CAPACITANCE T

= +25°C, f = 1MHz, V

= 5V.

Notes: (1) V

min. and V

max. are for reference only and are not tested.

(2) This parameter is periodically sampled and not 100% tested.

EQUIVALENT A.C. LOAD CIRCUIT

A.C. TEST CONDITIONS

A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)

Data Input Timing

Symbol

Parameter

Min.

Max.

Unit

PUR

(2)

Power-up to read operation

PUW

(2)

Power-up to write operation

Symbol

Test

Max.

Unit

Conditions

OUT

(2)

Output capacitance (SO, RESET)

OUT

= 0V

(2)

Input capacitance (SCK, SI, CS)

= 0V

Output

100pF

3.3k

RESET

30pF

1.64k

Input pulse levels

x 0.1 to V

x 0.9

Input rise and fall times

10ns

Input and output timing level

x0.5

SymboL

Parameter

1.8V-3.6V

2.7V-5.5V

Unit

Min. Max.

SCK

Clock frequency

MHz

CYC

Cycle time

1000

500

LEAD

CS lead time

400

200

LAG

CS lag time

400

200

Clock HIGH time

400

200

Clock LOW time

400

200

Data setup time

100

Data hold time

100

(3)

Input rise time

µs

(3)

Input fall time

µs

CS deselect time

250

150

(4)

Write cycle time

X5001

FN8125.0

April 6, 2005

Data Output Timing

Notes: (3) This parameter is periodically sampled and not 100% tested.

(4) t

is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile

write cycle.

Figure 10. Data Output Timing

Figure 11. Data Input Timing

Symbol Parameter

1.8V-3.6V

2.7V-5.5V

Unit

Min.

Max.

Min.

Max.

SCK

Clock frequency

MHz

DIS

Output disable time

400

200

Output valid from clock low

400

200

Output hold time

(3)

Output rise time

300

150

(3)

Output fall time

300

150

SCK

MSB Out

MSB1 Out

LSB Out

ADDR

LSB IN

CYC

DIS

LAG

SCK

MSB In

LAG

LEAD

LSB In

High Impedance

X5001

FN8125.0

April 6, 2005

SYMBOL TABLE

Figure 12. Power-Up and Power-Down Timing

RESET Output Timing

Note:

(5) This parameter is periodically sampled and not 100% tested.
PT = Package, Temperature

WAVEFORM

INPUTS

OUTPUTS

Must be

steady

Will be

steady

May change

from LOW

to HIGH

Will change

from LOW

to HIGH

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

Don't Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance

Symbol

Parameter

Min.

Typ.

Max.

Unit

TRIP

Reset trip point voltage, X5001PT-4.5A
Reset trip point voltage, X5001PT-4.5
Reset trip point voltage, X5001PT-2.7A
Reset trip point voltage, X5001PT-2.7
Reset trip point voltage, X5001PT-1.8

4.50
4.25
2.85
2.55
1.70

4.63
4.38
2.92
2.63
1.75

4.75
4.50
3.00
2.70
1.80

PURST

Power-up reset timeout

100

200

280

RPD

(5)

detect to reset/output

500

(5)

fall time

0.1

(5)

rise time

0.1

RVALID

Reset valid V

PURST

RPD

RESET (X5001)

0 Volts

TRIP

X5001

FN8125.0

April 6, 2005

TRIP

Programming Parameters

Parameter

Description

Min.

Max.

Unit

VPS

TRIP

program enable voltage setup time

µs

VPH

TRIP

program enable voltage hold time

µs

PCS

TRIP

programming CS inactive time

µs

TSU

TRIP

setup time

µs

THD

TRIP

hold (stable) time

TRIP

write cycle time

VPO

TRIP

program enable voltage Off time (between successive adjustments)

µs

TRIP

program recovery period (between successive adjustments)

Programming voltage

TRAN

TRIP

programmed voltage range

1.7

5.0

ta1

Initial V

TRIP

program voltage accuracy (V

applied-V

TRIP

) (programmed at 25°C)

-0.1

+0.4

ta2

Subsequent V

TRIP

program voltage accuracy [(V

applied-V

ta1

)-V

TRIP

Programmed at 25°C.]

-25

+25

TRIP

program voltage repeatability (Successive program operations. Programmed at

25°C.)

-25

+25

TRIP

program variation after programming (0-75°C). (programmed at 25°C)

-25

+25

TRIP programming parameters are periodically sampled and are not 100% tested.

X5001

FN8125.0

April 6, 2005

Watchdog Timer On (V

= 5V)

Watchdog Timer On (V

= 3V)

Watchdog Timer Off (V

= 3V, 5V)

-40C

25C

90C

Temp (c)

Isb (µA)

Supply Current vs. Temperature (I

)

WDO

vs. Voltage/Temperature (WD1, 0 = 1, 1)

TRIP

vs. Temperature (programmed at 25°C)

WDO

vs. Voltage/Temperature (WD1, 0 = 1, 0)

PURST

vs. Temperature

WDO

vs. Voltage/Temperature (WD1, 0 0 = 0, 1)

1.85

1.80

1.75

1.70

1.65

1.60

1.55

1.50

1.45

1.40

1.7

3.1

4.5

90°C

25°C

-40°C

set (s

econ

Voltage

5.025

5.000

4.975

3.525

3.500

3.475

2.525

2.500

2.475

Volta

Temperature

TRIP

= 5V

TRIP

= 3.5V

TRIP

= 2.5V

0.85

0.80

0.75

0.70

0.65

0.60

1.7

4.5

eset (

secon

Voltage

3.1

90°C

25°C

-40°C

275
270
265
260

255
250
245

240

235

-40

Degrees °C

280

Time

(ms

)

90°C

25°C

-40°C

0.28
0.27
0.26
0.25
0.24
0.23
0.22
0.21
0.20

0.29

eset (

secon

Voltage

1.7

3.1

4.5

0.35

0.55

1.0

0.30

X5001

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8125.0

April 6, 2005

Ordering Information

Part Mark Information

Range

TRIP

Range

Package

Operating Temperature Range

Part Number RESET

(Active LOW)

4.5-5.5V

4.5.4.75

8-Pin PDIP

0-70°C

X5001P-4.5A

8-Lead SOIC

0-70°C

X5001S8-4.5A

8-Lead TSSOP

0-70°C

X5001V8-4.5A

4.5-5.5V

4.25.4.5

8-Pin PDIP

0-70°C

X5001P

8-Lead SOIC

0-70°C

X5001S8

8-Lead TSSOP

0-70°C

X5001V8

2.7-5.5V

2.85-3.0

8-Lead SOIC

0-70°C

X5001S8-2.7A

2.7-5.5V

2.55-2.7

8-Lead SOIC

0-70°C

X5001S8-2.7

8-Lead TSSOP

0-70°C

X5001V8-2.7

8-Lead TSSOP

501AG = 1.8 to 3.6V, 0 to +70°C, V

TRIP

= 1.7-1.8V

YWW

XXXXX

501AH = 1.8 to 3.6V, -40 to +85°C, V

TRIP

= 1.7-1.8V

501F = 2.7 to 5.5V, 0 to +70°C, V

TRIP

= 2.55-2.7V

501G = 2.7 to 5.5V, -40 to +85°C, V

TRIP

= 2.55-2.7V

X501 = 4.5 to 5.5V, 0 to +70°C, V

TRIP

= 4.25-4.5V

501I = 4.5 to 5.5V, -40 to +85°C, V

TRIP

= 4.25-4.5V

8-Lead SOIC

X5001

YWW XX

AG = 1.8 to 3.6V, 0 to +70°C, V

TRIP

= 1.7-1.8V

AH = 1.8 to 3.6V, -40 to +85°C, V

TRIP

= 1.7-1.8V

F = 2.7 to 5.5V, 0 to +70°C, V

TRIP

= 2.55-2.7V

G = 2.7 to 5.5V, -40 to +85°C, V

TRIP

= 2.55-2.7V

I = 4.5 to 5.5V, -40 to +85°C, V

TRIP

= 4.25-4.5V

501AN = 2.7 to 5.5V, 0 to +70°C, V

TRIP

= 2.85-3.0V

501AP = 2.7 to 5.5V, -40 to +85°C, V

TRIP

= 2.85-3.0V

501AL = 4.5 to 5.5V, 0 to +70°C, V

TRIP

= 4.5-4.75V

501AM = 4.5 to 5.5V, -40 to +85°C, V

TRIP

= 4.5-4.75V

AN = 2.7 to 5.5V, 0 to +70°C, V

TRIP

= 2.85-3.0V

AP = 2.7 to 5.5V, -40 to +85°C, V

TRIP

= 2.85-3.0V

AL = 4.5 to 5.5V, 0 to +70°C, V

TRIP

= 4.5-4.75V

AM = 4.5 to 5.5V, -40 to +85°C, V

TRIP

= 4.5-4.75V

Blank = 4.5 to 5.5V, 0 to +70°C, V

TRIP

= 4.25-4.5V

YWW = year/work week device is packaged.

X5001

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X5001V8

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X5001V8