X9250

Low Noise/Low Power/SPI Bus/256 Taps

Quad Digitally Controlled Potentiometers

(XDCPTM)

FEATURES

· Four potentiometers in one package
· 256 resistor taps/pot - 0.4% resolution
· SPI serial interface
· Wiper resistance, 40

typical @ V

= 5V

· Four nonvolatile data registers for each pot
· Nonvolatile storage of wiper position
· Standby current < 5µA max (total package)
· Power supplies

--V

= 2.7V to 5.5V

--V+ = 2.7V to 5.5V
--V = -2.7V to -5.5V

· 100k

, 50k

total pot resistance

· High reliability

--Endurance 100,000 data changes per bit per

register

--Register data retention - 100 years

· 24-lead SOIC, 24-lead TSSOP
· Dual supply version of X9251

DESCRIPTION

The X9250 integrates 4 digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated circuit.

The digitally controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
SPI bus interface. Each potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array though the switches. Power up recalls
the contents of DR0 to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

BLOCK DIAGRAM

Wiper

Counter

(WCR)

Resistor

Array

Wiper

Counter

(WCR)

Interface

and

Control

Circuitry

SCK

A0
A1

Data

Wiper

Counter

(WCR)

Resistor

Array
Pot 2

Wiper

Counter

(WCR)

Resistor

Array
Pot 3

Pot1

HOLD

Pot 0

V+

V-

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-352-6832

Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Data Sheet

FN8165.1

March 25, 2005

FN8165.1

March 25, 2005

PIN DESCRIPTIONS

Serial Output (SO)

SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.

Serial Input

SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.

Serial Clock (SCK)

The SCK input is used to clock data into and out of the
X9250.

Chip Select (CS)

When CS is HIGH, the X9250 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9250, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.

Hold (HOLD)

HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.

Device Address (A

- A

)

The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9250. A maximum of 4 devices may occupy the
SPI serial bus.

Potentiometer Pins

- V

), V

)

The R

and R

pins are equivalent to the terminal

connections on a mechanical potentiometer.

W0 -

)

The wiper pins are equivalent to the wiper terminal of a
mechanical potentiometer.

Hardware Write Protect Input (WP)

The WP pin when LOW prevents nonvolatile writes to
the Data Registers.

Analog Supplies (V+, V-)

The analog supplies V+, V- are the supply voltages for
the XDCP analog section.

PIN CONFIGURATION

PIN NAMES

Symbol

Description

SCK

Serial Clock

SI, SO

Serial Data

-A

Device Address

Potentiometer Pins
(terminal equivalent)

Potentiometer Pins
(wiper equivalent)

Hardware Write Protection

V+,V-

Analog Supplies

System Supply Voltage

System Ground

No Connection

V+

HOLD

SCK

SOIC/TSSOP

X9250

FN8165.1

March 25, 2005

DEVICE DESCRIPTION

Serial Interface

The X9250 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.

The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.

Array Description

The X9250 is comprised of four resistor arrays. Each
array contains 255 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V

and V

inputs).

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V

) output. Within each individual array only one

switch may be turned on at a time.

These switches are controlled by a Wiper Counter
Register (WCR). The 8 bits of the WCR are decoded
to select, and enable, one of 256 switches.

Wiper Counter Register (WCR)

The X9250 contains four Wiper Counter Registers,
one for each XDCP potentiometer. The WCR is
equivalent to a serial-in, parallel-out register/counter
with its outputs decoded to select one of 256 switches
along its resistor array. The contents of the WCR can
be altered in four ways: it may be written directly by the
host via the write Wiper Counter Register instruction
(serial load); it may be written indirectly by transferring
the contents of one of four associated Data Registers
via the XFR Data Register or Global XFR Data
Register instructions (parallel load); it can be modified
one step at a time by the increment/decrement
instruction. Finally, it is loaded with the contents of its
Data Register zero (DR0) upon power-up.

The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9250 is powered-
down. Although the register is automatically loaded
with the value in R0 upon power-up, this may be
different from the value present at power-down.

Data Registers

Each potentiometer has four 8-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a nonvolatile operation and will take
a maximum of 10ms.

If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.

Data Register Detail

(MSB)

(LSB)

X9250

FN8165.1

March 25, 2005

Figure 1. Detailed Potentiometer Block Diagram

Write in Process

The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received
by the device. The progress of this internal write
operation can be monitored by a write in process bit
(WIP). The WIP bit is read with a read status
command.

INSTRUCTIONS

Identification (ID) Byte

The first byte sent to the X9250 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier, for the
X9250 this is fixed as 0101[B] (refer to Figure 2).

The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A

- A

input

pins. The X9250 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9250 to successfully
continue the command sequence. The A

- A

inputs

can be actively driven by CMOS input signals or tied to
V

or V

The remaining two bits in the slave byte must be set to 0.

Figure 2. Identification Byte Format

Instruction Byte

The next byte sent to the X9250 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the four pots and, when applicable,
they point to one of four associated registers. The
format is shown below in Figure 3.

Figure 3. Instruction Byte Format

Serial Data Path

From Interface

Circuitry

Serial
Bus
Input

Parallel

Input

Counter

Register

Inc/Dec

Logic

UP/DN

CLK

Modified SCK

UP/DN

o
u
n

e
c
o
d
e

If WCR = 00[H] then V

= V

WCR = FF[H]

then

= V

Wiper

(One of Four Arrays)

(WCR)

Bus

Device Type

Identifier

Device Address

Pot Select

Select

Instructions

X9250

FN8165.1

March 25, 2005

The four high order bits of the instruction byte specify
the operation. The next two bits (R

and R

) select

one of the four registers that is to be acted upon when
a register oriented instruction is issued. The last two
bits (P1 and P

) selects which one of the four

potentiometers is to be affected by the instruction.

Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte.
These instructions are:

XFR Data Register to Wiper Counter Register--This

transfers the contents of one specified Data Register
to the associated Wiper Counter Register.

XFR Wiper Counter Register to Data Register--This

transfers the contents of the specified Wiper Counter
Register to the specified associated Data Register.

Global XFR Data Register to Wiper Counter Regiter--

This transfers the contents of all specified Data Reg-
isters to the associated Wiper Counter Registers.

Global XFR Wiper Counter Register to Data Regiter--

This transfers the contents of all Wiper Counter Reg-
isters to the specified associated Data Registers.

The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by t

WRL

. A transfer

from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of t

to complete. The transfer can occur

between one of the four potentiometers and one of its
associated registers; or it may occur globally, where
the transfer occurs between all potentiometers and one
associated register.

Five instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9250; either between the host and
one of the data registers or directly between the host
and the Wiper Counter Register. These instructions
are:

Read Wiper Counter Register--read the current

wiper position of the selected pot,

Write Wiper Counter Register--change current

wiper position of the selected pot,

Read Data Register--read the contents of the

selected data register;

Write Data Register--write a new value to the

selected data register.

Read Status--This command returns the contents

of the WIP bit which indicates if the internal write
cycle is in progress.

The sequence of these operations is shown in Figure
5 and Figure 6.

The final command is Increment/Decrement. It is
different from the other commands, because it's length
is indeterminate. Once the command is issued, the
master can clock the selected wiper up and/or down in
one resistor segment steps; thereby, providing a fine
tuning capability to the host. For each SCK clock pulse
(t

HIGH

) while SI is HIGH, the selected wiper will move

one resistor segment towards the V

terminal.

Similarly, for each SCK clock pulse while SI is LOW,
the selected wiper will move one resistor segment
towards the V

terminal. A detailed illustration of the

sequence and timing for this operation are shown in
Figure 7 and Figure 8.

X9250

FN8165.1

March 25, 2005

Figure 8. Increment/Decrement Timing Limits

Table 1. Instruction Set

Instruction

Instruction Set

Operation

Read Wiper Counter
Register

Read the contents of the Wiper Counter
Register pointed to by P

- P

Write Wiper Counter
Register

Write new value to the Wiper Counter Register
pointed to by P

- P

Read Data Register

Read the contents of the Data Register
pointed to by P

- P

and R

- R

Write Data Register

Write new value to the Data Register pointed to
by P

- P

and R

- R

XFR Data Register to
Wiper Counter Register

Transfer the contents of the Data Register
pointed to by R

- R

to the Wiper Counter

- P

XFR Wiper Counter
Register to Data Register

Transfer the contents of the Wiper Counter
Register pointed to by P

- P

to the Register

pointed to by R

- R

Global XFR Data Register
to Wiper Counter Register

Transfer the contents of the Data Registers
pointed to by R

- R

of all four pots to their

respective Wiper Counter Register

Global XFR Wiper Counter
Register to Data Register

Transfer the contents of all Wiper Counter
Registers to their respective data Registers
pointed to by R

- R

of all four pots

Increment/Decrement
Wiper Counter Register

Enable Increment/decrement of the Wiper
Counter Register pointed to by P

- P

Read Status (WIP bit)

Read the status of the internal write cycle, by
checking the WIP bit.

SCK

INC/DEC CMD Issued

WRID

Voltage Out

X9250

FN8165.1

March 25, 2005

Instruction Format

Notes: (1) "A1 ~ A0": stands for the device addresses sent by the master.

(2) WPx refers to wiper position data in the Counter Register
(2) "I": stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) "D": stands for the decrement operation, SI held LOW during active SCK phase (high).

Read Wiper Counter Register(WCR)

Write Wiper Counter Register (WCR)

Read Data Register (DR)

Write Data Register (DR)

Transfer Data Register (DR) to Wiper Counter Register (WCR)

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

WCR

addresses

wiper position

(sent by X9250 on SO)

Rising

Edge

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

WCR

addresses

Data Byte

(sent by Host on SI)

Rising

Edge

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

DR and WCR

addresses

Data Byte

(sent by X9250 on SO)

Rising

Edge

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

DR and WCR

addresses

Data Byte

(sent by host on SI)

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

0 1 0 1 0 0

1 1 0 0

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

DR and WCR

addresses

Rising

Edge

0 1 0 1 0 0

1 1 0 1 R1 R0 P1 P0

X9250

FN8165.1

March 25, 2005

Transfer Wiper Counter Register (WCR) to Data Register (DR)

Increment/Decrement Wiper Counter Register (WCR)

Global Transfer Data Register (DR) to Wiper Counter Register (WCR)

Global Transfer Wiper Counter Register (WCR) to Data Register (DR)

Read Status

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

DR and WCR

addresses

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

0 1

1 0

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

WCR

addresses

increment/decrement

(sent by master on SI)

Rising

Edge

0 X X

I/D I/D

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

addresses

Rising

Edge

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

addresses

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

0 1 0 1 0 0

1 0 0 0

0 0

Falling

Edge

device type

identifier

device

addresses

instruction

opcode

Data Byte

(sent by X9250 on SO)

Rising

Edge

X9250

FN8165.1

March 25, 2005

ABSOLUTE MAXIMUM RATINGS

Temperature under bias......................... -65 to +135

Storage temperature ............................. -65 to +150

Voltage on SCK, SCL or any address input

with respect to V

................................. -1V to +7V

Voltage on V+ (referenced to V

) ........................ 10V

Voltage on V- (referenced to V

) ........................-10V

(V+) - (V-)............................................................... 12V
Any V

...............................................................V+

Any V

................................................................. V-

Lead temperature (soldering, 10 seconds) ........ 300

(10 seconds)................................................±15mA

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

potentiometer.

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiom-

eter. It is a measure of the error in step size.

(3) MI = RTOT/255 or (V

- V

)/255, single pot

(4) Individual array resolutions.

Symbol

Parameter

Limits

Test Conditions

Min.

Typ.

Max.

Unit

End to end resistance tolerance

±20

Power rating

25°C, each pot

Wiper current

±7.5

Wiper resistance

150

250

Wiper current =

1mA

Vv+

Voltage on V+ pin

X9250

+4.5

+5.5

X9250-2.7

+2.7

+5.5

Vv-

Voltage on V- pin

X9250

-5.5

-4.5

X9250-2.7

-5.5

-2.7

TERM

Voltage on any V

or V

V-

V+

Noise

-120

dBV

Ref: 1kHz

Resolution

(4)

0.6

Absolute linearity

(1)

±1

(3)

w(n)(actual)

- V

w(n)(expected)

Relative linearity

(2)

±0.6

(3)

w(n + 1 -

w(n) + MI

]

Temperature coefficient of R

TOTAL

300

ppm/°C

Ratiometric Temperature
Coefficient

±20

ppm/°C

Potentiometer Capacitances

10/10/25

See Circuit #3

RECOMMENDED OPERATING CONDITIONS

Temp

Min.

Max.

Commercial

+70

Industrial

-40

+85

Device

Supply Voltage (V

) Limits

(4)

X9250

10%

X9250-2.7

2.7V to 5.5V

X9250

FN8165.1

March 25, 2005

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

ENDURANCE AND DATA RETENTION

CAPACITANCE

POWER-UP TIMING

POWER UP AND DOWN REQUIREMENT

The are no restrictions on the sequencing of the bias supplies V

, V+, and V- provided that all three supplies reach

their final values within 1msec of each other. At all times, the voltages on the potentiometer pins must be less than V+
and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all supplies reach their
final value. The V

ramp rate spec is always in effect.

Notes: (5) This parameter is periodically sampled and not 100% tested

(6) t

PUR

and t

PUW

are the delays required from the time the third (last) power supply (V

, V+ or V-) is stable until the specific instruction can be

issued. These parameters are periodically sampled and not 100% tested.

(7) Sample tested only.

A.C. TEST CONDITIONS

Symbol

Parameter

Limits

Test Conditions

Min.

Typ.

Max.

Unit

CC1

supply current

(active)

400

µA

SCK

= 2MHz, SO = Open,

Other Inputs = V

CC2

supply current

(nonvolatile write)

SCK

= 2MHz, SO = Open,

Other Inputs = V

current (standby)

µA

SCK = SI = V

, Addr. = V

Input leakage current

µA

= V

to V

Output leakage current

µA

OUT

= V

to V

Input HIGH voltage

x 0.7

+ 0.1

Input LOW voltage

-0.5

x 0.3

Output LOW voltage

0.4

= 3mA

Parameter

Min.

Unit

Minimum endurance

100,000

Data changes per bit per register

Data retention

100

Years

Symbol

Test

Max.

Unit

Test Conditions

OUT

(5)

Output capacitance (SO)

OUT

= 0V

(5)

Input capacitance (A0, A1, SI, and SCK, CS)

= 0V

Symbol

Parameter Min.

Max.

Unit

PUR

(6)

Power-up to initiation of read operation

PUW

(6)

Power-up to initiation of write operation

(7)

power up ramp rate

0.2

V/msec

Input pulse levels

x 0.1 to V

x 0.9

Input rise and fall times

10ns

Input and output timing level

x 0.5

X9250

FN8165.1

March 25, 2005

Circuit #3 SPICE Macro Model

EQUIVALENT A.C. LOAD CIRCUIT

AC TIMING

10pF

TOTAL

25pF

10pF

1533

100pF

SDA Output

2.7V

100pF

Symbol

Parameter

Min.

Max.

Unit

SCK

SSI/SPI clock frequency

2.0

MHz

CYC

SSI/SPI clock cycle time

500

SSI/SPI clock high time

200

SSI/SPI clock low time

200

LEAD

Lead time

250

LAG

Lag time

250

SI, SCK, HOLD and CS input setup time

SI, SCK, HOLD and CS input hold time

SI, SCK, HOLD and CS input rise time

µs

SI, SCK, HOLD and CS input fall time

µs

DIS

SO output disable Time

500

SO output valid time

100

SO output hold time

SO output rise time

SO output fall time

HOLD

HOLD time

400

HSU

HOLD setup time

100

HOLD hold time

100

HOLD low to output in high Z

100

HOLD high to output in low Z

100

Noise suppression time constant at SI, SCK, HOLD and CS inputs

TBD

CS deselect time

µs

WPASU

WP, A0 and A1 setup time

WPAH

WP, A0 and A1 hold time

X9250

FN8165.1

March 25, 2005

HIGH-VOLTAGE WRITE CYCLE TIMING

XDCP TIMING

SYMBOL TABLE

TIMING DIAGRAMS

Input Timing

Symbol

Parameter

Typ.

Max.

Unit

High-voltage write cycle time (store instructions)

Symbol

Parameter

Min.

Max.

Unit

WRPO

Wiper response time after the third (last) power supply is stable

µs

WRL

Wiper response time after instruction issued (all load instructions)

µs

WRID

Wiper response time from an active SCL/SCK edge (increment/decrement instruc-
tion)

µs

WAVEFORM

INPUTS

OUTPUTS

Must be
steady

Will be
steady

May change
from Low to
High

Will change
from Low to
High

May change
from High to
Low

Will change
from High to
Low

Don't Care:
Changes
Allowed

Changing:
State Not
Known

N/A

Center Line
is High
Impedance

...

SCK

MSB

LSB

High Impedance

LEAD

LAG

CYC

...

X9250

FN8165.1

March 25, 2005

APPLICATIONS INFORMATION

Basic Configurations of Electronic Potentiometers

Application Circuits

Three terminal Potentiometer;
Variable voltage divider

Two terminal Variable Resistor;
Variable current

Noninverting Amplifier

Voltage Regulator

Offset Voltage Adjustment

Comparator with Hysterisis

= (1+R

adj

(REG) = 1.25V (1+R

)+I

adj

(REG)

317

= {R

/(R

) V

(max)

= {R

/(R

) V

(min)

100k

10k

-12V

+12V

TL072

}

X9250

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8165.1

March 25, 2005

Ordering Information

Device

Limits

Blank = 5V ± 10%
-2.7 = 2.7 to 5.5V

Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C

Package
S24 = 24-Lead SOIC
V24 = 24-Lead TSSOP

Potentiometer Organization
T =

100k

50k

X9250

S & V Package Marking

Line #1

(Blank)

Line #2

(Part Number)

Line #3

(Date Code) (*)

Line #4

(Blank)

= F

2.7V 0 to 70°C

G 2.7V -40 to +85°C
I

-40 to +85°C

X9250

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