FN8166.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X9251

Single Supply/Low Power/256-Tap/SPI Bus

Quad Digitally-Controlled (XDCPTM)

Potentiometer

FEATURES

· Four potentiometers in one package
· 256 resistor taps0.4% resolution
· SPI Serial Interface for write, read, and transfer

operations of the potentiometer

· Wiper resistance: 100

typical @ V

= 5V

· 4 Non-volatile data registers for each

potentiometer

· Non-volatile storage of multiple wiper positions
· Standby current < 5µA max
· V

: 2.7V to 5.5V Operation

· 50k

, 100k

versions of total resistance

· 100 yr. data retention
· Single supply version of X9250
· Endurance: 100,000 data changes per bit per

register

· 24 Ld SOIC, 24 Ld TSSOP
· Low power CMOS
· Pb-free plus anneal available (RoHS compliant)

DESCRIPTION

The X9251 integrates four digitally controlled potentio-
meters (XDCP) on a monolithic CMOS integrated
circuit.

The digitally controlled potentiometers are imple-
mented with a combination of resistor elements and
CMOS switches. The position of the wipers are
controlled by the user through the SPI bus interface.
Each potentiometer has associated with it a volatile
Wiper Counter Register (WCR) and four non-volatile
Data Registers that can be directly written to and read
by the user. The content of the WCR controls the
position of the wiper. At power-up, the device recalls
the content of the default Data Registers of each DCP
(DR00, DR10, DR20, and DR30) to the corresponding
WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

FUNCTIONAL DIAGRAM

POWER UP,

INTERFACE

CONTROL

AND

SPI

DCP0

HOLD

SCK

WCR0

DR00
DR01

DR02
DR03

DCP1

WCR1

DR10
DR11

DR12
DR13

DCP2

WCR2

DR20
DR21

DR22
DR23

DCP3

WCR3

DR30
DR31

DR32
DR33

Interface

STATUS

Data Sheet

September 14, 2005

FN8166.2

September 14, 2005

Ordering Information

PART NUMBER

PART MARKING

LIMITS (V)

POTENTIOMENTER

ORGANIZATION (k

)

TEMP RANGE

(°C)

PACKAGE

X9251UP24I

X9251UP I

5 ±10%

-40 to +85

24 Ld PDIP

X9251US24*

X9251US

0 to 70

24 Ld SOIC (300MIL)

X9251US24Z* (Note)

X9251US Z

0 to 70

24 Ld SOIC (300MIL) (Pb-Free)

X9251US24I*

X9251US I

-40 to +85

24 Ld SOIC (300MIL)

X9251US24IZ* (Note)

X9251US Z I

-40 to +85

24 Ld SOIC (300MIL) (Pb-Free)

X9251UV24

X9251UV

0 to 70

24 Ld TSSOP (4.4mm)

X9251UV24Z (Note)

X9251UV Z

0 to 70

24 Ld TSSOP (4.4mm) (Pb-free)

X9251UV24I

X9251UV I

-40 to +85

24 Ld TSSOP (4.4mm)

X9251UV24IZ (Note)

X9251UV Z I

-40 to +85

24 Ld TSSOP (4.4mm) (Pb-free)

X9251TP24I

100

-40 to +85

24 Ld PDIP

X9251TS24*

X9251TS

0 to 70

24 Ld SOIC (300MIL)

X9251TS24Z* (Note)

X9251TS Z

0 to 70

24 Ld SOIC (300MIL) (Pb-Free)

X9251TS24I*

X9251TS I

-40 to +85

24 Ld SOIC (300MIL)

X9251TS24IZ* (Note)

X9251TS Z I

-40 to +85

24 Ld SOIC (300MIL) (Pb-Free)

X9251TV24

X9251TV

0 to 70

24 Ld TSSOP (4.4mm)

X9251TV24Z (Note)

X9251TV Z

0 to 70

24 Ld TSSOP (4.4mm) (Pb-free)

X9251TV24I

X9251TV I

-40 to +85

24 Ld TSSOP (4.4mm)

X9251TV24IZ (Note)

X9251TV Z I

-40 to +85

24 Ld TSSOP (4.4mm) (Pb-free)

X9251US24-2.7*

X9251US F

2.7 to 5.5

0 to 70

24 Ld SOIC (300MIL)

X9251US24Z-2.7* (Note)

X9251US Z F

0 to 70

24 Ld SOIC (300MIL) (Pb-Free)

X9251US24I-2.7*

X9251US G

-40 to +85

24 Ld SOIC (300MIL)

X9251US24IZ-2.7* (Note)

X9251US Z G

-40 to +85

24 Ld SOIC (300MIL) (Pb-Free)

X9251UV24-2.7

X9251UV F

0 to 70

24 Ld TSSOP (4.4mm)

X9251UV24Z-2.7 (Note)

X9251UV Z F

0 to 70

24 Ld TSSOP (4.4mm) (Pb-free)

X9251UV24I-2.7

X9251UV G

-40 to +85

24 Ld TSSOP (4.4mm)

X9251UV24IZ-2.7 (Note)

X9251UV Z G

-40 to +85

24 Ld TSSOP (4.4mm) (Pb-free)

X9251TS24-2.7*

X9251TS F

100

0 to 70

24 Ld SOIC (300MIL)

X9251TS24Z-2.7* (Note)

X9251TS Z F

0 to 70

24 Ld SOIC (300MIL) (Pb-Free)

X9251TS24I-2.7*

X9251TS G

-40 to +85

24 Ld SOIC (300MIL)

X9251TS24IZ-2.7* (Note)

X9251TS Z G

-40 to +85

24 Ld SOIC (300MIL) (Pb-Free)

X9251TV24-2.7

X9251TV F

0 to 70

24 Ld TSSOP (4.4mm)

X9251TV24Z-2.7 (Note)

X9251TV Z F

0 to 70

24 Ld TSSOP (4.4mm) (Pb-free)

X9251TV24I-2.7

X9251TV G

-40 to +85

24 Ld TSSOP (4.4mm)

X9251TV24IZ-2.7 (Note)

X9251TV Z G

-40 to +85

24 Ld TSSOP (4.4mm) (Pb-free)

*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

X9251

FN8166.2

September 14, 2005

CIRCUIT LEVEL APPLICATIONS

· Vary the gain of a voltage amplifier
· Provide programmable dc reference voltages for

comparators and detectors

· Control the volume in audio circuits
· Trim out the offset voltage error in a voltage ampli-

fier circuit

· Set the output voltage of a voltage regulator
· Trim the resistance in Wheatstone bridge circuits
· Control the gain, characteristic frequency and

Q-factor in filter circuits

· Set the scale factor and zero point in sensor signal

conditioning circuits

· Vary the frequency and duty cycle of timer ICs
· Vary the dc biasing of a pin diode attenuator in RF

circuits

· Provide a control variable (I, V, or R) in feedback

circuits

SYSTEM LEVEL APPLICATIONS

· Adjust the contrast in LCD displays
· Control the power level of LED transmitters in

communication systems

· Set and regulate the DC biasing point in an RF

power amplifier in wireless systems

· Control the gain in audio and home entertainment

systems

· Provide the variable DC bias for tuners in RF wire-

less systems

· Set the operating points in temperature control

systems

· Control the operating point for sensors in industrial

systems

· Trim offset and gain errors in artificial intelligent

systems

PIN CONFIGURATION

PIN ASSIGNMENTS

Note 1: A0 - A1 device address pins must be tied to a logic level.

Pin

(SOIC)

Symbol

Function

Serial Data Output for SPI bus

Device Address for SPI bus. (See Note 1)

Wiper Terminal of DCP3

High Terminal of DCP3

Low Terminal of DCP3

System Supply Voltage

Low Terminal of DCP0

High Terminal of DCP0

Wiper Terminal of DCP0

SPI bus. Chip Select active low input

Hardware Write Protect - active low

Serial Data Input for SPI bus

Device Address for SPI bus. (See Note 1)

Low Terminal of DCP1

High Terminal of DCP1

Wiper Terminal of DCP1

System Ground

Wiper Terminal of DCP2

High Terminal of DCP2

Low Terminal of DCP2

SCK

Serial Clock for SPI bus

HOLD

Device select. Pauses the SPI serial bus.

6, 19

No Connect

2
3

4
5

6
7

8
9

23
22

21
20

19
18

17
16

HOLD

SCK
R

SOIC/TSSOP

X9251

11
12

X9251

FN8166.2

September 14, 2005

PIN DESCRIPTIONS

Bus Interface Pins

ERIAL

UTPUT

(SO)

SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.

ERIAL

NPUT

(SI)

SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the device
registers are input on this pin. Data is latched by the
rising edge of the serial clock.

ERIAL

LOCK

(SCK)

The SCK input is used to clock data into and out of the
X9251.

OLD

(HOLD)

HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.

EVICE

DDRESS

(A1 - A0)

The address inputs are used to set the two least
significant bits of the slave address. A match in the
slave address serial data stream must be made with
the address input in order to initiate communication
with the X9251. Device pins A1 - A0 must be tie to a
logic level which specify the internal address of the
device, see Figures 2, 3, 4, 5 and 6.

HIP

ELECT

(CS)

When CS is HIGH, the X9251 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device is in the standby
state. CS LOW enables the X9251, placing it in the
active power mode. It should be noted that after a
power-up, a HIGH to LOW transition on CS is required
prior to the start of any operation.

Potentiometer Pins

, R

The R

and R

pins are equivalent to the terminal

connections on a mechanical potentiometer. Since
there are 4 potentiometers, there are 4 sets of R

and

such that R

and R

are the terminals of DCP0

and so on.

The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are 4
potentiometers, there are 4 sets of R

such that R

is the terminals of DCP0 and so on.

Supply Pins

YSTEM

UPPLY

OLTAGE

)

AND

UPPLY

ROUND

)

The V

pin is the system supply voltage. The V

pin is the system ground.

Other Pins

ONNECT

No connect pins should be left floating. This pins are
used for Intersil manufacturing and testing purposes.

ARDWARE

RITE

ROTECT

NPUT

(WP)

The WP pin when LOW prevents non-volatile writes to
the Data Registers.

PRINCIPLES OF OPERATION

The X9251 is an integrated circuit incorporating four
DCPs and their associated registers and counters,
and a serial interface providing direct communication
between a host and the potentiometers.

DCP Description
Each DCP is implemented with a combination of
resistor elements and CMOS switches. The physical
ends of each DCP are equivalent to the fixed terminals
of a mechanical potentiometer (R

and R

pins). The

RW pin is an intermediate node, equivalent to the
wiper terminal of a mechanical potentiometer.

The position of the wiper terminal within the DCP is
controlled by an 8-bit volatile Wiper Counter Register
(WCR).

X9251

FN8166.2

September 14, 2005

Figure 1. Detailed Potentiometer Block Diagram

Power Up and Down Recommendations.
There are no restrictions on the power-up or power-
down conditions of V

and the voltages applied to

the potentiometer pins provided that V

is always

more positive than or equal to V

, V

, and V

, i.e.,

, V

. The V

ramp rate specification is

always in effect.

Wiper Counter Register (WCR)
The X9251 contains four Wiper Counter Registers,
one for each potentiometer. The Wiper Counter
Register can be envisioned as a 8-bit parallel and
serial load counter with its outputs decoded to select
one of 256 wiper positions along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction (See Instruction section for more details).
Finally, it is loaded with the contents of its Data
Register zero (DR#0) upon power-up. (See Figure 1.)

The wiper counter register is a volatile register; that is,
its contents are lost when the X9251 is powered-down.
Although the register is automatically loaded with the
value in DR#0 upon power-up, this may be different

from the value present at power-down. Power-up
guidelines are recommended to ensure proper
loadings of the DR#0 value into the WCR#.

Data Registers (DR)
Each of the four DCPs has four 8-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a non-volatile operation and takes a
maximum of 10ms.

If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.

Bits [7:0] are used to store one of the 256 wiper
positions or data (0~255).

Status Register (SR)
This 1-bit Status Register is used to store the system
status.

WIP: Write In Progress status bit, read only.

When WIP=1, indicates that high-voltage write cycle

is in progress.

When WIP=0, indicates that no high-voltage write

cycle is in progress.

SERIAL DATA PATH

FROM INTERFACE

CIRCUITRY

DR#0

SERIAL

BUS
INPUT

PARALLEL

BUS
INPUT

COUNTER

REGISTER

INC/DEC

LOGIC

UP/DN

CLK

MODIFIED SCK

UP/DN

COUNTER

IF WCR = 00[H] then R

is closet to R

IF WCR = FF[H] then R

is closet to R

WIPER

(WCR#)

#: 0, 1, 2, or 3

One of Four Potentiometers

DR#2

DR#1

DR#3

- - -

DECODE

DCP

CORE

X9251

FN8166.2

September 14, 2005

Table 1. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile).

Table 2. Data Register, DR (8-bit), DR[7:0]: Used to store wiper positions or data (Non-volatile).

SERIAL INTERFACE

The X9251 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in, on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.

The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.

DENTIFICATION

YTE

The first byte sent to the X9251 from the host,
following a CS going HIGH to LOW, is called the
Identification Byte. The most significant four bits of the
Identification Byte are a Device Type Identifier, ID[3:0].
For the X9251, this is fixed as 0101 (refer to Table 3).

The least significant four bits of the Identification Byte
are the Slave Address bits, AD[3:0]. For the X9251, A3
is 0, A2 is 0, A1 is the logic value at the input pin A1,
and A0 is the logic value at the input pin A0. Only the
device which Slave Address matches the incoming
bits sent by the master executes the instruction. The
A1 and A0 inputs can be actively driven by CMOS
input signals or tied to V

or V

NSTRUCTION

YTE

The next byte sent to the X9251 contains the instruction
and register pointer information. The four most significant
bits are used provide the instruction opcode (I[3:0]). The
RB and RA bits point to one of the four Data Registers of
each associated XDCP. The least two significant bits
point to one of four Wiper Counter Registers or
DCPs.The format is shown below in Table 4.

Table 3. Identification Byte Format

Table 4. Instruction Byte Format

WCR7

WCR6

WCR5

WCR4

WCR3

WCR2

WCR1

WCR0

(MSB)

(LSB)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(MSB)

(LSB)

ID3

ID2

ID1

ID0

Pin A1

Logic Value

Pin A0

Logic Value

(MSB)

(LSB)

Device Type

Identifier

Slave Address

(MSB)

(LSB)

Instruction

DCP Selection

Opcode

Selection

(WCR Selection)

X9251

FN8166.2

September 14, 2005

Data Register Selection

#: 0, 1, 2, or 3

Table 5. Instruction Set

Note:

1/0 = data is one or zero

Register

DR#0

DR#1

DR#2

DR#3

Instruction

Instruction Set

Operation

RB RA

Read Wiper Counter

1/0

1/0 Read the contents of the Wiper Counter

Write Wiper Counter

1/0

1/0 Write new value to the Wiper Counter

Read Data Register

1/0

1/0 Read the contents of the Data Register

pointed to by P1 - P0 and RB - RA

Write Data Register

1/0

1/0 Write new value to the Data Register

pointed to by P1 - P0 and RB - RA

XFR Data Register to

Wiper Counter Register

1/0

1/0 Transfer the contents of the Data Register

pointed to by P1 - P0 and RB - RA to its

associated Wiper Counter Register

XFR Wiper Counter

1/0

1/0 Transfer the contents of the Wiper Counter

Global XFR Data Registers

to Wiper Counter Registers

1/0

Transfer the contents of the Data Registers

pointed to by RB - RA of all four pots to their

respective Wiper Counter Registers

Global XFR Wiper Counter

Registers to Data Register

1/0

Transfer the contents of both Wiper Counter

Registers to their respective data Registers

pointed to by RB - RA of all four pots

Increment/Decrement

Wiper Counter Register

1/0

1/0 Enable Increment/decrement of the Control

Latch pointed to by P1 - P0

X9251

FN8166.2

September 14, 2005

Instructions
Four of the nine instructions are three bytes in length.
These instructions are:

Read Wiper Counter Register read the current

wiper position of the selected potentiometer,

Write Wiper Counter Register change current

wiper position of the selected potentiometer,

Read Data Register read the contents of the

selected Data Register,

Write Data Register write a new value to the

selected Data Register,

Read Status this command returns the contents

of the WIP bit which indicates if the internal write
cycle is in progress.

The basic sequence of the three byte instructions is
illustrated in Figure 3. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action is delayed by t

WRL

. A transfer from

the WCR (current wiper position), to a Data Register is
a write to non-volatile memory and takes a minimum of
t

to complete. The transfer can occur between one

of the four potentiometer's WCR, and one of its
associated registers, DRs; or it may occur globally,
where the transfer occurs between all potentiometers
and one associated register. The Read Status
Register instruction is the only unique format (See
Figure 5).

Four instructions require a two-byte sequence to
complete. These instructions transfer data between
the host and the X9251; either between the host and
one of the data registers or directly between the host
and the Wiper Counter Register. These instructions
are:

XFR Data Register to Wiper Counter Register

This transfers the contents of one specified Data
Register to the associated Wiper Counter Register.

XFR Wiper Counter Register to Data Register

This transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.

Global XFR Data Register to Wiper Counter

Register This transfers the contents of all speci-
fied Data Registers to the associated Wiper Counter
Registers.

Global XFR Wiper Counter Register to Data

Register This transfers the contents of all Wiper
Counter Registers to the specified associated Data
Registers.

INCREMENT/DECREMENT COMMAND

The final command is Increment/Decrement (See
Figures 6 and 7). The Increment/Decrement command
is different from the other commands. Once the
command is issued and the X9251 has responded
with an Acknowledge, the master can clock the
selected wiper up and/or down in one segment steps;
thereby, providing a fine tuning capability to the host.
For each SCK clock pulse (t

HIGH

) while SI is HIGH,

the selected wiper moves one wiper position towards
the R

terminal. Similarly, for each SCK clock pulse

while SI is LOW, the selected wiper moves one wiper
position towards the R

terminal. A detailed illustration

of the sequence and timing for this operation are
shown. See Instruction format for more details.

X9251

FN8166.2

September 14, 2005

Figure 2. Two-Byte Instruction Sequence

Figure 3. Three-Byte Instruction Sequence SPI Interface; Write Case

Figure 4. Three-Byte Instruction Sequence SPI Interface, Read Case

ID3 ID2 ID1 ID0

A1 A0

RB RA

SCK

Device ID

Internal

Instruction

Opcode

Address

DCP/WCR

Address

A1 A0

I3 I2

RB RA

SCK

D7 D6 D5 D4 D3 D2 D1 D0

ID3 ID2 ID1 ID0

Device ID

Internal

Instruction

Opcode

Address

DCP/WCR

Address

Data for WCR[7:0] or DR[7:0]

A1 A0

I1 I0

RB RA

SCK

D7 D6 D5 D4 D3 D2 D1 D0

ID3 ID2 ID1 ID0

Device ID

Internal

Instruction

Opcode

Address

DCP/WCR

Address

WCR[7:0]

Don't Care

Data Register Bit [7:0]

X9251

FN8166.2

September 14, 2005

Figure 5. Three-Byte Instruction Sequence (Read Status Register

Figure 6. Increment/Decrement Instruction Sequence

Figure 7. Increment/Decrement Timing Spec

WIP

Status

Bit

A1 A0

I1 I0

RB RA

SCK

ID3 ID2 ID1 ID0

Device ID

Internal

Instruction

Opcode

Address

Pot/WCR
Address

A1 A0

I1 I0

RB RA

SCK

ID3 ID2 ID1 ID0

Device ID

Internal

Instruction

Opcode

Address

Pot/WCR

Address

SCK

INC/DEC CMD ISSUED

tWRID

VOLTAGE OUT

X9251

FN8166.2

September 14, 2005

INSTRUCTION FORMAT

Read Wiper Counter Register (WCR)

Write Wiper Counter Register (WCR)

Read Data Register (DR)

Write Data Register (DR)

Global Transfer Data Register (DR) to Wiper Counter Register (WCR)

Notes: (1) "A1 ~ A0": stands for the device addresses sent by the master.

(2) WPx refers to wiper position data in the Counter Register
(2) "I": stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) "D": stands for the decrement operation, SI held LOW during active SCK phase (high).

Falling

Edge

Device Type

Identifier

Device

Addresses

Instruction

Opcode

WCR

Addresses

Wiper Position

(Sent by X9251 on SO)

Rising

Edge

0 1 0 1 0 0 A1 A0 1 0 0 1 0 0 0 0

Falling

Edge

Device Type

Identifier

Device

Addresses

Instruction

Opcode

WCR

Addresses

Data Byte

(Sent by Host on SI)

Rising

Edge

0 1 0 1 0 0 A1 A0 1 0 1 0 0 0 0 0

Falling

Edge

Device Type

Identifier

Device

Addresses

Instruction

Opcode

DR and WCR

Addresses

Data Byte

(Sent by X9271 on SO)

Rising

Edge

0 1 0 1 0 0 A1 A0 1 0 1 1 RB RA P1 P0

Falling

Edge

Device Type

Identifier

Device

Addresses

Instruction

Opcode

DR and WCR

Addresses

Data Byte

(Sent by Host on SI)

Rising

Edge

HIGH-VOLTAGE

ITE CYC

L
E

0 1 0 1 0 0 A1 A0 1 1 0 0 RB RA P1 P0

Falling

Edge

Device Type

Identifier

Device

Addresses

Instruction

Opcode

Addresses

Rising

Edge

0 1 0 1 0 0 A1 A0 0 0 0 1 RB RA 0 0

X9251

FN8166.2

September 14, 2005

Global Transfer Wiper Counter Register (WCR) to Data Register (DR)

Transfer Wiper Counter Register (WCR) to Data Register (DR)

Transfer Data Register (DR) to Wiper Counter Register (WCR)

Increment/Decrement Wiper Counter Register (WCR)

Read Status Register (SR)

Notes: (1) "A1 ~ A0": stands for the device addresses sent by the master.

Falling

Edge

Device Type

Identifier

Device

Addresses

Instruction

Opcode

Addresses

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

0 1 0 1 0 0 A1 A0 1 0 0 0 RB RA 0 0

Falling

Edge

Device Type

Identifier

Device

Addresses

Instruction

Opcode

DR and WCR

Addresses

Rising

Edge

HIGH-VOLTAGE

WRITE CYCLE

0 1 0 1 0 0 A1 A0 1 1 1 0 RB RA 0 0

Falling

Edge

Device Type

Identifier

Device

Addresses

Instruction

Opcode

DR and WCR

Addresses

Rising

Edge

0 1 0 1 0 0 A1 A0 1 1 0 1 RB RA 0

Falling

Edge

Device Type

Identifier

Device

Addresses

Instruction

Opcode

WCR

Addresses

Increment/Decrement

(Sent by Master on SI)

Rising

Edge

0 1 0 1 0 0 A1 A0 0 0 1 0 X X 0 0 I/D I/D .

. I/D I/D

Falling

Edge

Device Type

Identifier

Device

Addresses

Instruction

Opcode

WCR

Addresses

Data Byte

(Sent by X9251 on SO)

Rising

Edge

0 1 0 1 0 0 A1 A0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 WIP

X9251

FN8166.2

September 14, 2005

ABSOLUTE MAXIMUM RATINGS

Temperature under bias .................... -65

C to +135

Storage temperature ......................... -65

C to +150

Voltage on SCK, any address input, V

with respect to V

................................. -1V to +7V

V = | (V

- VL) |................................................... 5.5V

Lead temperature (soldering, 10s) .................... 300

(10s) ..............................................................±6mA

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.

ANALOG CHARACTERISTICS

(Over recommended industrial operating conditions unless otherwise stated.)

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

potentiometer.

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a

potentiometer. It is a measure of the error in step size.

(3) MI = RTOT / 255 or (R

- R

) / 255, single pot

(4) During power up V

> V

, V

, and V

(5) n = 0, 1, 2, ...,255; m =0, 1, 2, ..., 254.

Symbol

Parameter

Limits

Test Conditions

Min.

Typ.

Max.

Units

TOTAL

End to End Resistance

100

T version

TOTAL

End to End Resistance

U version

End to End Resistance Tolerance

±20

Power Rating

C, each pot

Wiper Current

±3

Wiper Resistance

300

@ V

= 3V

150

@ V

= 5V

TERM

Voltage on any R

or R

= 0V

Noise

-120

dBV

Hz Ref: 1V

Resolution

0.4

Absolute Linearity

(1)

-1

(3)

w(n)(actual)

- R

w(n)(expected)

(5)

Relative Linearity

(2)

-0.6

+0.6

(3)

w(n + 1)

- [R

w(n) + MI

]

(5)

Temperature Coefficient of R

TOTAL

300

ppm/

Ratiometric Temp. Coefficient

-20

+20

ppm/°C

Potentiometer Capacitances

10/10/25

See Macro model

RECOMMENDED OPERATING CONDITIONS

Temp

Min.

Max.

Commercial

+70

Industrial

-40

+85

Device

Supply Voltage (V

) Limits

(4)

X9251

10%

X9251-2.7

2.7V to 5.5V

V(V

)

TOTAL

V(V

)

TOTAL

X9251

FN8166.2

September 14, 2005

D.C. OPERATING CHARACTERISTICS

(Over the recommended operating conditions unless otherwise specified.)

ENDURANCE AND DATA RETENTION

CAPACITANCE

POWER-UP TIMING

A.C. TEST CONDITIONS

Notes: (6) This parameter is not 100% tested

(7) t

PUR

and t

PUW

are the delays required from the time the (last) power supply (V

-) is stable until the specific instruction can be issued.

These parameters are periodically sampled and not 100% tested.

Symbol

Parameter

Limits

Test Conditions

Min.

Typ.

Max.

Units

CC1

supply current

(active)

400

SCK

= 2.5 MHz, SO = Open, V

= 6V

Other Inputs = V

CC2

supply current

(non-volatile write)

SCK

= 2.5MHz, SO = Open, V

= 6V

Other Inputs = V

current (standby)

SCK = SI = V

, Addr. = V

CS = V

= 6V

Input leakage current

= V

to V

Output leakage current

OUT

= V

to V

Input HIGH voltage

x 0.7

+ 1

Input LOW voltage

-1

x 0.3

Output LOW voltage

0.4

= 3mA

Output HIGH voltage

- 0.8

= -1mA, V

+3V

Output HIGH voltage

- 0.4

= -0.4mA, V

+3V

Parameter

Min.

Units

Minimum endurance

100,000

Data changes per bit per register

Data retention

100

years

Symbol

Test

Max.

Units

Test Conditions

IN/OUT

)

Input / Output capacitance (SI)

OUT

= 0V

OUT

(6)

Output capacitance (SO)

OUT

= 0V

(6)

Input capacitance (A0, A1, CS, WP, HOLD, and SCK)

= 0V

Symbol

Parameter

Min.

Max.

Units

(6)

Power-up rate

0.2

V/ms

PUR

(7)

Power-up to initiation of read operation

PUW

(7)

Power-up to initiation of write operation

Input Pulse Levels

x 0.1 to V

x 0.9

Input rise and fall times

10ns

Input and output timing level

x 0.5

X9251

FN8166.2

September 14, 2005

EQUIVALENT A.C. LOAD CIRCUIT

AC TIMING

Symbol

Parameter

Min.

Max.

Units

SCK

SPI clock frequency

MHz

CYC

SPI clock cycle rime

500

SPI clock high rime

200

SPI clock low time

200

LEAD

Lead time

250

LAG

Lag time

250

SI, SCK, HOLD and CS input setup time

SI, SCK, HOLD and CS input hold time

SI, SCK, HOLD and CS input rise time

SI, SCK, HOLD and CS input fall time

DIS

SO output disable time

250

SO output valid time

200

SO output hold time

SO output rise time

100

SO output fall time

100

HOLD

HOLD time

400

HSU

HOLD setup time

100

HOLD hold time

100

HOLD low to output in high Z

100

HOLD high to output in low Z

100

Noise suppression time constant at SI, SCK, HOLD and CS inputs

CS deselect time

WPASU

WP, A0 setup time

WPAH

WP, A0 hold time

10pF

TOTAL

25pF

10pF

SPICE Macromodel

10pF

SO pin

X9251

FN8166.2

September 14, 2005

HIGH-VOLTAGE WRITE CYCLE TIMING

XDCP TIMING

SYMBOL TABLE

Symbol

Parameter

Typ.

Max.

Units

High-voltage write cycle time (store instructions)

Symbol

Parameter

Min. Max. Units

WRPO

Wiper response time after the third (last) power supply is stable

WRL

Wiper response time after instruction issued (all load instructions)

WAVEFORM

INPUTS

OUTPUTS

Must be

steady

Will be

steady

May change

from Low to

High

Will change

from Low to

High

May change

from High to

Low

Will change

from High to

Low

Don't Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance

X9251

FN8166.2

September 14, 2005

APPLICATIONS INFORMATION

Basic Configurations of Electronic Potentiometers

Application Circuits

Three terminal Potentiometer;

Variable voltage divider

Two terminal Variable Resistor;

Variable current

Noninverting Amplifier

Voltage Regulator

Offset Voltage Adjustment

Comparator with Hysterisis

= (1+R

adj

(REG) = 1.25V (1+R

)+I

adj

(REG)

317

= {R

/(R

)} V

(max)

= {R

/(R

)} V

(min)

100k

10k

-12V

+12V

TL072

}

X9251

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8166.2

September 14, 2005

PACKAGING INFORMATION

0.290 (7.37)
0.299 (7.60)

0.393 (10.00)
0.420 (10.65)

0.014 (0.35)
0.020 (0.50)

Pin 1

Pin 1 Index

0.050 (1.27)

0.598 (15.20)
0.610 (15.49)

0.003 (0.10)
0.012 (0.30)

0.092 (2.35)
0.105 (2.65)

(4X) 7°

24-Lead Plastic, SOIC, Package Code S24

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

0.420"

0.050" Typical

0.050"

Typical

0.030" Typical

24 Places

FOOTPRINT

0.010 (0.25)
0.020 (0.50)

0.015 (0.40)
0.050 (1.27)

0.009 (0.22)
0.013 (0.33)

0° - 8°

X 45°

X9251

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X9251US24