FN8173.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-352-6832

Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X9269

Single Supply/Low Power/256-Tap/2-Wire Bus

Dual Digitally-Controlled (XDCPTM)

Potentiometers

FEATURES

· DualTwo separate potentiometers
· 256 resistor taps/pot0.4% resolution
· 2-Wire Serial Interface for write, read, and

transfer operations of the potentiometer single
supply device

Wiper Resistance, 100

typical V

= 5V

· 4 Nonvolatile Data Registers for Each

Potentiometer

· Nonvolatile Storage of Multiple Wiper Positions
· Power-on Recall. Loads Saved Wiper Position on

Power-up.

· Standby Current < 5µA Max
· 50k

, 100k

versions of End to End Pot

Resistance

· 100 yr. Data Retention
· Endurance: 100,000 Data Changes per Bit per

Register

· 24-Lead SOIC, 24-Lead TSSOP
· Low Power CMOS
· Power Supply V

= 2.7V to 5.5V

DESCRIPTION

The X9269 integrates 2 digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.

The digital controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
2-Wire bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and a four nonvolatile Data Registers that can
be directly written to and read by the user. The
contents of the WCR controls the position of the wiper
on the resistor array though the switches. Powerup
recalls the contents of the default Data Register (DR0)
to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

FUNCTIONAL DIAGRAM

2-Wire

Bus

50k

or 100k

versions

Power-on Recall

Wiper Counter

Registers (WCR)

Data Registers

(DR0DR3)

Interface

Bus

Interface

and Control

Address

Data

Status

Write
Read

Transfer

Inc/Dec

Control

Data Sheet

March 28, 2005

FN8173.1

March 28, 2005

DETAILED FUNCTIONAL DIAGRAM

CIRCUIT LEVEL APPLICATIONS

· Vary the gain of a voltage amplifier

· Provide programmable dc reference voltages for

comparators and detectors

· Control the volume in audio circuits

· Trim out the offset voltage error in a voltage

amplifier circuit

· Set the output voltage of a voltage regulator

· Trim the resistance in Wheatstone bridge circuits

· Control the gain, characteristic frequency and

Q-factor in filter circuits

· Set the scale factor and zero point in sensor signal

conditioning circuits

· Vary the frequency and duty cycle of timer ICs

· Vary the dc biasing of a pin diode attenuator in RF

circuits

· Provide a control variable (I, V, or R) in feedback

circuits

SYSTEM LEVEL APPLICATIONS

· Adjust the contrast in LCD displays

· Control the power level of LED transmitters in

communication systems

· Set and regulate the DC biasing point in an RF

power amplifier in wireless systems

· Control the gain in audio and home entertainment

systems

· Provide the variable DC bias for tuners in RF

wireless systems

· Set the operating points in temperature control

systems

· Control the operating point for sensors in industrial

systems

· Trim offset and gain errors in artificial intelligent

systems

INTERFACE

AND

CONTROL

CIRCUITRY

SCL

SDA

Wiper

Counter

(WCR)

Resistor

Array
Pot 1

Wiper

Counter

(WCR)

Data

Pot 0

Power-on

Recall

Power-on

Recall

256-taps

50k

and 100k

X9269

FN8173.1

March 28, 2005

PIN CONFIGURATION

PIN ASSIGNMENTS

SCL

SOIC/TSSOP

X9269

SDA

Pin

(SOIC/TSSOP)

Symbol

Function

No Connect

Device Address for 2-Wire bus.

No Connect

System Supply Voltage

Low Terminal for Potentiometer 0.

High Terminal for Potentiometer 0.

Wiper Terminal for Potentiometer 0.

Device Address for 2-Wire bus.

Hardware Write Protect

SDA

Serial Data Input/Output for 2-Wire bus.

Device Address for 2-Wire bus.

Low Terminal for Potentiometer 1.

High Terminal for Potentiometer 1.

Wiper Terminal for Potentiometer 1.

System Ground

No Connect

SCL

Serial Clock for 2-Wire bus.

Device Address for 2-Wire bus.

X9269

FN8173.1

March 28, 2005

PIN DESCRIPTIONS

Bus Interface Pins

ERIAL

ATA

NPUT

UTPUT

(SDA)

The SDA is a bidirectional serial data input/output pin
for a 2-Wire slave device and is used to transfer data
into and out of the device. It receives device address,
opcode, wiper register address and data sent from an
2-Wire master at the rising edge of the serial clock
SCL, and it shifts out data after each falling edge of the
serial clock SCL.

It is an open drain output and may be wire-ORed with
any number of open drain or open collector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the
guidelines for calculating typical values on the bus
pull-up resistors graph.

ERIAL

LOCK

(SCL)

This input is used by 2-Wire master to supply 2-Wire
serial clock to the X9269.

EVICE

DDRESS

(A3 - A0)

The address inputs are used to set the least significant
4 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
Address input in order to initiate communication with
the X9269. A maximum of 16 devices may occupy the
2-Wire serial bus.

Potentiometer Pins

, R

The R

and R

pins are equivalent to the terminal

connections on a mechanical potentiometer. Since
there are 2 potentiometers, there are 2 sets of R

and

such that R

and R

are the terminals of POT 0

and so on.

The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are 4
potentiometers, there are 2 sets of R

such that R

is the terminal of POT 0 and so on.

Bias Supply Pins

YSTEM

UPPLY

OLTAGE

)

AND

UPPLY

ROUND

)

The V

pin is the system supply voltage. The V

pin is the system ground.

Other Pins

ONNECT

No connect pins should be left open. This pins are
used for Intersil manufacturing and testing purposes.

ARDWARE

RITE

ROTECT

NPUT

(WP)

The WP pin when LOW prevents nonvolatile writes to
the Data Registers.

X9269

FN8173.1

March 28, 2005

PRINCIPLES OF OPERATION

The X9269 is a integrated microcircuit incorporating
four resistor arrays and their associated registers and
counters and the serial interface logic providing direct
communication between the host and the digitally
controlled potentiometers. This section provides detail
description of the following:

Resistor Array Description

Serial Interface Description

Instruction and Register Description.

Array Description

The X9269 is comprised of a resistor array (See Figure
1). Each array contains 255 discrete resistive segments
that are connected in series. The physical ends of each
array are equivalent to the fixed terminals of a
mechanical potentiometer (R

and R

inputs).

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(R

) output. Within each individual array only one

switch may be turned on at a time.

These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256
switches (See Table 1).

The WCR may be written directly. These Data
Registers can the WCR can be read and written by the
host system.

Power-up and Down Requirements.

There are no restrictions on the power-up or power-
down conditions of V

and the voltages applied to

the potentiometer pins provided that V

is always

more positive than or equal to V

, V

, and V

, i.e.,

, V

. The V

ramp rate specification is

always in effect.

Figure 1. Detailed Potentiometer Block Diagram

SERIAL DATA PATH

FROM INTERFACE

CIRCUITRY

SERIAL
BUS
INPUT

PARALLEL
BUS
INPUT

COUNTER

REGISTER

INC/DEC

LOGIC

UP/DN

CLK

MODIFIED SCL

UP/DN

C
O
U
N
T
E
R

D
E
C
O
D
E

IF WCR = 00[H] THEN R

= R

WCR = FF[H]

THEN

WIPER

(WCR)

One of Two Potentiometers

(DR0)

(DR1)

(DR2)

(DR3)

X9269

FN8173.1

March 28, 2005

SERIAL INTERFACE DESCRIPTION

Serial Interface

The X9269 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9269 will be considered a
slave device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during
SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating start and stop
conditions. See Figure 2.

Start Condition

All commands to the X9269 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The X9269 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition is
met. See Figure 2.

Stop Condition

All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. See Figure 2.

Acknowledge

Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.

The X9269 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9269 will respond with a final acknowledge.
See Figure 2.

Figure 2. Acknowledge Response from Receiver

SCL FROM

MASTER

DATA

OUTPUT

FROM

TRANSMITTER

DATA

OUTPUT

FROM

RECEIVER

START

ACKNOWLEDGE

X9269

FN8173.1

March 28, 2005

Acknowledge Polling

The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9269
initiates the internal write cycle. ACK polling, Flow 1,
can be initiated immediately. This involves issuing the
start condition followed by the device slave address. If
the X9269 is still busy with the write operation no ACK
will be returned. If the X9269 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.

FLOW 1: ACK Polling Sequence

INSTRUCTION AND REGISTER DESCRIPTION

Instructions

EVICE

DDRESSING

: I

DENTIFICATION

YTE

(ID

AND

The first byte sent to the X9269 from the host is called
the Identification Byte. The most significant four bits of
the slave address are a device type identifier. The
ID[3:0] bits is the device id for the X9269; this is fixed
as 0101[B] (refer to Table 1).

The A[3:0] bits in the ID byte is the internal slave
address. The physical device address is defined by
the state of the A3-A0 input pins. The slave address
is externally specified by the user. The X9269
compares the serial data stream with the address
input state; a successful compare of both address
bits is required for the X9269 to successfully continue
the command sequence. Only the device which slave
address matches the incoming device address sent
by the master executes the instruction. The A3 - A0
inputs can be actively driven by CMOS input signals
or tied to V

or V

NSTRUCTION

YTE

(I)

The next byte sent to the X9269 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode I [3:0]. The RB and RA bits point to one of the
four Data Registers of each associated XDCP. The
least significant bit points to one of two Wiper Counter
Registers or Pots. The format is shown in Table 2.

Register Selection

Nonvolatile Write

Command Completed

EnterACK Polling

Issue

START

Issue Slave

Address

ACK

Returned?

Further

Operation?

Issue

Instruction

Issue STOP

Yes

Proceed

Issue STOP

Proceed

Register Selected

DR0

DR1

DR2

DR3

X9269

FN8173.1

March 28, 2005

Table 1. Identification Byte Format

Table 2. Instruction Byte Format

Table 3. Instruction Set

Note: 1/0 = data is one or zero

ID3

ID2

ID1

ID0

(MSB)

(LSB)

Device Type

Identifier

Slave Address

(MSB)

(LSB)

Instruction

Pot Selection

Opcode

Selection

(WCR Selection)

Instruction

Instruction Set

Operation

RB RA

Read Wiper Counter
Register

1/0

Read the contents of the Wiper Counter
Register pointed to by P0

Write Wiper Counter Register

1/0

Write new value to the Wiper Counter
Register pointed to by P0

Read Data Register

1/0

Read the contents of the Data Register
pointed to by P0 and RB - RA

Write Data Register

1/0

Write new value to the Data Register
pointed to by P0 and RB - RA

XFR Data Register to Wiper
Counter Register

1/0

Transfer the contents of the Data Register
pointed to by P0 and RB - RA to its
associated Wiper Counter Register

XFR Wiper Counter Register
to Data Register

1/0

Transfer the contents of the Wiper Counter
Register pointed to by P0 to the Data
Register pointed to by RB - RA

Global XFR Data Registers to
Wiper Counter Registers

1/0

Transfer the contents of the Data Registers
pointed to by RB - RA of all four pots to their
respective Wiper Counter Registers

Global XFR Wiper Counter
Registers to Data Register

1/0

Transfer the contents of both Wiper Counter
Registers to their respective data Registers
pointed to by RB - RA of all four pots

Increment/Decrement Wiper
Counter Register

1/0

Enable Increment/decrement of the Control
Latch pointed to by P0

X9269

FN8173.1

March 28, 2005

DEVICE DESCRIPTION

Wiper Counter Register (WCR)

The X9269 contains two Wiper Counter Registers, one
for each DCP potentiometer. The Wiper Counter
Register can be envisioned as a 8-bit parallel and
serial load counter with its outputs decoded to select
one of 256 switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction (See Instruction section for more details).
Finally, it is loaded with the contents of its Data
Register zero (DR0) upon power-up.

The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9269 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be

different from the value present at power-down.
Power-up guidelines are recommended to ensure
proper loadings of the DR0 value into the WCR (See
Design Considerations Section).

Data Registers (DR)

Each potentiometer has four 8-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
data registers is a nonvolatile operation and will take a
maximum of 10ms.

If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.

Bit [7:0] are used to store one of the 256 wiper
positions (0~255).

Table 4. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V).

Table 5. Data Register, DR (8-bit), Bit [7:0]: Used to store wiper positions or data (Nonvolatile, NV).

WCR7

WCR6

WCR5

WCR4

WCR3

WCR2

WCR1

WCR0

(MSB)

(LSB)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MSB

LSB

X9269

FN8173.1

March 28, 2005

DEVICE DESCRIPTION

Instructions

Four of the nine instructions are three bytes in length.
These instructions are:

Read Wiper Counter Register read the current

wiper position of the selected potentiometer,

Write Wiper Counter Register change current

wiper position of the selected potentiometer,

Read Data Register read the contents of the

selected Data Register;

Write Data Register write a new value to the

selected Data Register.

The basic sequence of the three byte instructions is
illustrated in Figure 4. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by t

WRL

. A transfer

from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of t

to complete. The transfer can occur

between one of the four potentiometers and one of its
associated registers; or it may occur globally, where
the transfer occurs between all potentiometers and
one associated register.

Four instructions require a two-byte sequence to
complete. These instructions transfer data between the
host and the X9269; either between the host and one of
the data registers or directly between the host and the
Wiper Counter Register. These instructions are:

XFR Data Register to Wiper Counter Register

This transfers the contents of one specified Data
Register to the associated Wiper Counter Register.

XFR Wiper Counter Register to Data Register

This transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.

Global XFR Data Register to Wiper Counter

Register This transfers the contents of all speci-
fied Data Registers to the associated Wiper Counter
Registers.

Global XFR Wiper Counter Register to Data

Register This transfers the contents of all Wiper
Counter Registers to the specified associated Data
Registers.

INCREMENT/DECREMENT COMMAND

The final command is Increment/Decrement (Figure 5
and 6). The Increment/Decrement command is
different from the other commands. Once the
command is issued and the X9269 has responded
with an acknowledge, the master can clock the
selected wiper up and/or down in one segment steps;
thereby, providing a fine tuning capability to the host.
For each SCL clock pulse (t

HIGH

) while SDA is HIGH,

the selected wiper will move one resistor segment
towards the R

terminal. Similarly, for each SCL clock

pulse while SDA is LOW, the selected wiper will move
one resistor segment towards the R

terminal.

See Instruction format for more details.

X9269

FN8173.1

March 28, 2005

Figure 3. Two-Byte Instruction Sequence

Figure 4. Three-Byte Instruction Sequence

Figure 5. Increment/Decrement Instruction Sequence

Figure 6. Increment/Decrement Timing Limits

R
T

RB RA 0

SCL

SDA

S
T

ID3 ID2 ID1 ID0

Device ID

External

Instruction
Opcode

Address

Pot/WCR

Address

RB RA

ID3 ID2 ID1 ID0

Device ID

External

Instruction
Opcode

Address

Pot/WCR

Address

WCR[7:0]

Data Register D[7:0]

R
T

P0 A

SCL

SDA

D6 D5 D4 D3 D2

D1 D0

ID3 ID2 ID1 ID0

Device ID

External

Instruction
Opcode

Address

Pot/WCR

Address

S
T

A
R
T

A1 A0

A
C

RA 0

A
C

SCL

SDA

S
T

D
E

SCL

SDA

INC/DEC

CMD

Issued

Voltage Out

WRID

X9269

FN8173.1

March 28, 2005

INSTRUCTION FORMAT

Read Wiper Counter Register (WCR)

Write Wiper Counter Register (WCR)

Read Data Register (DR)

Write Data Register (DR)

Global XFR Data Register (DR) to Wiper Counter Register (WCR)

A
R

Device Type

Identifier

Device

Addresses

S
A
C
K

Instruction

Opcode

DR/WCR

Addresses

S
A

Wiper Position

(Sent by X9269 on SDA) M

A
C
K

S
T

1 A3 A2 A1 A0

C
R

A
R

Device Type

Identifier

Device

Addresses

S
A
C
K

Instruction

Opcode

DR/WCR

Addresses

S
A

Wiper Position

(Sent by Master on SDA) S

A
C
K

S
T

1 A3 A2 A1 A0

C
R

A
R

Device Type

Identifier

Device

Addresses

S
A
C
K

Instruction

Opcode

DR/WCR

Addresses

S
A
C
K

Wiper Position

(Sent by X9269 on SDA) M

A
C
K

1 A3 A2 A1 A0

1 RB RA

C
R

A
R

Device Type

Identifier

Device

Addresses

S
A

Instruction

Opcode

DR/WCR

Addresses

S
A
C
K

Wiper Position

(Sent by Master on SDA) S

A
C
K

HIG

-VOLTAGE

ITE CYCLE

1 A3 A2 A1 A0

1 1 0 0 RB RA

0 P0

C
R

A
R

Device Type

Identifier

Device

Addresses

S
A
C
K

Instruction

Opcode

DR/WCR

Addresses

S
A

S
T

A3 A2 A1 A0

RB RA

X9269

FN8173.1

March 28, 2005

Global XFR Wiper Counter Register (WCR) to Data Register (DR)

Transfer Wiper Counter Register (WCR) to Data Register (DR)

Transfer Data Register (DR) to Wiper Counter Register (WCR)

Increment/Decrement Wiper Counter Register (WCR)

Notes: (1) "MACK"/"SACK": stands for the acknowledge sent by the master/slave.

(2) "A3 ~ A0": stands for the device addresses sent by the master.
(3) "X": indicates that it is a "0" for testing purpose but physically it is a "don't care" condition.
(4) "I": stands for the increment operation, SDA held high during active SCL phase (high).
(5) "D": stands for the decrement operation, SDA held low during active SCL phase (high).

S
T
A

Device Type

Identifier

Device

Addresses

S
A

Instruction

Opcode

DR/WCR

Addresses

S
A
C
K

HIGH-VOLTAGE

WRITE CYCLE

1 A3 A2 A1 A0

1 0 0 0 RB RA 0

S
T
A
R
T

Device Type

Identifier

Device

Addresses

S
A

Instruction

Opcode

DR/WCR

Addresses

S
A

S
T

HIGH-VOLTAGE

WRITE CYCLE

1 A3 A2 A1 A0

1 0 RB RA

A
R

Device Type

Identifier

Device

Addresses

S
A
C
K

Instruction

Opcode

DR/WCR

Addresses

S
A
C
K

A3 A2 A1 A0

1 1 0 1 RB RA

S
T
A

Device Type

Identifier

Device

Addresses

S
A

Instruction

Opcode

DR/WCR

Addresses

S
A
C
K

Increment/Decrement

(Sent by Master on SDA)

1 A3 A2 A1 A0

0 P0

I/D I/D

X9269

FN8173.1

March 28, 2005

ABSOLUTE MAXIMUM RATINGS

Temperature under bias..................... -65

C to +135

Storage temperature ......................... -65

C to +150

Voltage on SCL, SDA any address input

with respect to V

................................. -1V to +7V

V = | (V

- V

) | ................................................... 5.5V

Lead temperature (soldering, 10 seconds) ........ 300

(10 seconds) .................................................±6mA

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.

POTENTIOMETER CHARACTERISTICS

(Over recommended industrial (2.7V) operating conditions unless otherwise stated.)

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

potentiometer.

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a

potentiometer. It is a measure of the error in step size.

(3) MI = RTOT / 255 or (R

- R

) / 255, single pot

(4) During power-up V

> V

, V

, and V

(5) n = 0, 1, 2, ...,255; m =0, 1, 2, ..., 254.

Symbol

Parameter

Limits

Test Conditions

Min.

Typ.

Max.

Units

TOTAL

End to End Resistance

100

T version

TOTAL

End to End Resistance

U version

End to End Resistance
Tolerance

±20

Power Rating

C, each pot

Wiper Current

±3

Wiper Resistance

300

3mA @ V

= 3V

Wiper Resistance

150

3mA @ V

= 5V

TERM

Voltage on any R

or R

= 0V

Noise

-120

dBV

Ref: 1V

Resolution

0.4

Absolute Linearity

(1)

±1

(3)

w(n)(actual)

- R

w(n)(expected)

(5)

Relative Linearity

(2)

±0.6

(3)

w(n + 1)

- [R

w(n) + MI

]

(5)

Temperature Coefficient of
R

TOTAL

300

ppm/

Ratiometric Temp. Coefficient

ppm/°C

Potentiometer Capacitances

10/10/25

See Macro model

, R

Leakage

0.1

10.0

µA

Device in stand by.
Vin = V

to V

RECOMMENDED OPERATING CONDITIONS

Temp

Min.

Max.

Commercial

+70

Industrial

-40

+85

Device

Supply Voltage (V

)

(4)

Limits

X9261

10%

X9261-2.7

2.7V to 5.5V

X9269

FN8173.1

March 28, 2005

D.C. OPERATING CHARACTERISTICS

(Over the recommended operating conditions unless otherwise specified.)

ENDURANCE AND DATA RETENTION

CAPACITANCE

POWER-UP TIMING

POWER-UP AND DOWN REQUIREMENTS

The are no restrictions on the power-up or power-down conditions of V

and the voltages applied to the poten-

tiometer pins provided that V

is always more positive than or equal to V

, V

, and V

, i.e., V

, V

. The

power-up timing spec is always in effect.

A.C. TEST CONDITIONS

Notes: (6) This parameter is not 100% tested

(7) t

PUR

and t

PUW

are the delays required from the time the (last) power supply (V

-) is stable until the specific instruction can be issued.

These parameters are periodically sampled and not 100% tested.

Symbol

Parameter

Limits

Test Conditions

Min.

Typ.

Max.

Units

CC1

supply current

(active)

400

µA

SCL

= 400kHz; V

= +6V;

SDA = Open; (for 2-Wire, Active, Read and
Volatile Write States only)

CC2

supply current

(nonvolatile write)

SCL

= 400kHz; V

= +6V;

SDA = Open; (for 2-Wire, Active,
Nonvolatile Write State only)

current (standby)

= +6V; V

= V

or V

; SDA = V

;

(for 2-Wire, Standby State only)

Input leakage current

= V

to V

Output leakage cur-

OUT

= V

to V

Input HIGH voltage

x 0.7

+ 1

Input LOW voltage

-1

x 0.3

Output LOW voltage

0.4

= 3mA

Output HIGH voltage

- 0.8

= -1mA, V

+3V

Output HIGH voltage

- 0.4

= -0.4mA, V

+3V

Parameter

Min.

Units

Minimum endurance

100,000

Data changes per bit per register

Data retention

100

years

Symbol

Test

Max.

Units

Test Conditions

IN/OUT

(6)

Input / Output capacitance (SDA)

OUT

= 0V

(6)

Input capacitance (

SCL, WP, A3, A2, A1 and A0

)

= 0V

Symbol

Parameter

Min.

Max.

Units

(6)

Power-up rate

0.2

V/ms

PUR

(7)

Power-up to initiation of read operation

Input Pulse Levels

x 0.1 to V

x 0.9

Input rise and fall times

10ns

Input and output timing level

x 0.5

X9269

FN8173.1

March 28, 2005

EQUIVALENT A.C. LOAD CIRCUIT

AC TIMING

Symbol

Parameter

Min.

Max.

Units

SCL

Clock Frequency

400

kHz

CYC

Clock Cycle Time

2500

HIGH

Clock High Time

600

LOW

Clock Low Time

1300

SU:STA

Start Setup Time

600

HD:STA

Start Hold Time

600

SU:STO

Stop Setup Time

600

SU:DAT

SDA Data Input Setup Time

100

HD:DAT

SDA Data Input Hold Time

SCL and SDA Rise Time

300

SCL and SDA Fall Time

300

SCL Low to SDA Data Output Valid Time

0.9

SDA Data Output Hold Time

Noise Suppression Time Constant at SCL and SDA inputs

BUF

Bus Free Time (Prior to Any Transmission)

1200

SU:WPA

A0, A1, A2, A3 Setup Time

HD:WPA

A0, A1, A2, A3 Hold Time

1533

100pF

SDA pin

10pF

TOTAL

25pF

10pF

SPICE Macromodel

867

100pF

SDA pin

X9269

FN8173.1

March 28, 2005

HIGH-VOLTAGE WRITE CYCLE TIMING

XDCP TIMING

SYMBOL TABLE

Symbol

Parameter

Typ.

Max.

Units

High-voltage write cycle time (store instructions)

Symbol

Parameter

Min.

Max.

Units

WRPO

Wiper response time after the third (last) power supply is stable

WRL

Wiper response time after instruction issued (all load instructions)

WAVEFORM

INPUTS

OUTPUTS

Must be
steady

Will be
steady

May change
from Low to
High

Will change
from Low to
High

May change
from High to
Low

Will change
from High to
Low

Don't Care:
Changes
Allowed

Changing:
State Not
Known

N/A

Center Line
is High
Impedance

X9269

FN8173.1

March 28, 2005

APPLICATIONS INFORMATION

Basic Configurations of Electronic Potentiometers

Application Circuits

Three terminal Potentiometer;

Variable voltage divider

Two terminal Variable Resistor;

Variable current

Noninverting Amplifier

Voltage Regulator

Offset Voltage Adjustment

Comparator with Hysterisis

= (1+R

adj

(REG) = 1.25V (1+R

)+I

adj

(REG)

317

= {R

/(R

)} V

(max)

= {R

/(R

)} V

(min)

100k

10k

-12V

+12V

TL072

}

10k

X9269

FN8173.1

March 28, 2005

Application Circuits (continued)

Attenuator

Filter

Inverting Amplifier

Equivalent L-R Circuit

= G V

-1/2

+1/2

= 1 + R

fc = 1/(2

RC)

= R

+ s R

+ R

) C

= R

+ s Leq

+ R

) >> R

Function Generator

= R

= 10k

}

= G V

G = - R

}

frequency

, R

, C

amplitude

, R

X9269

FN8173.1

March 28, 2005

PACKAGING INFORMATION

0.290 (7.37)
0.299 (7.60)

0.393 (10.00)

0.420 (10.65)

0.014 (0.35)
0.020 (0.50)

Pin 1

Pin 1 Index

0.050 (1.27)

0.598 (15.20)
0.610 (15.49)

0.003 (0.10)
0.012 (0.30)

0.092 (2.35)
0.105 (2.65)

(4X) 7°

24-Lead Plastic Small Outline Gull Wing Package Type S

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

0.420"

0.050" Typical

0.050"

Typical

0.030" Typical

24 Places

FOOTPRINT

0.010 (0.25)

0.020 (0.50)

0.015 (0.40)
0.050 (1.27)

0.009 (0.22)

0.013 (0.33)

0° - 8°

X 45°

X9269

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8173.1

March 28, 2005

ORDERING INFORMATION

Device

Limits

Blank = 5V

10%

-2.7 = 2.7 to 5.5V

Temperature Range
Blank = Commercial = 0

C to +70

I = Industrial = -40

C to +85

Package
S24 = 24-Lead SOIC
V24 = 24-Lead TSSOP

Potentiometer Organization

Pot

U =

50k

T =

100k

X9269

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X9269US24

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X9269US24