1
FN8212.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X95820
Low Noise/Low Power/2-Wire Bus/256 Taps
Dual Digital Controlled Potentiometers
(XDCPTM)
The X95820 integrates two digitally controlled
potentiometers (XDCP) on a monolithic CMOS integrated
circuit.
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
2-wire bus interface. Each potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR), that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power up the device recalls the contents of the two
DCP's IVR to the corresponding WRs.
The DCPs can be used as three-terminal potentiometers or
as two-terminal variable resistors in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Features
Two potentiometers in one package
256 resistor taps-0.4% resolution
2-wire serial interface
Wiper resistance: 70
typical @ 3.3V
Non-volatile storage of wiper position
Standby current < 5A max
Power supply: 2.7V to 5.5V
50k
, 10k total resistance
High reliability
- Endurance: 150,000 data changes per bit per register
- Register data retention: 50 years @ T
75C
14 Ld TSSOP
Pb-free plus anneal available (RoHS compliant)
Pinouts
X95820
(14 LD TSSOP)
TOP VIEW
Ordering Information
PART NUMBER
PART
MARKING
RESISTANCE
OPTION
PACKAGE
X95820WV14I-2.7*
X95820WV G
10k
14 Ld TSSOP
X95820WV14IZ-2.7*
(See Note)
X95820WV Z G
10k
14 Ld TSSOP
(Pb-free)
X95820UV14I-2.7*
X95820UV G
50k
14 Ld TSSOP
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
A2
1
2
3
4
5
6
7
SDA
SCL
8
9
10
14
13
12
11
WP
RW0
RL0
RH0
A1
V
CC
RW1
RL1
RH1
A0
GND
Data Sheet
September 26, 2005
2
FN8212.1
September 26, 2005
Block Diagram
R
H1
WR1
R
W1
R
L1
R
H0
WR0
R
W0
R
L0
Power-up,
Interface,
Control and
Status Logic
Non-Volatile
Registers
2-wire
Interface
SDA
SCL
A2
A1
A0
WP
GND
V
CC
PiN Descriptions
PIN
SYMBOL
DESCRIPTION
1
V
CC
Power supply pin
2
WP
Hardware write protection pin. Active low. Prevents any "Write" operation of the 2-wire interface.
3
RH0
"High" terminal of DCP0
4
RL0
"Low" terminal of DCP0
5
RW0
"Wiper" terminal of DCP0
6
A2
Device address for the 2-wire interface
7
SCL
2-wire interface clock
8
SDA
Serial data I/O for the 2-wire interface
9
GND
Ground
10
RW1
"Wiper" terminal of DCP1
11
RL1
"Low" terminal of DCP1
12
RH1
"High" terminal of DCP1
13
A0
Device address for the 2-wire interface
14
A1
Device address for the 2-wire interface
X95820
3
FN8212.1
September 26, 2005
Absolute Maximum Ratings
Recommended Operating Conditions
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65
C to +150C
Voltage at any digital interface pin
with respect to GND. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V
CC
+0.3
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
Voltage at any DCP pin with respect to GND. . . . . . . . -0.3V to V
CC
Lead temperature (soldering, 10s). . . . . . . . . . . . . . . . . . . . . . 300
C
I
W
(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA
Temperature Range (Industrial) . . . . . . . . . . . . . . . . . . -40C to 85C
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Power rating of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW
Wiper current of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . .3.0mA
CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Analog Specifications
Over recommended operating conditions unless otherwise stated.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 1)
MAX
UNIT
R
TOTAL
R
H
to R
L
resistance
W, U versions respectively
10, 50
k
R
H
to R
L
resistance tolerance
-20
+20
%
R
W
Wiper resistance
VCC = 3.3V @ 25C
Wiper current = V
CC
/R
TOTAL
70
200
C
H
/C
L
/C
W
Potentiometer Capacitance (Note 15)
10/10/25
pF
I
LkgDCP
Leakage on DCP pins (Note 15)
Voltage at pin from GND to V
CC
0.1
1
A
VOLTAGE DIVIDER MODE (0V @ RL
i
; V
CC
@ RH
i
; measured at RW
i
, unloaded; i = 0 or 1)
INL (Note 6) Integral non-linearity
-1
1
LSB
(Note 2)
DNL (Note 5) Differential non-linearity
Monotonic over all tap positions
-0.5
0.5
LSB
(Note 2)
ZSerror
(Note 3)
Zero-scale error
U option
0
1
7
LSB
(Note 2)
W option
0
0.5
2
FSerror
(Note 4)
Full-scale error
U option
-7
-1
0
LSB
(Note 2)
W option
-2
-1
0
V
MATCH
(Note 7)
DCP to DCP matching
Any two DCPs at same tap position, same
voltage at all RH terminals, and same
voltage at all RL terminals
-2
2
LSB
(Note 2)
TC
V
(Note 8) Ratiometric Temperature Coefficient
DCP Register set to 80 hex
4
ppm/C
RESISTOR MODE (Measurements between RW
i
and RL
i
with RH
i
not connected, or between RW
i
and RH
i
with RL
i
not
connected. i = 0 or 1)
RINL
(Note 12)
Intregal non-linearity
DCP register set between 20 hex and
FF hex. Monotonic over all tap positions
-1
1
MI
(Note 9)
RDNL
(Note 11)
Differential non-linearity
-0.5
0.5
MI
(Note 9)
Roffset
(Note 10)
Offset
DCP Register set to 00 hex, U option
0
1
7
MI
(Note 9)
DCP Register set to 00 hex, W option
0
0.5
2
MI
(Note 9)
R
MATCH
(Note 13)
DCP to DCP Matching
Any two DCPs at the same tap position with
the same terminal voltages.
-2
2
MI
(Note 9)
TC
R
(Note 14)
Resistance Temperature Coefficient
DCP register set between 20 hex and FF
hex
45
ppm/C
X95820
4
FN8212.1
September 26, 2005
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 1)
MAX
UNITS
I
CC1
V
CC
supply current
(Volatile write/read)
f
SCL
= 400kHz;SDA = Open; (for 2-Wire,
Active, Read and Volatile Write States only)
1
mA
I
CC2
V
CC
supply current
(nonvolatile write)
f
SCL
= 400kHz; SDA = Open; (for 2-Wire,
Active, Nonvolatile Write State only)
3
mA
I
SB
V
CC
current (standby)
V
CC
= +5.5V, 2 Wire Interface in Standby State
5
A
V
CC
= +3.6V, 2 Wire Interface in Standby State
2
A
I
LkgDig
Leakage current, at pins A0,
A1, A2, SDA, SCL, and WP
pins
Voltage at pin from GND to V
CC
-10
10
A
t
DCP
(Note 15)
DCP wiper response time
SCL falling edge of last bit of DCP Data Byte to
wiper change
1
s
Vpor
Power-on recall voltage
Minimum V
CC
at which memory recall occurs
1.8
2.6
V
VccRamp
V
CC
ramp rate
0.2
V/ms
t
D
(Note 15)
Power up delay
V
CC
above Vpor, to DCP Initial Value Register recall
completed, and 2-Wire Interface in standby state
3
ms
EEPROM SPECS
EEPROM Endurance
150,000
Cycles
EEPROM Retention
Temperature
75C
50
Years
SERIAL INTERFACE SPECS
V
IL
WP, A2, A1, A0, SDA, and
SCL input buffer LOW
voltage
-0.3
0.3*Vcc
V
V
IH
WP, A2, A1, A0, SDA, and
SCL input buffer HIGH
voltage
0.7*Vcc
Vcc+0.3
V
Hysterisis
(Note 15)
SDA and SCL input buffer
hysterisis
0.05*
Vcc
V
V
OL
(Note 15)
SDA output buffer LOW
voltage, sinking 4mA
0
0.4
V
Cpin
(Note 15)
WP, A2, A1, A0, SDA, and
SCL pin capacitance
10
pF
f
SCL
SCL frequency
400
kHz
t
IN
(Note 15)
Pulse width suppression time
at SDA and SCL inputs
Any pulse narrower than the max spec is
suppressed.
50
ns
t
AA
(Note 15)
SCL falling edge to SDA
output data valid
SCL falling edge crossing 30% of V
CC
, until SDA
exits the 30% to 70% of V
CC
window.
900
ns
t
BUF
(Note 15)
Time the bus must be free
before the start of a new
transmission
SDA crossing 70% of V
CC
during a STOP condition,
to SDA crossing 70% of V
CC
during the following
START condition.
1300
ns
t
LOW
Clock LOW time
Measured at the 30% of V
CC
crossing.
1300
ns
t
HIGH
Clock HIGH time
Measured at the 70% of V
CC
crossing.
600
ns
t
SU:STA
START condition setup time
SCL rising edge to SDA falling edge. Both crossing
70% of V
CC
.
600
ns
t
HD:STA
START condition hold time
From SDA falling edge crossing 30% of V
CC
to SCL
falling edge crossing 70% of V
CC
.
600
ns
X95820
5
FN8212.1
September 26, 2005
SDA vs. SCL Timing
WP, A0, A1, and A2 Pin Timing
t
SU:DAT
Input data setup time
From SDA exiting the 30% to 70% of V
CC
window, to SCL rising edge crossing 30% of V
CC
100
ns
t
HD:DAT
Input data hold time
From SCL rising edge crossing 70% of V
CC
to SDA
entering the 30% to 70% of V
CC
window.
0
ns
t
SU:STO
STOP condition setup time
From SCL rising edge crossing 70% of V
CC
, to SDA
rising edge crossing 30% of V
CC
.
600
ns
t
HD:STO
STOP condition setup time
From SDA rising edge to SCL falling edge. Both
crossing 70% of V
CC
.
600
ns
t
DH
(Note 15) Output data hold time
From SCL falling edge crossing 30% of V
CC
, until
SDA enters the 30% to 70% of V
CC
window.
0
ns
t
R
(Note 15)
SDA and SCL rise time
From 30% to 70% of V
CC
20 +
0.1 * Cb
250
ns
t
F
(Note 15)
SDA and SCL fall time
From 70% to 30% of V
CC
20 +
0.1 * Cb
250
ns
Cb (Note 15) Capacitive loading of SDA or
SCL
Total on-chip and off-chip
10
400
pF
Rpu (Note 15) SDA and SCL bus pull-up
resistor off-chip
Maximum is determined by t
R
and t
F
.
For Cb = 400pF, max is about 2~2.5k
.
For Cb = 40pF, max is about 15~20k
.
1
k
t
WP
(Notes 15, 16)
Non-volatile Write cycle time
12
20
ms
t
SU:WPA
A2, A1, A0, and WP setup
time
Before START condition
600
ns
t
HD:WPA
A2, A1, A0, and WP hold
time
After STOP condition
600
ns
Operating Specifications
Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 1)
MAX
UNITS
t
SU:STO
t
DH
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA
(Input Timing)
SDA
(Output Timing)
t
F
t
LOW
t
BUF
t
AA
t
R
t
HD:WPA
SCL
SDA IN
WP, A0, A1, or A2
t
SU:WPA
Clk 1
START
STOP
X95820
6
FN8212.1
September 26, 2005
NOTES:
1. Typical values are for T
A
= 25C and 3.3V supply voltage.
2. LSB: [V(RW)
255
- V(RW)
0
]
/
255. V(RW)
255
and V(RW)
0
are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
3. ZS error = V(RW)
0
/
LSB.
4. FS error = [V(RW)
255
- V
CC
]
/
LSB.
5. DNL = [V(RW)
i
- V(RW)
i-1
]
/
LSB-1, for i = 1 to 255. i is the DCP register setting.
6. INL = [V(RW)
i
(i LSB V(RW)
0
)]/LSB for i = 1 to 255.
7. V
MATCH
= [V(RWx)
i
- V(RWy)
i
]
/
LSB, for i = 0 to 255, x = 0 to 1 and y = 0 to 1.
8.
for i = 16 to 240 decimal, T = -40C to 85C. Max( ) is the maximum value of the wiper voltage and Min ( ) is the minimum value of the wiper
voltage over the temperature range.
9. MI =
|
R
255
- R
0
|
/
255. R
255
and R
0
are the measured resistances for the DCP register set to FF hex and 00 hex respectively.
10. Roffset = R
0
/
MI, when measuring between RW and RL.
Roffset = R
255
/
MI, when measuring between RW and RH.
11. RDNL = (R
i
- R
i-1
)
/
MI, for i = 32 to 255.
12. RINL = [R
i
- (MI i) - R
0
]
/
MI, for i = 32 to 255.
13. R
MATCH
= (R
i,x
- R
i,y
)
/
MI, for i = 0 to 255, x = 0 to 1 and y = 0 to 1.
14.
for i = 32 to 255, T = -40C to 85C. Max( ) is the maximum value of the resistance and Min ( ) is the minimum value of the resistance over the
temperature range.
15. This parameter is not 100% tested.
16. t
WC
is the minimum cycle time to be allowed for any non-volatile Write by the user, unless Acknowledge Polling is used. It is the time from a
valid STOP condition at the end of a Write sequence of a 2-wire serial interface Write operation, to the end of the self-timed internal non-volatile
write cycle.
TC
V
Max V RW
(
)
i
(
) Min V RW
(
)
i
(
)
Max V RW
(
)
i
(
) Min V RW
(
)
i
(
)
+
[
] 2
/
----------------------------------------------------------------------------------------------
10
6
125C
-----------------
=
TC
R
Max Ri
( ) Min Ri
( )
[
]
Max Ri
( ) Min Ri
( )
+
[
] 2
/
----------------------------------------------------------------
10
6
125C
-----------------
=
Typical Performance Curves
FIGURE 1. WIPER RESISTANCE vs TAP POSITION
[ I(RW) = V
CC
/R
TOTAL
] FOR 50k
(U)
FIGURE 2. STANDBY I
CC
vs V
CC
0
20
40
60
80
100
120
140
160
0
50
100
150
200
250
TAP POSITION (DECIMAL)
WIPER RES
I
STANCE (
)
Vcc = 2.7, T = -40C
Vcc = 2.7, T = 25C
Vcc = 2.7, T = 85C
Vcc = 5.5, T = 85C
Vcc = 5.5, T = 25C
Vcc = 5.5, T = -40C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.7
3.2
3.7
4.2
4.7
5.2
V
CC
(V)
S
T
AN
DBY
I
CC
(A)
-40C
85C
25C
X95820
7
FN8212.1
September 26, 2005
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10k
(W)
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10k
(W)
FIGURE 5. ZSerror vs TEMPERATURE
FIGURE 6. FSerror vs TEMPERATURE
FIGURE 7. DNL vs TAP POSITION IN Rheostat MODE FOR
50k
(U)
FIGURE 8. INL vs TAP POSITION IN Rheostat MODE FOR
50k
(U)
Typical Performance Curves
(Continued)
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0
50
100
150
200
250
TAP POSITION (DECIMAL)
DN
L
(
L
S
B
)
Vcc = 2.7, T = -40C
Vcc = 5.5, T = -40C
Vcc = 2.7, T = 25C
Vcc = 5.5, T = 25C
Vcc = 2.7, T = 85C
Vcc = 5.5, T = 85C
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0
50
100
150
200
250
TAP POSITION (DECIMAL)
INL (L
SB)
Vcc = 5.5, T = -40C
Vcc = 5.5, T = 25C
Vcc = 2.7, T = -40C
Vcc = 2.7, T = 25C
Vcc = 2.7, T = 85C
Vcc = 5.5, T = 85C
0.15
0.2
0.25
0.3
0.35
0.4
-40
-20
0
20
40
60
80
TEMPERATURE (C)
ZSe
r
ror
(LSB)
5.5V
2.7V
-1
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
-40
-20
0
20
40
60
80
TEMPERATURE (C)
FS
e
rro
r (LS
B
)
Vcc = 2.7V
Vcc = 5.5V
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
32
82
132
182
232
TAP POSITION (DECIMAL)
DN
L (LSB)
Vcc = 2.7, T = -40C
Vcc = 5.5, T = -40C
Vcc = 5.5, T = 25C
Vcc = 5.5, T = 85C
Vcc = 2.7, T = 25C
Vcc = 2.7, T = 85C
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
32
82
132
182
232
TAP POSITION (DECIMAL)
INL (
L
SB
)
Vcc = 2.7, T = -40C
Vcc = 2.7, T = 25C
Vcc = 2.7, T = 85C
Vcc = 5.5, T = 25C
Vcc = 5.5, T = -40C
Vcc = 5.5, T = 85C
X95820
8
FN8212.1
September 26, 2005
FIGURE 9. END TO END R
TOTAL
% CHANGE vs
TEMPERATURE
FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm
FIGURE 11. TC FOR Rheostat MODE IN ppm
FIGURE 12. FREQUENCY RESPONSE (2.2MHz)
FIGURE 13. MIDSCALE GLITCH, CODE 80h TO 7Fh (WIPER 0)
FIGURE 14. LARGE SIGNAL SETTLING TIME
Typical Performance Curves
(Continued)
-1.50
-1.00
-0.50
0.00
0.50
1.00
1.50
-40
-20
0
20
40
60
80
TEMPERATURE (C)
END T
O
E
N
D
R
TOTA
L
CHANGE
(%)
5.5V
2.7V
-20
-10
0
10
20
32
82
132
182
232
TAP POSITION (DECIMAL)
TC (ppm
/C)
-25
-15
-5
5
15
25
35
32
57
82
107
132
157
182
207
232
TAP POSITION (DECIMAL)
TC (
p
p
m
/
C)
Tap Position = Mid Point
R
TOTAL
= 9.4K
OUTPUT
INPUT
Wiper Movement Mid Point
From 80h to 7fh
Signal at Wiper (Wiper Unloaded)
SCL
Signal at Wiper
(Wiper Unloaded Movement
From ffh to 00h)
X95820
9
FN8212.1
September 26, 2005
Principles of Operation
The X95820 in as integrated circuit incorporating two DCPs
with their associated registers, non-volatile memory, and a 2-
wire serial interface providing direct communication between
a host and the potentiometers and memory.
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of each DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by an 8-bit
volatile Wiper Register (WR). Each DCP has its own WR.
When the WR of a DCP contains all zeroes (WR<7:0>: 00h),
its wiper terminal (RW) is closest to its "Low" terminal (RL).
When the WR of a DCP contains all ones (WR<7:0>: FFh),
its wiper terminal (RW) is closest to its "High" terminal (RH).
As the value of the WR increases from all zeroes (00h) to all
ones (255 decimal), the wiper moves monotonically from the
position closest to RL to the closest to RH. At the same time,
the resistance between RW and RL increases monotonically,
while the resistance between RH and RW decreases
monotonically.
While the X95820 is being powered up, all two WRs are
reset to 80h (128 decimal), which locates RW roughly at the
center between RL and RH. Soon after the power supply
voltage becomes large enough for reliable non-volatile
memory reading, the X95820 reads the value stored on two
different non-volatile Initial Value Registers (IVRs) and loads
them into their corresponding WRs.
The WRs and IVRs can be read or written directly using the
2-wire serial interface as described in the following sections.
Memory Description
The X95820 contains eight non-volatile bytes. they are
accessed by 2-wire interface operations with Address Bytes
0 through 7 decimal. The first two non-volatile bytes at
addresses 0 and 1 contain the initial value loaded at power-
up into the volatile Wiper Registers (WRs) of DCP0 and
DCP1 respectively. Bytes at addresses 2, 3, 4, 5, and 6 are
available to the user as general purpose registers. The byte
at address 7 is reserved; the user should not write to it, and
its value should be ignored if read.
The volatile WR, and the non-volatile Initial Value Register
(IVR) of a DCP are accessed with the same Address Byte.
A volatile byte at address 8 decimal, controls what byte is
read or written when accessing DCP registers: the WR, the
IVR, or both.
When the byte at address 8 is all zeroes, which is the default
at power up:
A read operation to addresses 0 or 1 outputs the value of
the non-volatile IVRs.
A write operation to addresses 0 or 1 writes the same
value to the WR and IVR of the corresponding DCP.
When the byte at address 8 is 80h (128 decimal):
A read operation to addresses 0 or 1 outputs the value of
the volatile WR.
A write operation to addresses 0 or 1only writes to the
corresponding volatile WR.
It is not possible to write to an IVR without writing the same
value to its corresponding WR.
00h and 80h are the only values that should be written to
address 8. All other values are reserved and must not be
written to address 8.
To access the general purpose bytes at addresses 2, 3, 4, 5,
or 6, the value at address 8 must be all zeros.
The X95820 is pre-programmed with 80h in the two IVRs.
WR: Wiper Register, IVR: Initial value Register.
2-Wire Serial Interface
The X95820 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the X95820
operates as a slave device in all applications.
All communication over the 2-wire interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 15). On power up of the X95820 the SDA pin is in the
input mode.
TABLE 1. MEMORY MAP
ADDRESS
NON-VOLATILE
VOLATILE
8
-
Access Control
7
Reserved
6
5
4
3
2
General Purpose
Not Available
1
0
IVR1
IVR0
WR1
WR0
X95820
10
FN8212.1
September 26, 2005
All 2-wire interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The X95820 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 15). A START condition is ignored during the power
up sequence and during internal non-volatile write cycles.
All 2-wire interface operations must be terminated by a
STOP condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH (See Figure 15). A STOP condition at the
end of a read operation, or at the end of a write operation to
volatile bytes only places the device in its standby mode. A
STOP condition during a write operation to a non-volatile
byte, initiates an internal non-volatile write cycle. The device
enters its standby state when the internal non-volatile write
cycle is completed.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 16).
The X95820 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
X95820 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation
A valid Identification Byte contains 1010 as the four MSBs,
and the following three bits matching the logic values
present at pins A2, A1, and A0. The LSB in the Read/Write
bit. Its value is "1" for a Read operation, and "0" for a Write
operation (See Table 2).
TABLE 2. IDENTIFICATION BYTE FORMAT
1
0
1
0
A2
A1
A0
R/W
(MSB)
(LSB)
Logic values at pins A2, A1, and A0 respectively
SDA
SCL
START
DATA
DATA
STOP
STABLE
CHANGE
DATA
STABLE
FIGURE 15. VALID DATA CHANGES, START, AND STOP CONDITIONS
SDA Output from
Transmitter
SDA Output from
Receiver
8
1
9
START
ACK
SCL from Master
High Impedance
High Impedance
FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER
S
t
a
r
t
S
t
o
p
Identification
Byte
Address
Byte
Data
Byte
A
C
K
Signals from the
Master
Signals from the
X95820
A
C
K
1
0
1
0
0
A
C
K
Write
Signal at SDA
0 0 0 0
A2A1A0
FIGURE 17. BYTE WRITE SEQUENCE
X95820
11
FN8212.1
September 26, 2005
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
X95820 responds with an ACK. At this time, if the Data Byte
is to be written only to volatile registers, then the device
enters its standby state. If the Data Byte is to be written also
to non-volatile memory, the X95820 begins its internal write
cycle to non-volatile memory. During the internal non-volatile
write cycle, the device ignores transitions at the SDA and
SCL pins, and the SDA output is at a high impedance state.
When the internal non-volatile write cycle is completed, the
X95820 enters its standby state (See Figure 17).
The byte at address 00001000 bin (8 decimal) determines if
the Data Byte is to be written to volatile and/or non-volatile
memory. See "Memory Description" on page 9.
Data Protection
The WP pin has to be at logic HIGH to perform any Write
operation to the device. When the WP is active (LOW) the
device ignores Data Bytes of a Write Operation, does not
respond to the Data Bytes with an ACK, and instead, goes to
its standby state waiting for a new START condition.
A STOP condition also acts as a protection of non-volatile
memory. A valid Identification Byte, Address Byte, and total
number of SCL pulses act as a protection of both volatile
and non-volatile registers. During a Write sequence, the
Data Byte is loaded into an internal shift register as it is
received. If the Address Byte is 0, 1, or 8 decimal, the Data
Byte is transferred to the appropriate Wiper Register (WR) or
to the Access Control Register, at the falling edge of the SCL
pulse that loads the last bit (LSB) of the Data Byte. If the
Address Byte is between 0 and 6 (inclusive), and the Access
Control Register is all zeros (default), then the STOP
condition initiates the internal write cycle to non-volatile
memory.
Read Operation
A Read operation consists of a three byte instruction
followed by one or more Data Bytes (See Figure 18). The
master initiates the operation issuing the following
sequence: a START, the Identification byte with the R/W bit
set to "0", an Address Byte, a second START, and a second
Identification byte with the R/W bit set to "1". After each of
the three bytes, the X95820 responds with an ACK. Then the
X95820 transmits Data Bytes as long as the master
responds with an ACK during the SCL cycle following the
eight bit of each byte. The master terminates the read
operation (issuing a STOP condition) following the last bit of
the last Data Byte (See Figure 18).
The Data Bytes are from the memory location indicated by
an internal pointer. This pointer initial value is determined by
the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 01Fh (8 decimal) the
pointer "rolls over" to 00h, and the device continues to output
data for each ACK received.
The byte at address 00001000 bin (8 decimal) determines if
the Data Bytes being read are from volatile or non-volatile
memory. See "Memory Description" on page 9.
Signals
from the
Master
Signals from the
Slave
Signal at SDA
S
t
a
r
t
Identification
Byte
with
R/W=0
Address
Byte
A
C
K
A
C
K
1
0
1
0
0
S
t
o
p
A
C
K
1
1
1
0
0
Identification
Byte
with
R/W=1
A
C
K
S
t
a
r
t
Last Read Data
Byte
First Read Data
Byte
A
C
K
FIGURE 18. READ SEQUENCE
X95820
12
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN8212.1
September 26, 2005
TSSOP Packaging Information
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
14-Lead Plastic, TSSOP, Package Code V14
See Detail "A"
.031 (.80)
.041 (1.05)
.169 (4.3)
.177 (4.5) .252 (6.4) BSC
.025 (.65) BSC
.193 (4.9)
.200 (5.1)
.002 (.05)
.006 (.15)
.041 (1.05)
.0075 (.19)
.0118 (.30)
0 - 8
.010 (.25)
.019 (.50)
.029 (.75)
Gage Plane
Seating Plane
Detail A (20X)
X95820
PDF 
ZIP