1
Data Sheet No. PD60213 revC
IR2114SS/ IR21141SS
IR2214SS/IR22141SS
HALF-BRIDGE GATE DRIVER IC
Features
Floating channel up to +600 or +1200V
Soft
over-current
shutdown
Synchronization signal to synchronize shut down with the other phases
Integrated desaturation detection circuit
Two stage turn on output for di/dt control
Separate pull-up/pull-down output drive pins
Matched
delay
outputs
Under voltage lockout with hysteresis band
Description
The IR2114/21141/2214/IR22141 gate driver family is suited to drive a single
half bridge in power switching applications. The high gate driving capability (2A
source, 3A sink) and the low quiescent current enable bootstrap supply
techniques in medium power systems. These drivers feature full short circuit
protection by means of the power transistor desaturation detection and manages
all the half-bridge faults by turning off smoothly the desaturated transistor
through the dedicated soft shut down pin, therefore preventing over-voltages and
reducing EM emissions. In multi-phase system IR2114/21141/2214/IR22141
drivers communicate using a dedicated local network (SY_FLT and FAULT/SD
signals) to properly manage phase-to-phase short circuits. The system controller
may force shutdown or read device fault state through the 3.3 V compatible
CMOS I/O pin (FAULT/SD). To improve the signal immunity from DC-bus noise,
the control and power ground use dedicated pins enabling low-side emitter
current sensing as well. Undervoltage conditions in floating and low voltage
circuits are managed independently.
Product Summary
V
OFFSET
600V or
1200V max.
IO+/- (typ)
2.0 A / 3.0A
V
OUT
10.4V - 20V
Deadtime matching (max)
75 nsec
Deadtime (typ)
330
nsec
Desat blanking time (typ)
3
sec
DSH, DSL input voltage
threshold (typ)
8.0 V
Soft shutdown time (typ) 9.
25 sec
Package
24-Lead SSOP
Typical connection
DC+
DC-
DC BUS
(1200V)
VCC
LIN
HIN
FAULT/SD
VB
HOP
HON
SSDH
DSH
VS
LOP
LON
SSDL
DSL
COM
VSS
IR
22
14
FLT_CLR
SY_FLT
15 V
uP,
Control
Motor
IR2114/IR21141/IR2214/IR22141
2
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All
voltage parameters are absolute voltages referenced to V
SS
, all currents are defined positive into any lead
The thermal resistance and power dissipation ratings are measured under board mounted and still air
conditions.
Symbol Definition
Min.
Max.
Units
V
S
High side offset voltage
V
B
- 25
V
B
+ 0.3
V
B
High side floating supply voltage
(IR2114 or IR21141)
-0.3 625
(IR2214 or IR22141)
-0.3 1225
V
HO
High side floating output voltage (HOP, HON and SSDH)
V
S
- 0.3
V
B
+ 0.3
V
CC
Low side and logic fixed supply voltage
-0.3
25
COM Power
ground
V
CC
- 25
V
CC
+ 0.3
V
LO
Low side output voltage (LOP, LON and SSDL)
V
COM
-0.3
V
CC
+ 0.3
V
IN
Logic input voltage (HIN, LIN and FLT_CLR)
V
SS
-0.3
V
CC
+ 0.3
V
FLT
FAULT input/output voltage (FAULT/SD and SY_FLT)
V
SS
-0.3
V
CC
+ 0.3
V
DSH
High side DS input voltage
V
S
-3
V
B
+ 0.3
V
DSL
Low side DS input voltage
V
COM
-3
V
CC
+ 0.3
V
dVs/dt
Allowable offset voltage slew rate
--
50
V/ns
P
D
Package power dissipation @ TA +25C
--
1.5
W
Rth
JA
Thermal resistance, junction to ambient
--
65
C/W
T
J
Junction
temperature
-- 125
T
S
Storage
temperature
-55 150
T
L
Lead temperature (soldering, 10 seconds)
--
300
C
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. All voltage parameters
are absolute voltages referenced to V
SS
. The V
S
offset rating is tested with all supplies biased at 15V
differential.
Symbol Definition
Min.
Max.
Units
V
B
High side floating supply voltage (Note 1)
V
S
+ 11.5
V
S
+ 20
(IR2114 or IR21141)
Note 2
600
V
S
High side floating supply offset
voltage
(IR2214 or IR22141)
Note 2
1200
V
HO
High side output voltage (HOP, HON and SSDH)
V
S
V
S
+ 20
V
LO
Low side output voltage (LOP, LON and SSDL)
V
COM
V
CC
V
CC
Low side and logic fixed supply voltage (Note 1)
11.5
20
COM Power
ground
-5
5
V
IN
Logic input voltage (HIN, LIN and FLT_CLR)
V
SS
V
CC
V
FLT
Fault input/output voltage (FAULT/SD and SY_FLT)
V
SS
V
CC
V
DSH
High side DS pin input voltage
V
S
- 2.0
V
B
V
DSL
Low side DS pin input voltage
V
COM
- 2.0
V
CC
V
T
A
Ambient
temperature
-40 125
C
Note 1: While internal circuitry is operational below the indicated supply voltages, the UV lockout disables
the output drivers if the UV thresholds are not reached.
Note 2: Logic operational for V
S
from V
SS
-5V to V
SS
+600V or 1200V. Logic state held for V
S
from V
SS
-5V to
V
SS
-V
BS
. (Please refer to the Design Tip DT97-3 for more details).
IR2114/IR21141/IR2214/IR22141
3
Static Electrical Characteristics
V
CC
= 15 V, V
SS
= COM = 0 V, V
S
= 0 600V or 1200 V and T
A
= 25 C unless otherwise specified.
Pin: V
CC
, V
SS
, V
B
, V
S
Symbol Definition Min Typ Max Units
Test
Conditions
V
CCUV+
Vcc supply undervoltage positive going threshold
9.3 10.2 11.4
V
CCUV-
Vcc supply undervoltage negative going threshold
8.7
9.3 10.3
V
CCUVH
Vcc supply undervoltage lockout hysteresis
-
0.9
-
V
BSUV+
(V
B
-V
S
) supply undervoltage positive going threshold 9.3 10.2 11.4
V
S
=0V, V
S
=600V
or 1200V
V
BSUV-
(V
B
-V
S
) supply undervoltage negative going
threshold
8.7
9.3 10.3
V
S
=0V, V
S
=600V
or 1200V
V
BSUVH
(V
B
-V
S
) supply undervoltage lockout hysteresis
-
0.9
-
V
I
LK
Offset
supply
leakage
current
-
-
50 V
B
= V
S
= 600V or
1200V
I
QBS
Quiescent
V
BS
supply current
-
400 800
A
V
IN
= 0V or 3.3V
I
QCC
Quiescent Vcc supply current
-
0.7 2.5 mA
(No load)
V
CC
/V
B
V
CCUV
/V
BSUV
V
SS
/V
S
comparator
UV
internal
signal
Figure 1: Undervoltage diagram
Pin: HIN, LIN, FLTCLR, FAULT/SD, SY_FLT
Symbol Definition Min
Typ
Max
Units
Test
Conditions
V
IH
Logic "1" input voltage
2.0
-
-
V
IL
Logic "0" input voltage
-
-
0.8
V
IHSS
Logic input hysteresis
0.2
0.4
-
V
V
CC
= V
CCUV-
to
20V
I
IN+
Logic "1" input bias current
-
370
-
A
V
IN
= 3.3V
I
IN-
Logic "0" input bias current
-1
-
0
V
IN
= 0V
R
ON,FLT
FAULT/SD open drain resistance
-
60
-
R
ON,SY
SY_FLT open drain resistance
-
60
-
PW 7 s
HIN/LIN/
FLTCLR
V
SS
schmitt
trigger
10k
internal
signal
Figure 2: HIN, LIN and FLTCLR diagram
IR2114/IR21141/IR2214/IR22141
4
FAULT/SD
SY_FLT
V
SS
schmitt
trigger
R
ON
fault/hold
internal signal
hard/soft shutdown
internal signal
Figure 3: FAULT/SD and SY_FLT diagram
Pin: DSL, DSH
The active bias is present only in IR21141 and IR22141. V
DESAT
, I
DS
and I
DSB
parameters are referenced to
COM and V
S
respectively for DSL and DSH.
Symbol Definition Min Typ Max Units
Test
Conditions
V
DESAT+
High desat input threshold voltage
7.2 8.0 8.8
V
DESAT-
Low desat input threshold voltage
6.3 7.0 7.7
V
DSTH
Desat input voltage hysteresis
-
1.0
-
V
See Fig. 16, 4
I
DS+
High DSH or DSL input bias current
-
21
-
V
DESAT
= V
CC
or V
BS
I
DS-
Low DSH or DSL input bias current
- -160
-
A
V
DESAT
= 0V
I
DSB
DSH or DSL input bias current
-
-20
-
mA
V
DESAT
=
(IR21141 and IR22141 only)
(V
CC
or V
BS
) - 2V
DSL/DSH
V
DESAT
COM/V
S
comparator
100k
700k
V
CC
/V
BS
SSD
internal
signal
active
bias
Figure 4: DSH and DSL diagram.
IR2114/IR21141/IR2214/IR22141
5
Pin: HOP, LOP
Symbol Definition Min Typ Max
Units
Test
Conditions
V
OH
High level output voltage, V
B
V
HOP or
V
cc
V
LOP
-
40
300
mV I
O
= 20mA
I
O1+
Output high first stage short circuit pulsed current
-
2
-
V
HOP/LOP
=0V,
H
IN
or L
IN
= 1,
PW200ns,
resistive load,
see Fig. 8
I
O2+
Output high second stage short circuit pulsed current
- 1 -
A
V
HOP/LOP
=0V,
H
IN
or L
IN
= 1,
400nsPW10s,
resistive load,
see Fig. 8
LOP/HOP
V
CC
/V
B
on/off
internal signal
V
OH
200ns
oneshot
Figure 5: HOP and LOP diagram
Pin: HON, LON, SSDH, SSDL
Symbol Definition Min Typ Max
Units
Test
Conditions
V
OL
Low level output voltage, V
HON or
V
LON
-
45
300
mV I
O
= 20mA
R
ON,SSD
Soft Shutdown on resistance (Note 1)
-
90
-
PW 7 s
I
O-
Output low short circuit pulsed current
-
3
-
A
V
HOP/LOP
=15V,
H
IN
or L
IN
= 0,
PW10s
Note 1: SSD operation only.
SSDL/SSDH
COM/V
S
on/off
internal signal
R
ON,SSD
LON/HON
desat
internal signal
V
OL
Figure 6: HON, LON, SSDH and SSDL diagram
IR2114/IR21141/IR2214/IR22141
6
AC Electrical Characteristics
V
CC
= V
BS
= 15V, V
S
= V
SS
and T
A
= 25C unless otherwise specified.
Symbol Definition Min. Typ. Max. Units
Test
Conditions
ton
Turn on propagation delay
220 440 660
V
IN
= 0 & 1
toff
Turn off propagation delay
220 440 660
V
S
= 0 to 600V or
1200V
tr
Turn on rise time (C
LOAD
=1nF) --
24
--
HOP
shorted
to
HON,
LOP shorted to LON,
tf
Turn off fall time (C
LOAD
=1nF) --
7
--
Figure
7
ton1
Turn on first stage duration time
120 200 280
Figure 8
t
DESAT1
DSH to HO soft shutdown propagation delay at HO 2000 3300 4600
turn
on
V
HIN
= 1
t
DESAT2
DSH to HO soft shutdown propagation delay after 1050 --
--
V
DESAT
= 15V,Fig.10
Blanking
t
DESAT3
DSL to LO soft shutdown propagation delay at LO 2000 3300 4600
turn
on
V
LIN
= 1
t
DESAT4
DSL to LO soft shutdown propagation delay after
1050 --
--
V
DESAT
= 15V,Fig.10
Blanking
t
DS
Soft shutdown minimum pulse width of desat
1000 --
--
Figure 9
t
SS
Soft shutdown duration period 5000 9250 13500
V
DS
=15V,Fig. 9
t
SY_FLT
,
DSH to SY_FLT propagation delay at HO turn on
-- 3600
--
DESAT1
V
HIN
= 1
t
SY_FLT,
DSH to SY_FLT propagation delay after blanking
1300 --
--
V
DS
= 15V, Fig. 10
DESAT2
t
SY_FLT,
DSL to SY_FLT propagation delay at LO turn on
-- 3050
--
DESAT3
V
LIN
= 1
t
SY_FLT,
DSL to SY_FLT propagation delay after blanking
1050 --
--
V
DESAT
=15V,Fig.10
DESAT4
t
BL
DS blanking time at turn on
-- 3000
--
V
HIN
= V
LIN
= 1
V
DESA
T=15V,Fig.10
Dead-time/Delay Matching Characteristics
DT Dead-time
--
330
--
Figure
11
MDT
Dead-time matching, MDT=DTH-DTL
--
--
75
External DT=0nsec
Figure 11
PDM
Propagation delay matching,
--
--
75
External DT>
Max(ton, toff) - Min(ton, toff)
ns
500nsec, Fig.7
IR2114/IR21141/IR2214/IR22141
7
HIN
LIN
HO (HOP=HON)
LO (LOP=LON)
10%
3.3V
PW
in
PW
out
10%
90%
90%
50%
50%
t
on
t
r
t
off
t
f
Figure 7: Switching Time Waveforms
Ton1
Io1+
Io2+
Figure 8: Output Source Current
HIN/LIN
HO/LO
8V
8V
t
SS
t
DESAT
3.3V
DSH/DSL
t
DS
SSD Driver Enable
Figure 9: Soft Shutdown Timing Waveform
IR2114/IR21141/IR2214/IR22141
8
HIN
DSH
SY_FLT
t
DESAT1
8V
50%
t
SY_FLT,DESAT1
HON
90%
50%
t
BL
FAULT/SD
FLTCLR
SoftShutdown
LIN
LON
90%
SoftShutdown
t
DESAT2
8V
t
SY_FLT,DESAT2
50%
t
BL
DSL
90%
50%
t
BL
SoftShutdown
90%
SoftShutdown
50%
t
BL
8V
8V
50%
t
SY_FLT,DESAT3
t
SY_FLT,DESAT4
t
DESAT3
t
DESAT4
50%
50%
Turn-On Propagation Delay
Turn-On Propagation Delay
90%
Turn_Off propagation Delay
50%
90%
50%
50%
10%
10%
Figure 10: Desat Timing
HIN
LIN
HO (HOP=HON)
LO (LOP=LON)
DTH
DTL
50% 50%
50%
50%
50%
50%
MDT=DTH-DTL
Figure 11: Internal Dead-Time Timing
IR2114/IR21141/IR2214/IR22141
9
Lead Assignments
24-Lead SSOP
Lead Definitions
Symbol Description
VCC
Low side gate driver supply
VSS Logic
Ground
HIN
Logic input for high side gate driver outputs (HOP/HON)
LIN
Logic input for low side gate driver outputs (LOP/LON)
FAULT/SD
Dual function (in/out) active low pin. Refer to figures 17, 18 and 15. As an output, indicates fault
condition. As an input, shuts down the outputs of the gate driver regardless H
IN
/L
IN
status.
SY_FLT
Dual function (in/out) active low pin. Refer to figures 17, 18 and 15. As an output, indicates SSD
sequence is occurring. As an input, an active low signal freezes both output status.
FLT_CLR Fault clear active high input. Clears latched fault condition (See figure 17)
LOP
Low side driver sourcing output
LON
Low side driver sinking output
DSL
Low side IGBT desaturation protection input
SSDL Low
side
soft
shutdown
COM
Low side driver return
VB
High side gate driver floating supply
HOP
High side driver sourcing output
HON
High side driver sinking output
DSH
High side IGBT desaturation protection input
SSDH
High side soft shutdown
VS
High side floating supply return
SSOP24
1
12
24
13
SSDL
FLT_CLR
HIN
COM
SY_FLT
LON
FAULT/SD
VSS
LOP
VCC
DSL
HOP
SSDH
HON
N.C.
VS
N.C.
DSH
VB
N.C.
N.C.
N.C.
N.C.
LIN
IR2114/IR21141/IR2214/IR22141
10
Functional Block Diagram
SCHMITT
TRIGGER
INPUT
SHOOT
THROUGH
PREVENTION
(DT) Deadtime
LEVEL
SHIFTERS
LATCH
LOCAL DESAT
PROTECTION
SOFT SHUTDOWN
UV_VBS DETECT
di/dt control
Driver
UV_VCC
DETECT
LOCAL DESAT
PROTECTION
SOFTSHUTDOWN
di/dt control
Driver
on/off
on/off
desat
soft
shutdown
on/off
soft
shutdown
on/off (HS)
DesatHS
DesatLS
on/off (LS)
Har
d Shu
t
Down
int
er
nal Ho
l
d
SD
FAULT LOGIC
managemend
(See figure 14)
UV_VCC
VB
HOP
HON
SSDH
DSH
VS
LOP
LON
SSDL
DSL
COM
VSS
FLT_CLR
FAULT/SD
SY_FLT
LIN
HIN
VCC
FAULT
HOLD
SSD
INPUT
HOLD
LOGIC
OUTPUT
SHUTDOWN
LOGIC
State Diagram
Start-Up
Sequence
FAULT
HO/LO=1
HO=LO=0
UnderVoltage
V
CC
HO=LO=0
Freeze
ShutDown
SY
_F
LT
S
Y
_F
L
T
SY
_F
LT
FL
T_
C
LR
HI
N/
LI
N
H
IN
/L
IN
UV_
VCC
U
V
_V
C
C
UV_VBS
FAUL
T/SD
DS
H/
L
DS
H
/L
FA
UL
T/
SD
FAULT/SD
FAULT
/SD
FA
UL
T/
SD
UV
_V
BS
UV_VCC
DESAT
EVENT
UnderVoltage
V
BS
HO=0, LO=LIN
Soft
ShutDown
Stable State
- FAULT
- HO=LO=0
(Normal
operation)
- HO/LO=1
(Normal
operation)
- UNDERVOLTAGE
V
CC
- SHUTDOWN
(SD)
- UNDERVOLTAGE
V
BS
- FREEZE
Temporary State
- SOFT
SHUTDOWN
- START UP SEQUENCE
System Variable
- FLT_CLR
- HIN/LIN
- UV_VCC
- UV_VBS
- DSH/L
- SY_FLT
- FAULT/SD
NOTE1: a change of logic value of the signal labeled on lines (system variable) generates a state transition.
NOTE2: Exiting from UNDERVOLTAGE V
BS
state, the HO goes high only if a rising edge event happens in
H
IN
.
IR2114/IR21141/IR2214/IR22141
11
Logic Table
Output drivers status description
HO/LO
status
HOP/LOP HON/LON SSDH/SSDL
0
HiZ 0 HiZ
1
1 HiZ HiZ
SSD
HiZ HiZ
0
LO/HO
Output follows inputs (in=1->out=1, in=0->out=0)
LO
n-1
/HO
n-1
Output keeps previous status
INPUTS
INPUT/OUTPUT
Under Voltage
Yes: V< UV threshold
No : V> UV threshold
X : don't care
OUTPUTS
Operation
Hin
Lin
FLT_CLR
SY_FLT
SSD: desat (out)
HOLD: freezing (in)
FAULT/SD
SD: shutdown (in)
FAULT: diagnostic (out)
V
CC
V
BS
HO LO
Shut Down
X X X
X
0
(SD)
X
X
0
0
Fault Clear
H
IN
L
IN
NOTE1
(FAULT)
No No HO
LO
1 0 0
1
1
No No 1 0
0 1 0
1
1
No No 0 1
Normal
Operation
0 0 0
1
1
No No 0 0
Anti Shoot
Through
1 1 0
1
1
No No 0 0
1 0 0
(SSD)
1 No
No
SSD
0
Soft Shut
Down
(entering)
0 1 0
(SSD)
1 No
No
0
SSD
X X 0
(SSD)
(FAULT)
No No 0 0
Soft Shut
Down
(finishing)
X X 0
(SSD)
(FAULT)
No No 0 0
Freeze
X X X
0
(HOLD)
1
No
No
HO
n-1
LO
n-1
X
L
IN
X 1
1 No
Yes
0
LO
Under
Voltage
X
X
X 1 0
(FAULT)
Yes
X
0
0
NOTE1: SY_FLT automatically resets after SSD event is over and FLT_CLR is not required. In order to avoid
FLT_CLR to conflict with the SSD procedure, FLT_CLR should not be operated while SY_FLT is active.
IR2114/IR21141/IR2214/IR22141
12
FEATURES DESCRIPTION
1 Start-up sequence
At power supply start-up it is recommended to
keep FLT_CLR pin active until supply voltages are
properly established. This prevents spurious
diagnostic signals being generated. All protection
functions are operating independently from
FLT_CLR status and output driver status reflects
the input commands.
When bootstrap supply topology is used for
supplying the floating high side stage, the following
start-up sequence is recommended (see also
figure 12):
1. Set
Vcc
2. Set FLT_CLR pin to HIGH level
3. Set LIN pin to HIGH level and let the
bootstrap capacitor be charged
4. Release LIN pin to LOW level
5. Release FLT_CLR pin to LOW level
VCC
FLT_CLR
LIN
LO
Figure 12 Start-up sequence
A minimum 15 us LIN and FLT-CLR pulse is
required.
2 Normal operation mode
After start-up sequence has been terminated, the
device becomes fully operative (see grey blocks in
the State Diagram).
HIN and LIN produce driver outputs to switch
accordingly, while the input logic checks the input
signals preventing shoot-through events and
including DeadTime (DT).
3 Shut down
The system controller can asynchronously
command the Hard ShutDown (HSD) through the
3.3 V compatible CMOS I/O FAULT/SD pin. This
event is not latched.
In a multi-phase system, FAULT/SD signals are or-
wired so the controller or one of the gate drivers
can force simultaneous shutdown to the other gate
drivers through the same pin.
4 Fault management
IR2114/21141/2214/22141 is able to manage the
both the supply failure (undervoltage lock out on
both low and high side circuits) and the
desaturation of both power transistors.
4.1 Undervoltage (UV)
The Undervoltage protection function disables the
driver's output stage preventing the power device
being driven with too low voltages.
Both the low side (V
CC
supplied) and the floating
side (V
BS
supplied) are controlled by a dedicate
undervoltage function.
Undervoltage event on the V
CC
(when
V
CC
< UV
VCC-
) generates a diagnostic signal by
forcing FAULT/SD pin low (see FAULT/SD section
and figure 14). This event disables both low side
and floating drivers and the diagnostic signal holds
until the under voltage condition is over. Fault
condition is not latched and the FAULT/SD pin is
released once V
CC
becomes higher than UV
VCC+
.
The undervoltage on the V
BS
works disabling only
the floating driver. Undervoltage on V
BS
does not
prevent the low side driver to activate its output nor
generate diagnostic signals. V
BS
undervoltage
condition (V
BS
< UV
VBS-
) latches the high side
output stage in the low state. V
BS
must be
reestablished higher than UV
VBS+
to return in
normal operating mode. To turn on the floating
driver H
IN
must be re-asserted high (rising edge
event on H
IN
is required).
4.2 Power devices desaturation
Different causes can generate a power inverter
failure: phase and/or rail supply short-circuit,
overload conditions induced by the load, etc... In
all these fault conditions a large current increase is
produced in the IGBT.
The IR2114/21141/2214/22141 fault detection
circuit monitors the IGBT emitter to collector
voltage (V
CE
) by means of an external high voltage
diode. High current in the IGBT may cause the
transistor to desaturate, i.e. V
CE
to increase.
Once in desaturation, the current in power
transistor can be as high as 10 times the nominal
current. Whenever the transistor is switched off,
this high current generates relevant voltage
transients in the power stage that need to be
smoothed out in order to avoid destruction (by
over-voltages). The gate driver accomplishes the
transients control by smoothly turning off the
desaturated transistor by means of the SSD pin
activating a so called Soft ShutDown sequence
(SSD).
4.2.1 Desaturation detection: DSH/L function
Figure 13 shows the structure of the desaturation
sensing and soft shutdown block. This
configuration is the same for both high and low
side output stages.
IR2114/IR21141/IR2214/IR22141
13
t
BL
Blanking
VB/Vcc
HONH/L
DSH/L
VS/COM
R
on,
s
s
HOPH/L
tss
One Shot
V
DESAT
(t
on
1)
ONE
SHOT
t
DS
filter
SSDH/L
RD
SH/L
P
P
r
r
e
e
D
D
r
r
i
i
v
v
e
e
r
r
sensing
diode
on/off
DesatHS/LS
desat
comparator
Figure 13: high and low side output stage
FLTCLR
Q
Q
SET
CLR
S
R
FAULT/SD
SY_FLT
internal
HOLD
(external
hold)
(external hard
shutdown)
internal FAULT
(hard shutdown)
UVCC
DesatHS
DesatLS
Figure 14: fault management diagram
The external sensing diode should have BV>600V
or 1200V and low stray capacitance (in order to
minimize noise coupling and switching delays).
The diode is biased by an internal pull-up resistor
R
DSH/L
(equal to V
CC
/I
DS-
or V
BS
/I
DS-
for IR2114 or
IR2214) or by a dedicated circuit (see the active-
bias section for IR21141 and IR22141). When V
CE
increases, the voltage at DSH/L pin increases too.
Being internally biased to the local supply, DSH/L
voltage is automatically clamped. When DSH/L
exceeds the V
DESAT+
threshold the comparator
triggers (see figure 13). Comparator output is
filtered in order to avoid false desaturation
detection by externally induced noise; pulses
shorter than t
DS
are filtered out. To avoid detecting
a false desaturation during IGBT turn on, the
desaturation circuit is disabled by a Blanking signal
(T
BL
, see Blanking block in figure 13). This time is
the estimated maximum IGBT turn on time and
must be not exceeded by proper gate resistance
sizing. When the IGBT is not completely saturated
after T
BL
, desaturation is detected and the driver
will turn off.
Eligible desaturation signals initiate the Soft
Shutdown sequence (SSD). While in SSD, the
output driver goes in high impedance and the SSD
pull-down is activated to turn off the IGBT through
SSDH/L pin. The SY_FLT output pin (active low,
see figure 14) reports the gate driver status all the
way long SSD sequence lasts (t
SS
). Once finished
SSD, SYS_FLT releases, and the gate driver
generates a FAULT signal (see the FAULT/SD
section) by activating FAULT/SD pin. This
generates a hard shut down for both high and low
output stages (HO=LO=low). Each driver is latched
low until the fault is cleared (see FLT_CLR).
Figure 14 shows the fault management circuit. In
this diagram DesatHS and DesatLS are two
internal signals that come from the output stages
(see figure 13).
It must be noted that while in Soft Shut Down, both
Under Voltage fault and external Shut Down (SD)
IR2114/IR21141/IR2214/IR22141
14
are masked until the end of SSD. Desaturation
protection is working independently by the other
entire control pin and it is disabled only when the
output status is off.
VCC
LIN
HIN
FLT_CLR
VB
HOP
HON
SSH
DSH
VS
LOP
LON
SSL
DSL
COM
VSS
SY_FLT
FAULT/SD
I
R
2214
VCC
LIN
HIN
FLT_CLR
VB
HOP
HON
SSH
DSH
VS
LOP
LON
SSL
DSL
COM
VSS
SY_FLT
FAULT/SD
I
R
2214
VCC
LIN
HIN
FLT_CLR
VB
HOP
HON
SSH
DSH
VS
LOP
LON
SSL
DSL
COM
VSS
SY_FLT
FAULT/SD
I
R
2214
phase U
phase V
phase W
FAULT
Figure 15: IR2x14x application in 3ph system.
4.2.2 Fault management in multi-phase
systems
In a system with two or more gate drivers the
devices must be connected as in figure 15.
SY_FLT.
The bi-directional SY_FLT pins communicate each
other in the local network. The logic signal is active
low.
The device that detects the IGBT desaturation
activates the SY_FLT, which is then read by the
other gate drivers. When SYS_FLT is active all the
drivers hold their output state regardless the input
signals (H
IN
, L
IN
) they receive from the controller
(freeze state).
This feature is particularly important in phase-to-
phase short circuit where two IGBTs are involved;
in fact, while one is softly shutting-down, the other
must be prevented from hard shutdown to avoid
vanishing SSD.
In the Freeze state the frozen drivers are not
completely inactive because desaturation detection
still takes the highest priority.
SY_FLT communication has been designed for
creating a local network between the drivers. There
is no need to wire SY_FLT to the controller.
FAULT/SD
The bi-directional FAULT/SD pins communicates
each other and with the system controller. The
logic signal is active low.
When low, the FAULT/SD signal commands the
outputs to go off by hard shutdown. There are
three events that can force FAULT/SD low:
1.
Desaturation detection event: the
FAULT\SD pin is latched low when SSD is
over, and only a FLT_CLR signal can reset
it.
2. Undervoltage on V
CC
: the FAULT\SD pin is
forced low and held until the undervoltage
is active (not latched).
3. FAULT/SD is externally driven low either
from the controller or from another
IR2x14x device. This event is not latched;
therefore the FLT_CLR cannot disable it.
Only when FAULT/SD becomes high the
device returns in normal operating mode.
5 Active bias
For the purpose of sensing the power transistor
desaturation the collector voltage is read by an
external HV diode. The diode is normally biased by
an internal pull up resistor connected to the local
supply line (V
B
or V
CC
). When the transistor is "on"
the diode is conducting and the amount of current
flowing in the circuit is determined by the internal
pull up resistor value.
In the high side circuit, the desaturation biasing
current may become relevant for dimensioning the
bootstrap capacitor (see figure 19). In fact, too low
pull up resistor value may result in high current
discharging significantly the bootstrap capacitor.
For that reason typical pull up resistor are in the
range of 100 k. This is the value of the internal
pull up.
While the impedance of DSH/DSL pins is very low
when the transistor is on (low impedance path
through the external diode down to the power
transistor), the impedance is only controlled by the
pull up resistor when the transistor is off. In that
case relevant dV/dt applied by the power transistor
during the commutation at the output results in a
considerable current injected through the stray
capacitance of the diode into the desaturation
detection pin (DSH/L). This coupled noise may be
easily reduced using an active bias for the sensing
diode.
An Active Bias structure is available only for
IR21141 or IR22141 version for DSH/L pin. The
DSH/L pins present an active pull-up respectively
to VB/VCC, and a pull-down respectively to
VS/COM.
The dedicated biasing circuit reduces the
impedance on the DSH/L pin
when the voltage
exceeds the V
DESAT
threshold (see figure 16). This
low impedance helps in rejecting the noise
providing the current inject by the parasitic
capacitance. When the power transistor is fully on,
the sensing diode gets forward biased and the
voltage at the DSH/L pin decreases. At this point
the biasing circuit deactivates, in order to reduce
the bias current of the diode as shown in figure 16.
VDSH/L
V
D
E
S
A
T
-
V
D
E
S
A
T
+
100 ohm
100K ohm
RDSH/L
Figure 16: R
DSH/L
Active Biasing
IR2114/IR21141/IR2214/IR22141
15
6 Output stage
The structure is shown in figure 13 and consists of
two turns on stages and one turn off stage.
When the driver turns on the IGBT (see figure 8), a
first stage is constantly activated while an
additional stage is maintained active only for a
limited time (ton1). This feature boost the total
driving capability in order to accommodate both
fast gate charge to the plateau voltage and dV/dt
control in switching.
At turn off, a single n-channel sinks up to 3A (I
O-
)
and offers a low impedance path to prevent the
self-turn on due to the parasitic Miller capacitance
in the power switch.
7 Timing and logic state diagrams
description
The following figures show the input/output logic
diagram.
Figure 17 shows the SY_FLT and FAULT/SD
signals as output, whereas figure 18 as input.
HIN
LIN
FAULT/SD
LO(LOP/LON)
DSH
FLT_CLR
SY_FLT
HO(HOP/HON)
DSL
A
B
C
D
E
F
G
Figure 17: I/O timing diagram with SY_FLT and FAULT/SD as output
A B
C
D
E
F
HIN
LIN
SY_FLT
FAULT/SD
FLT_CLR
HO (HOP/HON)
LO (LOP/LON)
Figure 18: I/O logic diagram with SY_FLT and FAULT/SD as input
Referred to timing diagram of figure 17:
A. When the input signals are on together
the outputs go off (anti-shoot through).
B. The HO signal is on and the high side
IGBT desaturates, the HO turn off softly
while the SY_FLT stays low. When
SY_FLT goes high the FAULT/SD goes
low. While in SSD, if LIN goes up, LO
does not change (freeze).
C. When FAULT/SD is latched low (see
FAULT/SD section) FLT_CLR can disable
IR2114/IR21141/IR2214/IR22141
16
it and the outputs go back to follow the
inputs.
D. The DSH goes high but this is not read
because HO is off.
E. The LO signal is on and the low side
IGBT desaturates, the low side behaviour
is the same as described in point B.
F. The DSL goes high but this is not read
because LO is off.
G. As point A (anti-shoot through).
Referred to timing diagram figure 18:
A. The device is in hold state, regardless of
input variations. Hold state is forced by
SY_FLT forced low externally
B. The device outputs goes off by hard
shutdown, externally commanded. A
through B is the same sequence adopted
by another IR2x14x device in SSD
procedure.
C.
Externally driven low FAULT/SD
(shutdown state) cannot be disabled by
forcing FLT_CLR (see FAULT/SD
section).
D. The FAULT/SD is released and the
outputs go back to follow the inputs.
E. Externally driven low FAULT/SD: outputs
go off by hard shutdown (like point B).
F. As point A and B but for the low side
output.
Sizing tips
Bootstrap supply
The V
BS
voltage provides the supply to the high
side driver circuitry of the gate driver. This supply
sits on top of the V
S
voltage and so it must be
floating.
The bootstrap method to generate V
BS
supply can
be used with any of the IR2114, IR21141,
IR2214, IR22141. The bootstrap supply is formed
by a diode and a capacitor connected as in figure
19.
bootstrap
diode
IR22
14
bootstrap
capacitor
VB
VS
VCC
HOP
HON
SSDH
DC+
bootstrap
resistor
COM
V
CC
V
BS
V
F
V
GE
V
CEon
V
FP
I
LOAD
motor
R
boot
Figure 19: bootstrap supply schematic
This method has the advantage of being simple
and low cost but may force some limitations on
duty-cycle and on-time since they are limited by
the requirement to refresh the charge in the
bootstrap capacitor.
Proper capacitor choice can reduce drastically
these limitations.
Bootstrap capacitor sizing
To size the bootstrap capacitor, the first step is to
establish the minimum voltage drop (V
BS
) that
we have to guarantee when the high side IGBT is
on.
If V
GEmin
is the minimum gate emitter voltage we
want to maintain, the voltage drop must be:
CEon
GE
F
CC
BS
V
V
V
V
V
-
-
-
min
under the condition:
-
>
BSUV
GE
V
V
min
where V
CC
is the IC voltage supply, V
F
is bootstrap
diode forward voltage, V
CEon
is emitter-collector
voltage of low side IGBT and V
BSUV-
is the high-
side supply undervoltage negative going
threshold.
Now we must consider the influencing factors
contributing V
BS
to decrease:
- IGBT turn on required Gate charge (Q
G
);
- IGBT gate-source leakage current (I
LK_GE
);
- Floating section quiescent current (I
QBS
);
- Floating section leakage current (I
LK
)
- Bootstrap diode leakage current (I
LK_DIODE
);
- Desat diode bias when on (I
DS-
)
- Charge required by the internal level shifters
(Q
LS
); typical 20nC
-
Bootstrap capacitor leakage current
(I
LK_CAP
);
- High side on time (T
HON
).
I
LK_CAP
is only relevant when using an electrolytic
capacitor and can be ignored if other types of
capacitors are used. It is strongly recommend
using at least one low ESR ceramic capacitor
(paralleling electrolytic and low ESR ceramic may
result in an efficient solution).
Then we have:
+
+
+
+
=
QBS
GE
LK
LS
G
TOT
I
I
Q
Q
Q
_
(
HON
DS
CAP
LK
DIODE
LK
LK
T
I
I
I
I
+
+
+
+
-
)
_
_
The minimum size of bootstrap capacitor is:
IR2114/IR21141/IR2214/IR22141
17
BS
TOT
BOOT
V
Q
C
=
min
An example follows using IR2214SS or
IR22141SS:
a) using a 25A @ 125C 1200V IGBT
(IRGP30B120KD):
I
QBS
= 800 A
(This Datasheet);
I
LK
= 50 A (See Static Electrical Charact.);
Q
LS
= 20 nC;
Q
G
= 160 nC (Datasheet IRGP30B120KD);
I
LK_GE
= 100 nA (Datasheet IRGP30B120KD);
I
LK_DIODE
= 100 A (with reverse recovery time
<100 ns);
I
LK_CAP
= 0 (neglected for ceramic capacitor);
I
DS-
= 150 A (see Static Electrical Charact.);
T
HON
= 100 s.
And:
V
CC
= 15 V
V
F
= 1 V
V
CEonmax
= 3.1 V
V
GEmin
= 10.5 V
the maximum voltage drop V
BS
becomes
=
-
-
-
CEon
GE
F
CC
BS
V
V
V
V
V
min
V
V
V
V
V
4
.
0
1
.
3
5
.
10
1
15
=
-
-
-
=
And the bootstrap capacitor is:
nF
V
nC
C
BOOT
725
4
.
0
290
=
NOTICE:
Here above
V
CC
has been chosen
to be 15V. Some IGBTs may require higher
supply to work correctly with the bootstrap
technique. Also Vcc variations must be
accounted in the above formulas.
Some important considerations
a. Voltage
ripple
There are three different cases making the
bootstrap circuit gets conductive (see figure 19)
I
LOAD
< 0; the load current flows in the low
side IGBT displaying relevant V
CEon
CEon
F
CC
BS
V
V
V
V
-
-
=
In this case we have the lowest value for V
BS
.
This represents the worst case for the bootstrap
capacitor sizing. When the IGBT is turned off
the Vs node is pushed up by the load current
until the high side freewheeling diode get
forwarded biased
I
LOAD
= 0; the IGBT is not loaded while being
on and V
CE
can be neglected
F
CC
BS
V
V
V
-
=
I
LOAD
> 0; the load current flows through the
freewheeling diode
FP
F
CC
BS
V
V
V
V
+
-
=
In this case we have the highest value for V
BS
.
Turning on the high side IGBT, I
LOAD
flows into it
and V
S
is pulled up.
To minimize the risk of undervoltage, bootstrap
capacitor should be sized according to the I
LOAD
<0
case.
b. Bootstrap
Resistor
A resistor (R
boot
) is placed in series with bootstrap
diode (see figure 19) so to limit the current when
the bootstrap capacitor is initially charged. We
suggest not exceeding some Ohms (typically 5,
maximum 10 Ohm) to avoid increasing the V
BS
time-constant. The minimum on time for charging
the bootstrap capacitor or for refreshing its charge
must be verified against this time-constant.
c. Bootstrap
Capacitor
For high T
HON
designs where is used an
electrolytic tank capacitor, its ESR must be
considered. This parasitic resistance forms a
voltage divider with R
boot
generating a voltage step
on V
BS
at the first charge of bootstrap capacitor.
The voltage step and the related speed (dV
BS
/dt)
should be limited. As a general rule, ESR should
meet the following constraint:
V
V
R
ESR
ESR
CC
BOOT
3
+
Parallel combination of small ceramic and large
electrolytic capacitors is normally the best
compromise, the first acting as fast charge thank
for the gate charge only and limiting the dV
BS
/dt
by reducing the equivalent resistance while the
second keeps the V
BS
voltage drop inside the
desired V
BS
.
d. Bootstrap
Diode
The diode must have a BV> 600V or 1200V and a
fast recovery time (trr < 100 ns) to minimize the
amount of charge fed back from the bootstrap
capacitor to V
CC
supply.
IR2114/IR21141/IR2214/IR22141
18
Gate resistances
The switching speed of the output transistor can
be controlled by properly size the resistors
controlling the turn-on and turn-off gate current.
The following section provides some basic rules
for sizing the resistors to obtain the desired
switching time and speed by introducing the
equivalent output resistance of the gate driver
(R
DRp
and R
DRn
).
The examples always use IGBT power transistor.
Figure 20 shows the nomenclature used in the
following paragraphs. In addition, V
ge
*
indicates
the plateau voltage, Q
gc
and Q
ge
indicate the gate
to collector and gate to emitter charge
respectively.
V
ge
*
10%
t
1
,Q
GE
C
RESoff
C
RESon
V
CE
I
C
V
GE
C
RES
10%
90%
C
RES
t
Don
V
GE
dV/dt
I
C
t
2
,Q
GC
t,Q
t
R
t
SW
Figure 20: Nomenclature
Sizing the turn-on gate resistor
-
Switching-time
For the matters of the calculation included
hereafter, the switching time t
sw
is defined as the
time spent to reach the end of the plateau voltage
(a total Q
gc
+Q
ge
has been provided to the IGBT
gate). To obtain the desired switching time the
gate resistance can be sized starting from Q
ge
and
Q
gc
, Vcc, V
ge
*
(see figure 21):
sw
ge
gc
avg
t
Q
Q
I
+
=
and
avg
ge
TOT
I
V
Vcc
R
*
-
=
Vcc/Vb
R
DRp
R
Gon
C
RES
COM/Vs
I
avg
Figure 21: R
Gon
sizing
where
Gon
DRp
TOT
R
R
R
+
=
R
Gon
= gate on-resistor
R
DRp
= driver equivalent on-resistance
When R
Gon
> 7 Ohm, R
DRp
is defined by
>
-
+
=
+
+
+
1
1
1
1
2
1
1
on
SW
o
on
SW
on
SW
o
o
DRp
t
t
when
I
Vcc
t
t
when
t
t
I
Vcc
I
Vcc
R
(I
O1+
,I
O2+
and t
on1
from "static Electrical
Characteristics").
Table 1 reports the gate resistance size for two
commonly used IGBTs (calculation made using
typical datasheet values and assuming Vcc=15V).
-
Output voltage slope
Turn-on gate resistor R
Gon
can be sized to control
output slope
(dV
OUT
/dt)
.
While the output voltage has a non-linear
behaviour, the maximum output slope can be
approximated by:
RESoff
avg
out
C
I
dt
dV
=
inserting the expression yielding I
avg
and
rearranging:
dt
dV
C
V
Vcc
R
out
RESoff
ge
TOT
-
=
*
As an example, table 2 shows the sizing of gate
resistance to get dV
out
/dt=5V/ns when using two
popular IGBTs, typical datasheet values and
assuming Vcc=15V.
IR2114/IR21141/IR2214/IR22141
19
NOTICE: Turn on time must be lower than T
BL
to
avoid improper desaturation detection and SSD
triggering.
Sizing the turn-off gate resistor
The worst case in sizing the turn-off resistor R
Goff
is when the collector of the IGBT in off state is
forced to commutate by external events (i.e. the
turn-on of the companion IGBT).
In this case the dV/dt of the output node induces a
parasitic current through C
RESoff
flowing in R
Goff
and R
DRn
(see figure 22).
If the voltage drop at the gate exceeds the
threshold voltage of the IGBT, the device may self
turn on causing large oscillation and relevant
cross conduction.
OFF
HS Turning ON
ON
dV/dt
R
Goff
C
RESoff
R
DRn
C
IES
Figure 22: R
Goff
sizing: current path when Low
Side is off and High Side turns on
The transfer function between IGBT collector and
IGBT gate then becomes:
)
(
)
(
1
)
(
IES
RESoff
DRn
Goff
RESoff
DRn
Goff
de
ge
C
C
R
R
s
C
R
R
s
V
V
+
+
+
+
=
Which yields to a high pass filter with a pole at:
)
(
)
(
1
/
1
IES
RESoff
DRn
Goff
C
C
R
R
+
+
=
As a result, when
is faster than the collector rise
time (to be verified after calculation) the transfer
function can be approximated by:
RESoff
DRn
Goff
de
ge
C
R
R
s
V
V
+
=
)
(
So that
dt
dV
C
R
R
V
de
RESoff
DRn
Goff
ge
+
=
)
(
in the
time domain.
Then the condition:
(
)
dt
dV
C
R
R
V
V
out
RESoff
DRn
Goff
ge
th
+
=
>
must be verified to avoid spurious turn on.
Rearranging the equation yields:
DRn
RESoff
th
Goff
R
dt
dV
C
V
R
-
<
In any case, the worst condition for unwanted turn
on is with very fast steps on IGBT collector.
In that case collector to gate transfer function can
be approximated with the capacitor divider:
)
(
IES
RESoff
RESoff
de
ge
C
C
C
V
V
+
=
which is driven only by IGBT characteristics.
As an example, table 3 reports R
Goff
(calculated
with the above mentioned disequation) for two
popular IGBTs to withstand dV
out
/dt = 5V/ns.
NOTICE: the above-described equations are
intended being an approximated way for the gate
resistances sizing. More accurate sizing may
account more precise device modelling and
parasitic component dependent on the PCB and
power section layout and related connections.
Table 1: t
sw
driven R
Gon
sizing
IGBT Qge
Qgc
Vge*
tsw
Iavg
Rtot
RGon
std commercial value
Tsw
IRGP30B120K(D) 19nC 82nC 9V 400ns 0.25A 24
RTOT - RDRp = 12.7
10
420ns
IRG4PH30K(D) 10nC
20nC
9V 200ns
0.15A
40
RTOT - RDRp = 32.5
33
202ns
Table 2: dV
OUT
/dt driven R
Gon
sizing
IGBT Qge
Qgc
Vge*
CRESoff
Rtot
RGon
std commercial value
dVout/dt
IRGP30B120K(D) 19nC
82nC
9V 85pF 14
RTOT - RDRp = 6.5
8.2
4.5V/ns
IRG4PH30K(D) 10nc
20nC
9V
14pF 85
RTOT - RDRp = 78
82
5V/ns
Table 3: R
Goff
sizing
IGBT Vth(min)
CRESoff
RGoff
IRGP30B120K(D) 4
85pF RGoff
4
IRG4PH30K(D) 3
14pF RGoff
35
IR2114/IR21141/IR2214/IR22141
20
PCB LAYOUT TIPS
Distance from H to L voltage:
The IR2x14x pin out maximizes the distance
between floating (from DC- to DC+) and low
voltage pins. It's strongly recommended to place
components tied to floating voltage in the high
voltage side of device (V
B
, V
S
side) while the other
components in the opposite side.
Ground plane:
Ground plane must not be placed under or nearby
the high voltage floating side to minimize noise
coupling.
Gate drive loops:
Current loops behave like an antenna able to
receive and transmit EM noise. In order to reduce
EM coupling and improve the power switch turn
on/off performances, gate drive loops must be
reduced as much as possible. Figure 23 shows
the high and low side gate loops.
Moreover, current can be injected inside the gate
drive loop via the IGBT collector-to-gate parasitic
capacitance. The parasitic auto-inductance of the
gate loop contributes to develop a voltage across
the gate-emitter increasing the possibility of self
turn-on effect. For this reason is strongly
recommended to place the three gate resistances
close together and to minimize the loop area (see
figure 23).
gate
resistance
VS/COM
VB/ VCC
H/LOP
H/LON
SSDH/L
V
GE
Gate Drive
Loop
C
GC
I
GC
Figure 23: gate drive loop
Supply capacitors:
IR2x14x output stages are able to quickly turn on
IGBT with up to 2 A of output current. The supply
capacitors must be placed as close as possible to
the device pins (V
CC
and V
SS
for the ground tied
supply, V
B
and V
S
for the floating supply) in order
to minimize parasitic inductance/resistance.
Routing and placement example:
Figure 24 shows one of the possible layout
solutions using a 3 layer PCB. This example takes
into account all the previous considerations.
Placement and routing for supply capacitors and
gate resistances in the high and low voltage side
minimize respectively supply path and gate drive
loop. The bootstrap diode is placed under the
device to have the cathode as close as possible to
bootstrap capacitor and the anode far from high
voltage and close to V
CC
.
R2
R3
R4
R5
R6
R7
C2
D3
D2
IR2214
V
GH
V
GL
DC+
Phase
a)
D1
R1
C1
V
EH
V
EL
V
CC
b)
c)
Figure 24: layout example: top (a), bottom (b) and
ground plane (c) layer
Referred to figure 24:
Bootstrap section: R1, C1, D1
High side gate: R2, R3, R4
High side Desat: D2
Low side supply: C2
Low side gate: R5, R6, R7
Low side Desat: D3
IR2114/IR21141/IR2214/IR22141
21
Case Outline
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
This product has been designed and qualified for industrial market
Data and specifications subject to change without notice. 3/2
4/2005
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