www.docs.chipfind.ru
www.irf.com
1
1/14/04
IRF7832
HEXFET
Power MOSFET
Notes
through
are on page 10
Benefits
l
Very Low R
DS(on)
at 4.5V V
GS
l
Ultra-Low Gate Impedance
l
Fully Characterized Avalanche Voltage
and Current
l
20V V
GS
Max. Gate Rating
Applications
l
Synchronous MOSFET for Notebook
Processor Power
l
Synchronous Rectifier MOSFET for
Isolated DC-DC Converters in
Networking Systems
Top View
8
1
2
3
4
5
6
7
D
D
D
D
G
S
A
S
S
A
SO-8
V
DSS
R
DS(on)
max
Qg
30V
4.0m
:
@V
GS
= 10V 34nC
Absolute Maximum Ratings
Parameter
Units
V
DS
Drain-to-Source Voltage
V
V
GS
Gate-to-Source Voltage
I
D
@ T
A
= 25C
Continuous Drain Current, V
GS
@ 10V
I
D
@ T
A
= 70C
Continuous Drain Current, V
GS
@ 10V
A
I
DM
Pulsed Drain Current
c
P
D
@T
A
= 25C
Power Dissipation
W
P
D
@T
A
= 70C
Power Dissipation
Linear Derating Factor
W/C
T
J
Operating Junction and
C
T
STG
Storage Temperature Range
Thermal Resistance
Parameter
Typ.
Max.
Units
R
JL
Junction-to-Drain Lead
20
C/W
R
JA
Junction-to-Ambient
f
50
-55 to + 155
2.5
0.02
1.6
Max.
20
16
160
20
30
PD - 94594D
IRF7832
2
www.irf.com
S
D
G
Static @ T
J
= 25C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
BV
DSS
Drain-to-Source Breakdown Voltage
30
V
V
DSS
/
T
J
Breakdown Voltage Temp. Coefficient
0.023
V/C
R
DS(on)
Static Drain-to-Source On-Resistance
3.1
4.0
m
3.7
4.8
V
GS(th)
Gate Threshold Voltage
1.39
2.32
V
V
GS(th)
Gate Threshold Voltage Coefficient
5.7
mV/C
I
DSS
Drain-to-Source Leakage Current
1.0
A
150
I
GSS
Gate-to-Source Forward Leakage
100
nA
Gate-to-Source Reverse Leakage
-100
gfs
Forward Transconductance
77
S
Q
g
Total Gate Charge
34
51
Q
gs1
Pre-Vth Gate-to-Source Charge
8.6
Q
gs2
Post-Vth Gate-to-Source Charge
2.9
nC
Q
gd
Gate-to-Drain Charge
12
Q
godr
Gate Charge Overdrive
10.5
See Fig. 16
Q
sw
Switch Charge (Q
gs2
+ Q
gd
)
14.9
Q
oss
Output Charge
23
nC
t
d(on)
Turn-On Delay Time
12
t
r
Rise Time
6.7
t
d(off)
Turn-Off Delay Time
21
ns
t
f
Fall Time
13
C
iss
Input Capacitance
4310
C
oss
Output Capacitance
990
pF
C
rss
Reverse Transfer Capacitance
450
Avalanche Characteristics
Parameter
Units
E
AS
Single Pulse Avalanche Energy
d
mJ
I
AR
Avalanche Current
A
Diode Characteristics
Parameter
Min. Typ. Max. Units
I
S
Continuous Source Current
3.1
(Body Diode)
A
I
SM
Pulsed Source Current
160
(Body Diode)
V
SD
Diode Forward Voltage
1.0
V
t
rr
Reverse Recovery Time
41
62
ns
Q
rr
Reverse Recovery Charge
39
59
nC
t
on
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
I
D
= 16A
V
GS
= 0V
V
DS
= 15V
V
GS
= 4.5V, I
D
= 16A
e
V
GS
= 4.5V
Typ.
V
DS
= V
GS
, I
D
= 250A
Clamped Inductive Load
V
DS
= 15V, I
D
= 16A
T
J
= 25C, I
F
= 16A, V
DD
= 10V
di/dt = 100A/s
e
T
J
= 25C, I
S
= 16A, V
GS
= 0V
e
showing the
integral reverse
p-n junction diode.
MOSFET symbol
V
DS
= 16V, V
GS
= 0V
V
DD
= 15V, V
GS
= 4.5V
I
D
= 16A
V
DS
= 15V
V
GS
= 20V
V
GS
= -20V
V
DS
= 24V, V
GS
= 0V
V
DS
= 24V, V
GS
= 0V, T
J
= 125C
Conditions
V
GS
= 0V, I
D
= 250A
Reference to 25C, I
D
= 1mA
V
GS
= 10V, I
D
= 20A
e
Conditions
Max.
260
16
= 1.0MHz
IRF7832
www.irf.com
3
Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
0.1
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
0.01
0.1
1
10
100
1000
I D
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
C
u
r
r
e
n
t
(
A
)
2.25V
20s PULSE WIDTH
Tj = 25C
VGS
TOP
10V
5.0V
4.5V
3.5V
3.0V
2.7V
2.5V
BOTTOM
2.25V
2.0
2.5
3.0
3.5
4.0
VGS, Gate-to-Source Voltage (V)
0
1
10
100
1000
I D
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
C
u
r
r
e
n
t
(
)
TJ = 25C
TJ = 150C
VDS = 15V
20s PULSE WIDTH
0.1
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
I D
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
C
u
r
r
e
n
t
(
A
)
2.25V
20s PULSE WIDTH
Tj = 150C
VGS
TOP
10V
5.0V
4.5V
3.5V
3.0V
2.7V
2.5V
BOTTOM
2.25V
-60 -40 -20
0
20 40 60 80 100 120 140 160
TJ, Junction Temperature (C )
0.0
0.5
1.0
1.5
2.0
R
D
S
(
o
n
)
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
O
n
R
e
s
i
s
t
a
n
c
e
(
N
o
r
m
a
l
i
z
e
d
)
ID = 16A
VGS = 4.5V
IRF7832
4
www.irf.com
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
1
10
100
VDS, Drain-to-Source Voltage (V)
100
1000
10000
100000
C
,
C
a
p
a
c
i
t
a
n
c
e
(
p
F
)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0
10
20
30
40
50
QG Total Gate Charge (nC)
0
1
2
3
4
5
6
V
G
S
,
G
a
t
e
-
t
o
-
S
o
u
r
c
e
V
o
l
t
a
g
e
(
V
)
VDS= 24V
VDS= 15V
ID= 16A
0.0 0.2
0.4
0.6 0.8
1.0 1.2
1.4
1.6
VSD , Source-to-Drain Voltage (V)
0.1
1
10
100
1000
I S
D
,
R
e
v
e
r
s
e
D
r
a
i
n
C
u
r
r
e
n
t
(
)
VGS = 0V
TJ = 150C
TJ = 25C
1
10
100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
I D
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
C
u
r
r
e
n
t
(
A
)
Tc = 25C
Tj = 150C
Single Pulse
1msec
10msec
100sec
IRF7832
www.irf.com
5
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10. Threshold Voltage Vs. Temperature
25
50
75
100
125
150
TC , Case Temperature (C)
0
4
8
12
16
20
24
I D
,
D
r
a
i
n
C
u
r
r
e
n
t
(
A
)
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
100
t1 , Rectangular Pulse Duration (sec)
0.01
0.1
1
10
100
T
h
e
r
m
a
l
R
e
s
p
o
n
s
e
(
Z
t
h
J
A
)
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
-60 -40 -20
0
20 40 60 80 100 120 140 160
TJ , Temperature (C)
0.5
1.0
1.5
2.0
2.5
V
G
S
(
t
h
),
G
a
t
e
T
h
r
e
s
h
o
l
d
V
o
l
t
a
g
e
(
V
)
ID = 250A
IRF7832
6
www.irf.com
Fig 13. Maximum Avalanche Energy
vs. Drain Current
25
50
75
100
125
150
Starting TJ , Junction Temperature (C)
0
100
200
300
400
500
600
E
A
S
,
S
i
n
g
l
e
P
u
l
s
e
A
v
a
l
a
n
c
h
e
E
n
e
r
g
y
(
m
J
)
ID
TOP 7.0A
13A
BOTTOM 16A
Fig 16. Switching Time Test Circuit
Fig 17. Switching Time Waveforms
Fig 12. On-Resistance vs. Gate Voltage
D.U.T.
V
DS
I
D
I
G
3mA
V
GS
.3
F
50K
.2
F
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 15. Gate Charge Test Circuit
Fig 14. Unclamped Inductive Test Circuit
and Waveform
tp
V
(BR)DSS
I
AS
RG
IAS
0.01
tp
D.U.T
L
VDS
+
- VDD
DRIVER
A
15V
20V
VGS
V
GS
Pulse Width < 1s
Duty Factor < 0.1%
V
DD
V
DS
L
D
D.U.T
+
-
V
GS
V
DS
90%
10%
t
d(on)
t
d(off)
t
r
t
f
2
3
4
5
6
7
8
9
10
VGS, Gate -to -Source Voltage (V)
0
2
4
6
8
10
R
D
S
(
o
n)
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
O
n
R
e
s
i
s
t
a
n
c
e
(
m
)
ID = 20A
TJ = 125C
TJ = 25C
IRF7832
www.irf.com
7
Fig 18.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
Power MOSFETs
Circuit Layout Considerations
Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple
5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D =
P.W.
Period
*
V
GS
= 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
R
G
V
DD
dv/dt controlled by R
G
Driver same type as D.U.T.
I
SD
controlled by Duty Factor "D"
D.U.T. - Device Under Test
D.U.T
Fig 19. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
IRF7832
8
www.irf.com
Control FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the R
ds(on)
of the
MOSFET, but these conduction losses are only about
one half of the total losses.
Power losses in the control switch Q1 are given
by;
P
loss
= P
conduction
+ P
switching
+ P
drive
+ P
output
This can be expanded and approximated by;
P
loss
= I
rms
2
R
ds(on )
(
)
+ I
Q
gd
i
g
V
in
f
+ I
Q
gs 2
i
g
V
in
f
+ Q
g
V
g
f
(
)
+
Q
oss
2
V
in
f
This simplified loss equation includes the terms Q
gs2
and Q
oss
which are new to Power MOSFET data sheets.
Q
gs2
is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Q
gs1
and Q
gs2
, can be seen from
Fig 16.
Q
gs2
indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to I
dmax
at which time the drain voltage be-
gins to change. Minimizing Q
gs2
is a critical factor in
reducing switching losses in Q1.
Q
oss
is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Q
oss
is formed by the
parallel combination of the voltage dependant (non-
linear) capacitances C
ds
and C
dg
when multiplied by
the power supply input buss voltage.
Synchronous FET
The power loss equation for Q2 is approximated
by;
P
loss
= P
conduction
+ P
drive
+ P
output
*
P
loss
= I
rms
2
R
ds(on)
(
)
+ Q
g
V
g
f
(
)
+ Q
oss
2
V
in
f
+ Q
rr
V
in
f
(
)
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, R
ds(on)
is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Q
oss
and re-
verse recovery charge Q
rr
both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs' susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and V
in
. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Q
gd
/Q
gs1
must be minimized to reduce the
potential for Cdv/dt turn on.
Power MOSFET Selection for Non-Isolated DC/DC Converters
Figure A: Q
oss
Characteristic
IRF7832
www.irf.com
9
SO-8 Package Details
SO-8 Part Marking
r
9
@
i
6
6
C
F
G
'(
#(&
"
$76TD8
$"!
#
!!'#
((
%
(%'
$&#
'
!
%''
('
!##
(%
$
#'
"'
""
"$
$'
!$
#
!&76TD8
$
#
$
&$
!$
%!
$
!&
HDI
H6Y
HDGGDH@U@ST
DI8C@T
HDI
H6Y
9DH
'
r
p
&$
('
(
!$
!$76TD8
%"$76TD8
'
&
$
%
$
9
7
@
6
r
%Y
C
!$b d
6
%
&
F#$
'YG
'Yp
!$b d
8 6 7
r
6
6
'Yi
8
b#d
#
"
!
APPUQSDIU
'Y&!b!'d
%#%b!$$d
"Y !&b$d
#PVUGDI@8PIAPSHTUPE@9@8PVUGDI@HT !66
IPU@T)
9DH@ITDPIDIBUPG@S6I8DIBQ@S6TH@` #$H ((#
!8PIUSPGGDIB9DH@ITDPI)HDGGDH@U@S
"9DH@ITDPIT6S@TCPXIDIHDGGDH@U@STbDI8C@Td
$9DH@ITDPI9P@TIPUDI8GV9@HPG9QSPUSVTDPIT
%9DH@ITDPI9P@TIPUDI8GV9@HPG9QSPUSVTDPIT
HPG9QSPUSVTDPITIPUUP@Y8@@9!$b d
&9DH@ITDPIDTUC@G@IBUCPAG@69APSTPG9@SDIBUP
6TV7TUS6U@
HPG9QSPUSVTDPITIPUUP@Y8@@9 $b%d
'Y &'b&d
@Y6HQG@)UCDTDT6IDSA& HPTA@U
DIU@SI6UDPI6G
S@8UDAD@S
GPBP
)
<::
;;;;
Q6SUIVH7@S
GPU8P9@
XX2X@@F
`2G6TU9DBDUPAUC@`@6S
96U@8P9@`XX
IRF7832
10
www.irf.com
Notes:
Repetitive rating; pulse width limited by max. junction temperature.
Starting T
J
= 25C, L = 2.0mH, R
G
= 25
, I
AS
= 16A.
Pulse width
400s; duty cycle
2%.
When mounted on 1 inch square copper board.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.01/04
330.00
(12.992)
MAX.
14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
FEED DIRECTION
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
SO-8 Tape and Reel
PDF 
ZIP