IRU3021M
1
Rev. 1.4
07/24/01
TYPICAL APPLICATION
DESCRIPTION
The IRU3021M controller IC is specifically designed to
meet Intel specification for next generation microproces-
sor applications requiring multiple on-board regulators.
The IRU3021M provides a single chip controller IC for
the Vcore, three LDO controllers, one with an automatic
select pin that connects to the Type Detect pin of the
AGP slot for the AGP V
DDQ
supply, one for GTL+ and
the other for the 1.8V chip set regulator as required for
the next generation PC applications. The IRU3021M uses
N-channel MOSFET as pass transistor for Vout2(V
DDQ
),
Vout3(1.5V) and Vout4(1.8V). No external resistor di-
vider is necessary for any of the regulators. The switch-
ing regulator feature a patented topology that in combi-
nation with a few external components as shown in the
typical application circuit, will provide well in excess of
20A of output current for an on-board DC/DC converter
while automatically providing the right output voltage via
the 5-bit internal DAC .The IRU3021M also features, loss-
less current sensing for both switcher by using the R
DS(on)
of the high-side power MOSFET as the sensing resistor,
an output under-voltage shutdown that detects short cir-
cuit condition for the linear outputs and latches the sys-
tem off, and a Power Good window comparator that
switches its open collector output low when any one of
the outputs is outside of a pre-programmed window.
Provides single chip solution for Vcore, GTL+,
AGP bus, and 1.8V
Automatic voltage selection for AGP slot V
DDQ
supply
Linear Regulator Controller On-Board for 1.8V
Designed to meet Intel latest VRM specification
for next generation microprocessors
On-Board DAC programs the output voltage from
1.3V to 3.5V
Linear Regulator Controller On-Board for 1.5V
GTL+ Supply
Loss-less Short Circuit Protection for all Outputs
Synchronous operation allows maximum effi-
ciency
Patented architecture allows fixed frequency
operation as well as 100% duty cycle during
dynamic load
Minimum Part Count
Soft-Start
High current totem pole driver for direct driving of
the external Power MOSFET
Power Good function monitors all outputs
Over-Voltage Protection Circuitry Protects the
switcher output and generates a Fault output
PACKAGE ORDER INFORMATION
FEATURES
5-BIT PROGRAMMABLE SYNCHRONOUS BUCK
PLUS TRIPLE LDO CONTROLLER
APPLICATIONS
Total Power Solution for next generation Intel
processor application
T
A
(!C) DEVICE PACKAGE
0 To 70 IRU3021MCW 28-Pin Plastic SOIC WB
Data Sheet No. PD94145
3021Mapp3-1.1
LINEAR
CONTROL
LINEAR
CONTROL
SWITCHER
CONTROL
IRU3021M
Vout3
5V
Vout1
Vout4
LINEAR
CONTROL
Vout2
3.3V
Figure 1 - Typical application of the IRU3021M.
2
Rev. 1.4
07/24/01
IRU3021M
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
V5 Supply Voltage ................................................... 7V
V12 Supply Voltage .................................................. 20V
Storage Temperature Range ...................................... -65C To 150C
Operating Junction Temperature Range ..................... 0C To 125C
PACKAGE INFORMATION
28-PIN WIDE BODY PLASTIC SOIC (W)
PARAMETER SYM
TEST CONDITION
MIN
TYP
MAX
UNITS
Supply UVLO Section
UVLO Threshold-12V
Supply Ramping Up
10
V
UVLO Hysteresis-12V
0.6
V
UVLO Threshold-5V
Supply Ramping Up
4.4
V
UVLO Hysteresis-5V
0.3
V
Supply Current
Operating Supply Current
V12
6
mA
V5
30
Switching Controllers; Vcore (Vsen 1) and AGP (Vsen 2)
VID Section (Vcore only)
DAC output voltage (Note 1)
0.99Vs
Vs 1.01Vs
V
DAC Output Line Regulation
0.1
%
DAC Output Temp Variation
0.5
%
VID Input LO
0.8
V
VID Input HI
2
V
VID Input Internal Pull-Up
Resistor to V5
27
K
Vsen2 Voltage
Select<0.8V
1.5
V
Select>2V
3.3
V
Drive2
Fix
VID4
VID3
VID2
VID1
VID0
PGood
SD
Vsen2
Select
SS
Fault / Rt
Vsen4
Drive4
NC
Gnd
Drive3
Vsen3
V5
Fb
Vsen1
OCSet
PGnd
LGate
Phase
UGate
V12
4
3
2
1
25
26
27
28
14
7
6
5
15
22
23
24
TOP VIEW
13
16
12
17
11
18
10
19
9
20
8
21
Unless otherwise specified, these specifications apply over V12=12V, V5=5V and T
A
=0 to 70C. Typical values refer
to T
A
=25C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient
temperature.
JA
=80!C/W
IRU3021M
3
Rev. 1.4
07/24/01
Error Comparator Section
Input Bias Current
2
A
Input Offset Voltage
-2
+2
mV
Delay to Output
Vdiff=10mV
100
ns
Current Limit Section
CS Threshold Set Current
200
A
CS Comp Offset Voltage
-5
+5
mV
Hiccup Duty Cycle
Css=0.1F
10
%
Output Drivers Section
Rise Time
C
L
=3000pF
70
ns
Fall Time
C
L
=3000pF
70
ns
Dead Band Time Between
High Side and Synch Drive
(Vcore Switcher Only)
C
L
=3000pF
200
ns
Oscillator Section (Internal)
Osc Frequency
Rt=Open
217
KHz
1.8V Regulator (Vsen 4)
Vsense Voltage
Vo4
T
A
=25!C, Drive4=Vsen4
1.800
V
Vsense Voltage
1.800
V
Input Bias Current
2
A
Output Drive Current
Vaux - Vdrive>0.6V
50
mA
1.5V Regulator (Vsen3)
Vsense Voltage
Vo3
T
A
=25!C, Drive3=Vsen3
1.500
V
Vsense Voltage
1.500
V
Input Bias Current
2
A
Output Drive Current
Vaux - Vdrive>0.6V
50
mA
Power-Good Section
Vsen1 UV Lower Trip Point
Vsen1 Ramping Down
0.90Vs
V
Vsen1 UV Upper Trip Point
Vsen1 Ramping Up
0.92Vs
V
Vsen1 UV Hysteresis
0.02Vs
V
Vsen1 HV Upper Trip Point
Vsen1 Ramping Up
1.10Vs
V
Vsen1 HV Lower Trip Point
Vsen1 Ramping Down
1.08Vs
V
Vsen1 HV Hysterises
0.02Vs
V
Vsen2 Trip Point
Select<0.8V
1.100
V
Select>2V
2.560
V
Vsen4 Trip Point
Fix=Gnd
0.920
V
Fix=Open
1.320
V
Vsen3 Trip Point
Fix=Gnd
0.920
V
Fix=Open
1.140
V
Power Good Output LO
R
L
=3mA
0.4
V
Power Good Output HI
R
L
=5K, Pull-Up to 5V
4.8
V
Fault (Overvoltage) Section
Core OV Upper Trip Point
Vsen1 Ramping Up
1.17Vs
V
Core OV Lower Trip Point
Vsen1 Ramping Down
1.15Vs
V
FAULT Output HI
Io=3mA
10
V
Soft-Start Section
Soft-Start Current
OCSet=0V, Phase=5V
20
A
PARAMETER SYM
TEST CONDITION
MIN
TYP
MAX
UNITS
Note 1: Vs refers to the set point voltage given in Table 1.
4
Rev. 1.4
07/24/01
IRU3021M
This pin controls the gate of an external MOSFET for the AGP linear regulator.
Leaving this pin open provides fixed output voltages of the 1.5V and 1.8V for the #3 and #4
linear regulators. When this pin is grounded the reference to the linear regulators are set
to 1.26V and therefore the output of the regulators can be programmed to any voltages
above the 1.26V using: Vout=1.26 (1 + Rtop/Rbot)
Where:
Rtop = Top resistor connected from the output to the Vsense pin
Rbot = Bottom resistor connected from the Vsense pin to ground
This pin selects a range of output voltages for the DAC. When in the LOW state the range
is 1.3V to 2.05V and when it switches to HI state the range is 2.0V to 3.5V. This pin is TTL
compatible that realizes a logic "1" as either HI or Open. When left open, this pin is pulled
up internally by a 27K resistor to 5V supply.
MSB input to the DAC that programs the output voltage. This pin is TTL compatible that
realizes a logic "1" as either HI or Open. When left open, this pin is pulled up internally by
a 27K resistor to 5V supply.
Input to the DAC that programs the output voltage. This pin is TTL compatible that realizes
a logic "1" as either HI or Open. When left open, this pin is pulled up internally by a 27K
resistor to 5V supply.
Input to the DAC that programs the output voltage. This pin is TTL compatible that realizes
a logic "1" as either HI or Open. When left open, this pin is pulled up internally by a 27K
resistor to 5V supply.
LSB input to the DAC that programs the output voltage. This pin is TTL compatible that
realizes a logic "1" as either HI or Open. When left open, this pin is pulled up internally by
a 27K resistor to 5V supply.
This pin is an open collector output that switches LO when any of the outputs are outside
of the specified under-voltage trip point. It also switches low when Vsen1 pin is more than
10% above the DAC voltage setting.
PIN DESCRIPTIONS
D4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vs
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
D4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vs
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
Table 1 - Set point voltage vs. VID codes.
PIN# PIN SYMBOL PIN DESCRIPTION
1
2
3
4
5
6
7
8
Drive2
Fix
VID4
VID3
VID2
VID1
VID0
PGood
IRU3021M
5
Rev. 1.4
07/24/01
This pin provides shutdown for all the regulators. A TTL compatible, logic level high applied
to this pin disables all the outputs and discharges the soft-start capacitor. The SD signal
turns off the synchronous MOSFET allowing body diode to conduct and discharge the
output capacitor.
This pin provides the feedback for the AGP linear regulator. The Select pin when con-
nected to the "Type Detect" pin of the AGP slot automatically selects the right voltage for
the AGP V
DDQ
.
This pin provides automatic voltage selection for the AGP switching regulator. When it is
pulled LO, the voltage is 1.5V and when left open or pulled to HI, the voltage is 3.3V.
This pin provides the soft-start for all the regulators. An internal current source charges an
external capacitor that is connected from this pin to ground which ramps up the outputs of
the regulators, preventing the outputs from overshooting as well as limiting the input cur-
rent. The second function of the Soft-Start cap is to provide long off time (HICCUP) for the
synchronous MOSFET during current limiting.
This pin has dual function. It acts as an output of the over-voltage protection circuitry or it
can be used to program the frequency using an external resistor. When used as a fault
detector, if any of the switcher outputs exceed the OVP trip point, the Fault pin switches
to 12V and the soft-start cap is discharged. If the Fault pin is to be connected to any
external circuitry, it needs to be buffered.
This pin provides the feedback for the linear regulator that its output drive is Drive4.
This pin controls the gate of an external MOSFET for the 1.8V chip set linear regulator.
This pin is not connected internally.
This pin serves as the ground pin and must be connected directly to the ground plane.
This pin controls the gate of an external transistor for the 1.5V GTL+ linear regulator.
This pin provides the feedback for the linear regulator that its output drive is Drive3.
5V supply voltage. A high frequency capacitor (0.1 to 1F) must be placed close to this
pin and connected from this pin to the ground plane for noise free operation.
This pin provides the feedback for the synchronous switching regulator. Typically this pin
can be connected directly to the output of the switching regulator. However, a resistor
divider is recommended to be connected from this pin to Vout1 and ground to adjust the
output voltage for any drop in the output voltage that is caused by the trace resistance.
The value of the resistor connected from Vout1 to Fb1 must be less than 1000.
This pin is internally connected to the under-voltage and over-voltage comparators sens-
ing the Vcore status. It must be connected directly to the Vcore supply.
This pin is connected to the Drain of the power MOSFET of the Core supply and it provides
the positive sensing for the internal current sensing circuitry. An external resistor pro-
grams the current sense threshold depending on the R
DS
of the power MOSFET. An
external capacitor is placed in parallel with the programming resistor to provide high fre-
quency noise filtering.
This pin serves as the Power ground pin and must be connected directly to the ground
plane close to the source of the synchronous MOSFET. A high frequency capacitor (typi-
cally 1F) must be connected from V12 pin to this pin for noise free operation.
Output driver for the synchronous power MOSFET for the Core supply.
This pin is connected to the source of the power MOSFET for the Core supply and it
provides the negative sensing for the internal current sensing circuitry.
Output driver for the high side power MOSFET for the Core supply.
This pin is connected to the 12V supply and serves as the power Vcc pin for the output
drivers. A high frequency capacitor (typically 1F) must be placed close to this pin and
PGnd pin and be connected directly from this pin to the ground plane for the noise free
operation.
PIN# PIN SYMBOL PIN DESCRIPTION
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SD
Vsen2
Select
SS
Fault / Rt
Vsen4
Drive4
NC
Gnd
Drive3
Vsen3
V5
Fb
Vsen1
OCSet
PGnd
LGate
Phase
UGate
V12
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