www.docs.chipfind.ru
Parameter
Symbol
IRF7807
IRF7807A
Units
Drain-Source Voltage
V
DS
30
V
Gate-Source Voltage
V
GS
12
Continuous Drain or Source
25C
I
D
8.3
8.3
A
Current (V
GS
4.5V)
70C
6.6
6.6
Pulsed Drain Current
I
DM
66
66
Power Dissipation
25C
P
D
2.5
W
70C
1.6
Junction & Storage Temperature Range
T
J
,
T
STG
55 to 150
C
Continuous Source Current (Body Diode)
I
S
2.5
2.5
A
Pulsed source Current
I
SM
66
66
N Channel Application Specific MOSFETs
Ideal for Mobile DC-DC Converters
Low Conduction Losses
Low Switching Losses
Description
These new devices employ advanced HEXFET Power
MOSFET technology to achieve an unprecedented
balance of on-resistance and gate charge. The
reduced conduction and switching losses make them
ideal for high efficiency DC-DC Converters that power
the latest generation of mobile microprocessors.
A pair of IRF7807 devices provides the best cost/
performance solution for system voltages, such as 3.3V
and 5V.
HEXFET
Chip-Set for DC-DC Converters
Absolute Maximum Ratings
Parameter
Max.
Units
Maximum Junction-to-Ambient
R
JA
50
C/W
Thermal Resistance
T o p V ie w
8
1
2
3
4
5
6
7
D
D
D
D
G
S
A
S
S
IRF7807/IRF7807A
www.irf.com
1
10/10/00
SO-8
IRF7807 IRF7807A
Vds
30V
30V
Rds(on) 25m
25m
Qg
17nC
17nC
Qsw
5.2nC
Qoss
16.8nC
16.8nC
Device Features
PD 91747C
www.irf.com
2
IRF7807/IRF7807A
Parameter
Min
Typ
Max
Min
Typ
Max Units
Conditions
Diode Forward
V
SD
1.2
1.2
V
I
S
= 7A
, V
GS
= 0V
Voltage*
Reverse Recovery
Q
rr
80
80
nC
di/dt = 700A/s
Charge
V
DS
= 16V, V
GS
= 0V, I
S
= 7A
Reverse Recovery
Q
rr(s)
50
50
Charge (with Parallel
Schotkky)
Parameter
Min Typ Max
Min
Typ Max Units
Conditions
Drain-to-Source
V
(BR)DSS
30
30
V
V
GS
= 0V, I
D
= 250A
Breakdown Voltage*
Static Drain-Source
R
DS
(on)
17
25
17
25
m
V
GS
= 4.5V, I
D
= 7A
on Resistance*
Gate Threshold Voltage*
V
GS
(th)
1.0
1.0
V
V
DS
= V
GS
, I
D
= 250A
Drain-Source Leakage
I
DSS
30
30
A
V
DS
= 24V, V
GS
= 0
150
150
V
DS
= 24V, V
GS
= 0,
Tj = 100C
Gate-Source Leakage
I
GSS
100
100
nA
V
GS
= 12V
Current*
Total Gate Charge*
Q
g
12
17
12
17
V
GS
= 5V, I
D
= 7A
Pre-Vth
Q
gs1
2.1
2.1
V
DS
= 16V, I
D
= 7A
Gate-Source Charge
Post-Vth
Q
gs2
0.76
0.76
nC
Gate-Source Charge
Gate to Drain Charge
Q
gd
2.9
2.9
Switch Charge*
Q
SW
3.66
5.2
3.66
(Q
gs2
+ Q
gd
)
Output Charge*
Q
oss
14
16.8
14
16.8
V
DS
= 16V, V
GS
= 0
Gate Resistance
R
g
1.2
1.2
Turn-on Delay Time
t
d
(on)
12
12
V
DD
= 16V
Rise Time
t
r
17
17
ns
I
D
= 7A
Turn-off Delay Time
t
d
(off)
25
25
R
g
= 2
Fall Time
t
f
6
6
V
GS
= 4.5V
Resistive Load
Electrical Characteristics
Source-Drain Rating & Characteristics
Notes:
Repetitive rating; pulse width limited by max. junction temperature.
Pulse width
300 s; duty cycle
2%.
When mounted on 1 inch square copper board, t < 10 sec.
Typ = measured - Q
oss
*
Devices are 100% tested to these parameters.
IRF7807
IRF7807A
Current*
di/dt = 700A/s
(with 10BQ040)
V
DS
= 16V, V
GS
= 0V, I
S
= 7A
www.irf.com
3
IRF7807/IRF7807A
Control FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called the
Control FET, are impacted by the R
ds(on)
of the MOSFET,
but these conduction losses are only about one half of
the total losses.
Power losses in the control switch Q1 are given by;
P
loss
= P
conduction
+ P
switching
+ P
drive
+ P
output
This can be expanded and approximated by;
P
loss
=
I
rms
2
R
ds(on )
(
)
+
I
Q
gd
i
g
V
in
f
+
I
Q
gs2
i
g
V
in
f
+
Q
g
V
g
f
(
)
+
Q
oss
2
V
in
f
This simplified loss equation includes the terms Q
gs2
and Q
oss
which are new to Power MOSFET data sheets.
Q
gs2
is a sub element of traditional gate-source charge
that is included in all MOSFET data sheets. The impor-
tance of splitting this gate-source charge into two sub
elements, Q
gs1
and Q
gs2
, can be seen from Fig 1.
Q
gs2
indicates the charge that must be supplied by
the gate driver between the time that the threshold volt-
age has been reached (t1) and the time the drain cur-
rent rises to I
dmax
(t2) at which time the drain voltage
begins to change. Minimizing Q
gs2
is a critical factor in
reducing switching losses in Q1.
Q
oss
is the charge that must be supplied to the output
capacitance of the MOSFET during every switching
cycle. Figure 2 shows how Q
oss
is formed by the paral-
lel combination of the voltage dependant (non-linear)
capacitance's C
ds
and C
dg
when multiplied by the power
supply input buss voltage.
Figure 1: Typical MOSFET switching waveform
Synchronous FET
The power loss equation for Q2 is approximated
by;
P
loss
=
P
conduction
+
P
drive
+
P
output
*
P
loss
=
I
rms
2
R
ds(on)
(
)
+
Q
g
V
g
f
(
)
+
Q
oss
2
V
in
f
+
Q
rr
V
in
f
(
)
*dissipated primarily in Q1.
Power MOSFET Selection for DC/DC
Converters
4
1
2
Drain Current
Gate Voltage
Drain Voltage
t3
t2
t1
V
GTH
Q
GS1
Q
GS2
Q
GD
t0
www.irf.com
4
IRF7807/IRF7807A
5V Supply : Q1=Q2=IRF7807
89
90
91
92
93
94
95
1
1.5
2
2.5
3
3.5
4
4.5
5
Load Current (A)
Efficiency (%)
Vin = 10V
Vin = 14V
Vin=24V
Typical Mobile PC Application
The performance of these new devices has been tested
in circuit and correlates well with performance predic-
tions generated by the system models. An advantage
of this new technology platform is that the MOSFETs
it produces are suitable for both control FET and syn-
chronous FET applications. This has been demon-
strated with the 3.3V and 5V converters. (Fig 3 and
Fig 4). In these applications the same MOSFET IRF7807
was used for both the control FET (Q1) and the syn-
chronous FET (Q2). This provides a highly effective
cost/performance solution.
3.3V Supply : Q1=Q2=IRF7807
84
85
86
87
88
89
90
91
92
93
1
1.5
2
2.5
3
3.5
4
4.5
5
Load Current (A)
Efficiency (%)
Vin = 10V
Vin = 14V
Vin = 24V
Figure 3
Figure 4
Figure 2: Q
oss
Characteristic
For the synchronous MOSFET Q2, R
ds(on)
is an im-
portant characteristic; however, once again the impor-
tance of gate charge must not be overlooked since it
impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Q
oss
and re-
verse recovery charge Q
rr
both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs' susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and V
in
. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Q
gd
/Q
gs1
must be minimized to reduce the
potential for Cdv/dt turn on.
Spice model for IRF7807 can be downloaded in ma-
chine readable format at www.irf.com.
www.irf.com
5
IRF7807/IRF7807A
Figure 9. Typical Rds(on) vs. Gate-to-Source Voltage
Figure 7. Typical Gate Charge vs. Gate-to-Source Voltage
Figure 5. Normalized On-Resistance vs. Temperature
Figure 10. Typical Rds(on) vs. Gate-to-Source Voltage
Figure 8. Typical Gate Charge vs. Gate-to-Source Voltage
Figure 6. Normalized On-Resistance vs. Temperature
IRF7807
IRF7807A
Typical Characteristics
PDF 
ZIP