01/12/99
IRFIB6N60A
SMPS
MOSFET
HEXFET
Power MOSFET
l
Switch Mode Power Supply ( SMPS )
l
Uninterruptable Power Supply
l
High speed power switching
l
High Voltage Isolation = 2.5KVRMS
Benefits
Applications
l
Low Gate Charge Qg results in Simple
Drive Requirement
l
Improved Gate, Avalanche and dynamic
dv/dt Ruggedness
l
Fully Characterized Capacitance and
Avalanche Voltage and Current
V
DSS
Rds(on) max
I
D
600V
0.75
W
5.5A
Typical SMPS Topologies:
l
Single Transistor Forward
Notes
through
are on page 8
S
D
G
l
Active Clamped Forward
TO-220 FULLPAK
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1
Parameter
Max.
Units
I
D
@ T
C
= 25C
Continuous Drain Current, V
GS
@ 10V
5.5
I
D
@ T
C
= 100C
Continuous Drain Current, V
GS
@ 10V
3.5
A
I
DM
Pulsed Drain Current
37
P
D
@T
C
= 25C
Power Dissipation
60
W
Linear Derating Factor
0.48
W/C
V
GS
Gate-to-Source Voltage
30
V
dv/dt
Peak Diode Recovery dv/dt
5.0
V/ns
T
J
Operating Junction and
-55 to + 150
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
300 (1.6mm from case )
C
Mounting torqe, 6-32 or M3 screw 10 lbfin (1.1Nm)
Absolute Maximum Ratings
PD - 91813
IRFIB6N60A
2
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Parameter
Min. Typ. Max. Units
Conditions
g
fs
Forward Transconductance
5.5
S
V
DS
= 25V, I
D
= 5.5A
Q
g
Total Gate Charge
49 I
D
= 9.2A
Q
gs
Gate-to-Source Charge
13
nC
V
DS
= 400V
Q
gd
Gate-to-Drain ("Miller") Charge
20
V
GS
= 10V, See Fig. 6 and 13
t
d(on)
Turn-On Delay Time
13
V
DD
= 300V
t
r
Rise Time
25
I
D
= 9.2A
t
d(off)
Turn-Off Delay Time
30
R
G
= 9.1
W
t
f
Fall Time
22
R
D
= 35.5
W
,See Fig. 10
C
iss
Input Capacitance
1400
V
GS
= 0V
C
oss
Output Capacitance
180
V
DS
= 25V
C
rss
Reverse Transfer Capacitance
7.1
pF
= 1.0MHz, See Fig. 5
C
oss
Output Capacitance
1957
V
GS
= 0V, V
DS
= 1.0V, = 1.0MHz
C
oss
Output Capacitance
49
V
GS
= 0V, V
DS
= 480V, = 1.0MHz
C
oss
eff.
Effective Output Capacitance
96
V
GS
= 0V, V
DS
= 0V to 480V
Parameter
Min. Typ. Max. Units
Conditions
V
(BR)DSS
Drain-to-Source Breakdown Voltage
600
V
V
GS
= 0V, I
D
= 250A
R
DS(on)
Static Drain-to-Source On-Resistance
0.75
W
V
GS
= 10V, I
D
= 3.3A
V
GS(th)
Gate Threshold Voltage
2.0
4.0
V
V
DS
= V
GS
, I
D
= 250A
25
A
V
DS
= 600V, V
GS
= 0V
250
V
DS
= 480V, V
GS
= 0V, T
J
= 150C
Gate-to-Source Forward Leakage
100
V
GS
= 30V
Gate-to-Source Reverse Leakage
-100
nA
V
GS
= -30V
Static @ T
J
= 25C (unless otherwise specified)
I
GSS
I
DSS
Drain-to-Source Leakage Current
Dynamic @ T
J
= 25C (unless otherwise specified)
ns
Parameter
Typ.
Max.
Units
E
AS
Single Pulse Avalanche Energy
290
mJ
I
AR
Avalanche Current
9.2
A
E
AR
Repetitive Avalanche Energy
6.0
mJ
Avalanche Characteristics
S
D
G
Parameter
Min. Typ. Max. Units
Conditions
I
S
Continuous Source Current
MOSFET symbol
(Body Diode)
showing the
I
SM
Pulsed Source Current
integral reverse
(Body Diode)
p-n junction diode.
V
SD
Diode Forward Voltage
1.5
V
T
J
= 25C, I
S
= 9.2A, V
GS
= 0V
t
rr
Reverse Recovery Time
530
800
ns
T
J
= 25C, I
F
= 9.2A
Q
rr
Reverse RecoveryCharge
3.0
4.4
C
di/dt = 100A/s
t
on
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
Diode Characteristics
5.5
37
A
Thermal Resistance
Parameter
Typ.
Max.
Units
R
q
JC
Junction-to-Case
2.1
R
q
JA
Junction-to-Ambient
65
C/W
IRFIB6N60A
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3
Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
0.1
1
10
100
0.1
1
10
100
20s PULSE WIDTH
T = 25 C
J
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.7V
V , Drain-to-Source Voltage (V)
I , Drain-to-Source Current (A)
DS
D
4.7V
1
10
100
1
10
100
20s PULSE WIDTH
T = 150 C
J
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.7V
V , Drain-to-Source Voltage (V)
I , Drain-to-Source Current (A)
DS
D
4.7V
0.1
1
10
100
4.0
5.0
6.0
7.0
8.0
9.0
10.0
V = 50V
20s PULSE WIDTH
DS
V , Gate-to-Source Voltage (V)
I , Drain-to-Source Current (A)
GS
D
T = 25 C
J
T = 150 C
J
-60 -40 -20
0
20
40
60
80 100 120 140 160
0.0
0.5
1.0
1.5
2.0
2.5
3.0
T , Junction Temperature ( C)
R , Drain-to-Source On Resistance
(Normalized)
J
D
S
(
on)
V
=
I =
GS
D
10V
9.2A
IRFIB6N60A
4
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
0
10
20
30
40
50
0
4
8
12
16
20
Q , Total Gate Charge (nC)
V , G
a
te-to-Source Vol
t
age (V)
G
GS
FOR TEST CIRCUIT
SEE FIGURE
I =
D
13
9.2A
V
= 120V
DS
V
= 300V
DS
V
= 480V
DS
0.1
1
10
100
0.2
0.5
0.7
1.0
1.2
V ,Source-to-Drain Voltage (V)
I , Reverse Drain Current (A)
SD
SD
V = 0 V
GS
T = 25 C
J
T = 150 C
J
0
400
800
1200
1600
2000
2400
1
10
100
1000
C
,
Ca
pa
c
i
t
a
n
c
e (
p
F
)
DS
V , Drain-to-Source Voltage (V)
A
V = 0V, f = 1MHz
C = C + C , C SHORTED
C = C
C = C + C
GS
iss gs gd ds
rss gd
oss ds gd
C
iss
C
oss
C
rss
400V
0.1
1
10
100
1000
10
100
1000
10000
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
Single Pulse
T
T
= 150 C
= 25 C
J
C
V , Drain-to-Source Voltage (V)
I , Drain Current (A)
I , Drain Current (A)
DS
D
10us
100us
1ms
10ms
IRFIB6N60A
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5
0.01
0.1
1
10
0.00001
0.0001
0.001
0.01
0.1
1
10
Notes:
1. Duty factor D =
t / t
2. Peak T = P
x Z
+ T
1
2
J
DM
thJC
C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Ther
m
a
l
R
e
sponse
(Z
)
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
Fig 10a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig 10b. Switching Time Waveforms
V
DS
Pulse Width 1 s
Duty Factor 0.1 %
R
D
V
GS
R
G
D.U.T.
10V
+
-
V
DD
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
25
50
75
100
125
150
0.0
1.0
2.0
3.0
4.0
5.0
6.0
T , Case Temperature ( C)
I , Drain Current (A)
C
D
IRFIB6N60A
6
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Q
G
Q
GS
Q
GD
V
G
Charge
D.U.T.
V
DS
I
D
I
G
3mA
V
GS
.3
F
50K
.2
F
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
R G
IAS
0.01
tp
D.U.T
L
VDS
+
-
VDD
DRIVER
A
15V
20V
25
50
75
100
125
150
0
100
200
300
400
500
600
Starting T , Junction Temperature ( C)
E
,
S
i
ngl
e P
u
l
s
e A
v
al
anche E
ner
gy (
m
J)
J
AS
ID
TOP
BOTTOM
4.1A
5.8A
9.2A
IRFIB6N60A
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7
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple
5%
Body Diode
Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D =
P.W.
Period
+
-
+
+
+
-
-
-
Fig 14. For N-Channel HEXFETS
*
V
GS
= 5V for Logic Level Devices
Peak Diode Recovery dv/dt Test Circuit
R
G
V
DD
dv/dt controlled by R
G
Driver same type as D.U.T.
I
SD
controlled by Duty Factor "D"
D.U.T. - Device Under Test
D.U.T
Circuit Layout Considerations
Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer
*
IRFIB6N60A
8
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Part Marking Information
TO-220 Fullpak
Package Outline
TO-220 Fullpak Outline
Dimensions are shown in millimeters (inches)
LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SOURCE
NOTES:
1 DIMENSIONING & TOLERANCING
PER ANSI Y14.5M, 1982
2 CONTROLLING DIMENSION: INCH.
D
C
A
B
MINIMUM CREEPAGE
DISTANCE BETWEEN
A-B-C-D = 4.80 (.189)
3X
2.85 (.112)
2.65 (.104)
2.80 (.110)
2.60 (.102)
4.80 (.189)
4.60 (.181)
7.10 (.280)
6.70 (.263)
3.40 (.133)
3.10 (.123)
- A -
3.70 (.145)
3.20 (.126)
1.15 (.045)
MIN.
3.30 (.130)
3.10 (.122)
- B -
0.90 (.035)
0.70 (.028)
3X
0.25 (.010)
M
A M B
2.54 (.100)
2X
3X
13.70 (.540)
13.50 (.530)
16.00 (.630)
15.80 (.622)
1 2 3
10.60 (.417)
10.40 (.409)
1.40 (.055)
1.05 (.042)
0.48 (.019)
0.44 (.017)
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
DATE CODE
(YYWW)
YY = YEAR
WW = WEEK
ASSEMBLY
LOT CODE
E401 9245
IRFI840G
EXAMPLE : THIS IS AN IRFI840G
WITH ASSEMBLY
LOT CODE E401
A
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
IR GREAT BRITAIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
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IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111
IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086
IR SOUTHEAST ASIA: 1 Kim Seng Promenade, Great World City West Tower, 13-11, Singapore 237994 Tel: ++ 65 838 4630
IR TAIWAN:16 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 10673, Taiwan Tel: 886-2-2377-9936
http://www.irf.com/ Data and specifications subject to change without notice. 5/99
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
I
SD
9.2A, di/dt
50A/s, V
DD
V
(BR)DSS
,
T
J
150C
Notes:
Starting T
J
= 25C, L = 6.8mH
R
G
= 25
W
, I
AS
= 9.2A. (See Figure 12)
Pulse width
300s; duty cycle
2%.
C
oss
eff. is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
t=60s, f=60Hz
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