09/12/03
www.irf.com
1
HEXFET
is a registered trademark of International Rectifier.
IRFZ46Z
IRFZ46ZS
IRFZ46ZL
HEXFET
Power MOSFET
S
D
G
V
DSS
= 55V
R
DS(on)
= 13.6m
I
D
= 51A
Features
Advanced Process Technology
Ultra Low On-Resistance
Dynamic dv/dt Rating
175C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
AUTOMOTIVE MOSFET
PD - 94769
Description
Specifically designed for Automotive applica-
tions, this HEXFET
Power MOSFET utilizes the
latest processing techniques to achieve extremely
low on-resistance per silicon area. Additional
features of this design are a 175C junction
operating temperature, fast switching speed and
improved repetitive avalanche rating . These
features combine to make this design an ex-
tremely efficient and reliable device for use in
Automotive applications and a wide variety of
other applications.
D
2
Pak
IRFZ46ZS
TO-220AB
IRFZ46Z
TO-262
IRFZ46ZL
Absolute Maximum Ratings
Parameter
Units
I
D
@ T
C
= 25C
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
A
I
D
@ T
C
= 100C
Continuous Drain Current, V
GS
@ 10V (See Fig. 9)
I
DM
Pulsed Drain Current
c
P
D
@T
C
= 25C
Maximum Power Dissipation
W
Linear Derating Factor
W/C
V
GS
Gate-to-Source Voltage
V
E
AS
Single Pulse Avalanche Energy (Thermally Limited)
d
mJ
E
AS
(tested)
Single Pulse Avalanche Energy Tested Value
i
I
AR
Avalanche Current
c
A
E
AR
Repetitive Avalanche Energy
h
mJ
T
J
Operating Junction and
C
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw
Thermal Resistance
Parameter
Typ.
Max.
Units
R
JC
Junction-to-Case
1.84
C/W
R
CS
Case-to-Sink, Flat, Greased Surface
0.50
R
JA
Junction-to-Ambient
62
R
JA
Junction-to-Ambient (PCB Mount, steady state)
j
40
10 lbfin (1.1Nm)
82
0.54
20
63
97
See Fig.12a,12b,15,16
300 (1.6mm from case )
-55 to + 175
Max.
51
36
200
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2
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Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Limited by T
Jmax
, starting T
J
= 25C, L =0.13mH,
R
G
= 25
, I
AS
= 31A, V
GS
=10V. Part not
recommended for use above this value.
I
SD
31A, di/dt
1070A/s, V
DD
V
(BR)DSS
,
T
J
175C.
Pulse width
1.0ms; duty cycle
2%.
C
oss
eff. is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
Limited by T
Jmax
, see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
This value determined from sample failure population. 100%
tested to this value in production.
This is applied to D
2
Pak, when mounted on 1" square PCB
( FR-4 or G-10 Material ). For recommended footprint and
soldering techniques refer to application note #AN-994.
S
D
G
S
D
G
Static @ T
J
= 25C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
V
(BR)DSS
Drain-to-Source Breakdown Voltage
55
V
V
DSS
/
T
J
Breakdown Voltage Temp. Coefficient
0.053
V/C
R
DS(on)
Static Drain-to-Source On-Resistance
10.9
13.6
m
V
GS(th)
Gate Threshold Voltage
2.0
4.0
V
gfs
Forward Transconductance
45
S
I
DSS
Drain-to-Source Leakage Current
20
A
250
I
GSS
Gate-to-Source Forward Leakage
200
nA
Gate-to-Source Reverse Leakage
-200
Q
g
Total Gate Charge
31
46
nC
Q
gs
Gate-to-Source Charge
7.6
11
Q
gd
Gate-to-Drain ("Miller") Charge
12
18
t
d(on)
Turn-On Delay Time
13
ns
t
r
Rise Time
63
t
d(off)
Turn-Off Delay Time
37
t
f
Fall Time
39
L
D
Internal Drain Inductance
4.5
nH
Between lead,
6mm (0.25in.)
L
S
Internal Source Inductance
7.5
from package
and center of die contact
C
iss
Input Capacitance
1460
pF
C
oss
Output Capacitance
250
C
rss
Reverse Transfer Capacitance
130
C
oss
Output Capacitance
860
C
oss
Output Capacitance
190
C
oss
eff.
Effective Output Capacitance
310
Diode Characteristics
Parameter
Min. Typ. Max. Units
I
S
Continuous Source Current
51
(Body Diode)
A
I
SM
Pulsed Source Current
200
(Body Diode)
V
SD
Diode Forward Voltage
1.3
V
t
rr
Reverse Recovery Time
21
31
ns
Q
rr
Reverse Recovery Charge
16
24
nC
t
on
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Conditions
V
GS
= 0V, I
D
= 250A
Reference to 25C, I
D
= 1mA
V
GS
= 10V, I
D
= 31A
f
V
DS
= V
GS
, I
D
= 250A
V
DS
= 55V, V
GS
= 0V
V
DS
= 55V, V
GS
= 0V, T
J
= 125C
R
G
= 15
I
D
= 31A
V
DS
= 25V, I
D
= 31A
V
DD
= 28V
I
D
= 31A
V
GS
= 20V
V
GS
= -20V
T
J
= 25C, I
F
= 31A, V
DD
= 28V
di/dt = 100A/s
f
T
J
= 25C, I
S
= 31A, V
GS
= 0V
f
showing the
integral reverse
p-n junction diode.
MOSFET symbol
V
GS
= 0V
V
DS
= 25V
V
GS
= 0V, V
DS
= 44V, = 1.0MHz
Conditions
V
GS
= 0V, V
DS
= 0V to 44V
V
DS
= 44V
V
GS
= 10V
f
= 1.0MHz, See Fig. 5
V
GS
= 0V, V
DS
= 1.0V, = 1.0MHz
V
GS
= 10V
f
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3
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
Fig 4. Typical Forward Transconductance
vs. Drain Current
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
I D
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
C
u
r
r
e
n
t
(
A
)
VGS
TOP
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM
4.5V
20s PULSE WIDTH
Tj = 25C
4.5V
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
I D
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
C
u
r
r
e
n
t
(
A
)
20s PULSE WIDTH
Tj = 175C
4.5V
VGS
TOP
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM
4.5V
4
5
6
7
8
9
10
VGS, Gate-to-Source Voltage (V)
1.0
10
100
1000
I D
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
C
u
r
r
e
n
t
(
)
TJ = 25C
TJ = 175C
VDS = 15V
20s PULSE WIDTH
0
10
20
30
40
50
60
ID,Drain-to-Source Current (A)
0
10
20
30
40
50
60
G
f
s,
F
o
r
w
a
r
d
T
r
a
n
s
c
o
n
d
u
c
t
a
n
c
e
(
S
)
TJ = 25C
TJ = 175C
VDS = 10V
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4
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
1
10
100
VDS, Drain-to-Source Voltage (V)
100
1000
10000
C
,
C
a
p
a
c
i
t
a
n
c
e
(
p
F
)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0
5
10
15
20
25
30
35
QG Total Gate Charge (nC)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
V
G
S
,
G
a
t
e
-
t
o
-
S
o
u
r
c
e
V
o
l
t
a
g
e
(
V
)
VDS= 44V
VDS= 28V
VDS= 11V
ID= 31A
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VSD, Source-to-Drain Voltage (V)
0.10
1.00
10.00
100.00
1000.00
I S
D
,
R
e
v
e
r
s
e
D
r
a
i
n
C
u
r
r
e
n
t
(
A
)
TJ = 25C
TJ = 175C
VGS = 0V
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
I D
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
C
u
r
r
e
n
t
(
A
)
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100sec
Tc = 25C
Tj = 175C
Single Pulse
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5
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Normalized On-Resistance
vs. Temperature
25
50
75
100
125
150
175
TC , Case Temperature (C)
0
5
10
15
20
25
30
35
40
45
50
55
I D
,
D
r
a
i
n
C
u
r
r
e
n
t
(
A
)
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (C)
0.5
1.0
1.5
2.0
2.5
R
D
S
(
o
n
)
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
O
n
R
e
s
i
s
t
a
n
c
e
(
N
o
r
m
a
l
i
z
e
d
)
ID = 31A
VGS = 10V
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
10
T
h
e
r
m
a
l
R
e
s
p
o
n
s
e
(
Z
t
h
J
C
)
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Ri (C/W)
i (sec)
0.9322 0.000357
0.5533 0.001133
0.3545 0.004091
J
J
1
1
2
2
3
3
R
1
R
1
R
2
R
2
R
3
R
3
C
Ci i
/
Ri
Ci=
i
/
Ri
IRFZ46Z/S/L
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Q
G
Q
GS
Q
GD
V
G
Charge
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 14. Threshold Voltage vs. Temperature
RG
IAS
0.01
tp
D.U.T
L
VDS
+
- VDD
DRIVER
A
15V
20V
V
GS
1K
VCC
DUT
0
L
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (C)
0
50
100
150
200
250
300
E
A
S
,
S
i
n
g
l
e
P
u
l
s
e
A
v
a
l
a
n
c
h
e
E
n
e
r
g
y
(
m
J
)
ID
TOP 3.5A
5.0A
BOTTOM 31A
-75 -50 -25
0
25 50 75 100 125 150 175 200
TJ , Temperature ( C )
1.0
2.0
3.0
4.0
V
G
S
(
t
h
)
G
a
t
e
t
h
r
e
s
h
o
l
d
V
o
l
t
a
g
e
(
V
)
ID = 250A
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7
Fig 15. Typical Avalanche Current vs.Pulsewidth
Fig 16. Maximum Avalanche Energy
vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T
jmax
. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. P
D (ave)
= Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I
av
= Allowable avalanche current.
7.
T
=
Allowable rise in junction temperature, not to exceed
T
jmax
(assumed as 25C in Figure 15, 16).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
f
Z
thJC
(D, t
av
) = Transient thermal resistance, see figure 11)
P
D (ave)
= 1/2 ( 1.3BVI
av
) =
D
T/ Z
thJC
I
av
=
2
D
T/ [1.3BVZ
th
]
E
AS (AR)
= P
D (ave)
t
av
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
0.1
1
10
100
1000
A
v
a
l
a
n
c
h
e
C
u
r
r
e
n
t
(
A
)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming
Tj = 25C due to
avalanche losses
0.01
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (C)
0
10
20
30
40
50
60
70
E
A
R
,
A
v
a
l
a
n
c
h
e
E
n
e
r
g
y
(
m
J
)
TOP Single Pulse
BOTTOM 1% Duty Cycle
ID = 31A
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8
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Fig 17.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
Power MOSFETs
Circuit Layout Considerations
Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple
5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D =
P.W.
Period
*
V
GS
= 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
R
G
V
DD
dv/dt controlled by R
G
Driver same type as D.U.T.
I
SD
controlled by Duty Factor "D"
D.U.T. - Device Under Test
D.U.T
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
V
DS
Pulse Width 1 s
Duty Factor 0.1 %
R
D
V
GS
R
G
D.U.T.
10V
+
-
V
DD
Fig 18a. Switching Time Test Circuit
Fig 18b. Switching Time Waveforms
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9
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
- B -
1.32 (.052)
1.22 (.048)
3X
0.55 (.022)
0.46 (.018)
2.92 (.115)
2.64 (.104)
4.69 (.185)
4.20 (.165)
3X
0.93 (.037)
0.69 (.027)
4.06 (.160)
3.55 (.140)
1.15 (.045)
MIN
6.47 (.255)
6.10 (.240)
3.78 (.149)
3.54 (.139)
- A -
10.54 (.415)
10.29 (.405)
2.87 (.113)
2.62 (.103)
15.24 (.600)
14.84 (.584)
14.09 (.555)
13.47 (.530)
3X
1.40 (.055)
1.15 (.045)
2.54 (.100)
2X
0.36 (.014) M B A M
4
1 2 3
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
EXAMPLE:
IN THE ASSEMBLY LINE "C"
THIS IS AN IRF1010
LOT CODE 1789
ASSEMBLED ON WW 19, 1997
PART NUMBER
ASSEMBLY
LOT CODE
DAT E CODE
YEAR 7 = 1997
LINE C
WEEK 19
LOGO
RECTIFIER
INTERNATIONAL
EXAMPLE: THIS IS AN IRF1010
LOT CODE 1789
ASSEMBLED ON WW 19, 1997
IN THE ASSEMBLY LINE "C"
INTERNATIONAL
RECTIFIER
LOGO
LOT CODE
PART NUMBER
DATE CODE
For GB Production
IRFZ46Z/S/L
10
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D
2
Pak Part Marking Information
F530S
THIS IS AN IRF530S WITH
LOT CODE 8024
ASSEMBLED ON WW 02, 2000
IN THE ASSEMBLY LINE "L"
ASSEMBLY
LOT CODE
INTERNATIONAL
RECTIFIER
LOGO
PART NUMBER
DATE CODE
YEAR 0 = 2000
WEEK 02
LINE L
DATE CODE
IN THE ASS EMBLY LINE "L"
ASS EMBLED ON WW 02, 2000
THIS IS AN IRF530S WITH
LOT CODE 8024
INTERNATIONAL
LOGO
RECTIFIER
LOT CODE
PART NUMBER
F530S
For GB Production
D
2
Pak Package Outline
Dimensions are shown in millimeters (inches)
IRFZ46Z/S/L
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11
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
EXAMPLE: T HIS IS AN IRL3103L
LOT CODE 1789
AS SEMBLY
PART NUMBER
DATE CODE
WEEK 19
LINE C
LOT CODE
YEAR 7 = 1997
ASS EMBLED ON WW 19, 1997
IN THE ASS EMBLY LINE "C"
LOGO
RECTIFIER
INT ERNATIONAL
IGBT
1- GATE
2- COLLECTOR
3- EMITTER
IRFZ46Z/S/L
12
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Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101]
market.
Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 09/03
TO-220AB package is not recommended for Surface Mount Application.
D
2
Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
3
4
4
TRR
FEED DIRECTION
1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
TRL
FEED DIRECTION
10.90 (.429)
10.70 (.421)
16.10 (.634)
15.90 (.626)
1.75 (.069)
1.25 (.049)
11.60 (.457)
11.40 (.449)
15.42 (.609)
15.22 (.601)
4.72 (.136)
4.52 (.178)
24.30 (.957)
23.90 (.941)
0.368 (.0145)
0.342 (.0135)
1.60 (.063)
1.50 (.059)
13.50 (.532)
12.80 (.504)
330.00
(14.173)
MAX.
27.40 (1.079)
23.90 (.941)
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
26.40 (1.039)
24.40 (.961)
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
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