www.docs.chipfind.ru
IRL540NS/L
HEXFET
Power MOSFET
PD -91535
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power MOSFETs
are well known for, provides the designer with an extremely
efficient and reliable device for use in a wide variety of
applications.
The D
2
Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible on-
resistance in any existing surface mount package. The
D
2
Pak is suitable for high current applications because of
its low internal connection resistance and can dissipate up
to 2.0W in a typical surface mount application.
The through-hole version (IRF540NL) is available for low-
profile applications.
S
D
G
V
DSS
= 100V
R
DS(on)
= 0.044
I
D
= 36A
Description
5/13/98
Parameter
Typ.
Max.
Units
R
JC
Junction-to-Case
1.1
R
JA
Junction-to-Ambient ( PCB Mounted,steady-state)**
40
Thermal Resistance
C/W
Parameter
Max.
Units
I
D
@ T
C
= 25C
Continuous Drain Current, V
GS
@ 10V
36
I
D
@ T
C
= 100C
Continuous Drain Current, V
GS
@ 10V
26
A
I
DM
Pulsed Drain Current
120
P
D
@T
A
= 25C
Power Dissipation
3.8
W
P
D
@T
C
= 25C
Power Dissipation
140
W
Linear Derating Factor
0.91
W/C
V
GS
Gate-to-Source Voltage
16
V
E
AS
Single Pulse Avalanche Energy
310
mJ
I
AR
Avalanche Current
18
A
E
AR
Repetitive Avalanche Energy
14
mJ
dv/dt
Peak Diode Recovery dv/dt
5.0
V/ns
T
J
Operating Junction and
-55 to + 175
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
300 (1.6mm from case )
C
Absolute Maximum Ratings
2
D P ak
T O -26 2
l
Advanced Process Technology
l
Surface Mount (IRL540NS)
l
Low-profile through-hole (IRL540NL)
l
175C Operating Temperature
l
Fast Switching
l
Fully Avalanche Rated
IRL540NS/L
Parameter
Min. Typ. Max. Units
Conditions
I
S
Continuous Source Current
MOSFET symbol
(Body Diode)
showing the
I
SM
Pulsed Source Current
integral reverse
(Body Diode)
p-n junction diode.
V
SD
Diode Forward Voltage
1.3
V
T
J
= 25C, I
S
= 18A, V
GS
= 0V
t
rr
Reverse Recovery Time
190
290
ns
T
J
= 25C, I
F
= 18A
Q
rr
Reverse RecoveryCharge
1.1
1.7
C
di/dt = 100A/s
t
on
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
Starting T
J
= 25C, L = 1.9mH
R
G
= 25
, I
AS
= 18A. (See Figure 12)
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Notes:
I
SD
18A, di/dt
180A/s, V
DD
V
(BR)DSS
,
T
J
175C
Pulse width
300s; duty cycle
2%.
Uses IRL540N data and test conditions
** When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended soldering techniques refer to application note #AN-994.
S
D
G
Source-Drain Ratings and Characteristics
36
120
A
Parameter
Min. Typ. Max. Units
Conditions
V
(BR)DSS
Drain-to-Source Breakdown Voltage
100
V
V
GS
= 0V, I
D
= 250A
V
(BR)DSS
/
T
J
Breakdown Voltage Temp. Coefficient
0.11
V/C
Reference to 25C, I
D
= 1mA
0.044
V
GS
= 10V, I
D
= 18A
0.053
V
GS
= 5.0V, I
D
= 18A
0.063
V
GS
= 4.0V, I
D
= 15A
V
GS(th)
Gate Threshold Voltage
1.0
2.0
V
V
DS
= V
GS
, I
D
= 250A
g
fs
Forward Transconductance
14
S
V
DS
= 25V, I
D
= 18A
25
V
DS
= 100V, V
GS
= 0V
250
V
DS
= 80V, V
GS
= 0V, T
J
= 150C
Gate-to-Source Forward Leakage
100
nA
V
GS
= 16V
Gate-to-Source Reverse Leakage
-100
V
GS
= -16V
Q
g
Total Gate Charge
74
I
D
= 18A
Q
gs
Gate-to-Source Charge
9.4
nC
V
DS
= 80V
Q
gd
Gate-to-Drain ("Miller") Charge
38
V
GS
= 5.0V, See Fig. 6 and 13
t
d(on)
Turn-On Delay Time
11
V
DD
= 50V
t
r
Rise Time
81
I
D
= 18A
t
d(off)
Turn-Off Delay Time
39
R
G
= 5.0
,
V
GS
= 5.0V
t
f
Fall Time
62
R
D
= 2.7
,
See Fig. 10
Between lead,
and center of die contact
C
iss
Input Capacitance
1800
V
GS
= 0V
C
oss
Output Capacitance
350
pF
V
DS
= 25V
C
rss
Reverse Transfer Capacitance
170
= 1.0MHz, See Fig. 5
Electrical Characteristics @ T
J
= 25C (unless otherwise specified)
nH
I
GSS
R
DS(on)
Static Drain-to-Source On-Resistance
L
S
Internal Source Inductance
7.5
ns
I
DSS
Drain-to-Source Leakage Current
A
IRL540NS/L
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
Fig 2. Typical Output Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
1
1 0
1 0 0
1 0 0 0
0.1
1
1 0
1 0 0
I , Drain-to-Source Current (A)
D
V , Drain-to-Source Voltage (V)
D S
A
2 0 s P U L S E W I D T H
T = 25C
J
VGS
TOP 15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
2 . 5 V
1
1 0
1 0 0
1 0 0 0
0.1
1
1 0
1 0 0
I , Drain-to-Source Current (A)
D
V , Drain-to-Source Voltage (V)
D S
A
2 0 s P U L S E W I D T H
T = 175C
VGS
TOP 15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
2 . 5 V
J
1
1 0
1 0 0
1 0 0 0
2
4
6
8
1 0
T = 25C
J
G S
V , Gate-to-Source Voltage (V)
D
I , Drain-to-Source Current (A)
T = 175C
J
A
V = 50V
20s PULSE WIDTH
D S
0 . 0
0 . 5
1 . 0
1 . 5
2 . 0
2 . 5
3 . 0
- 6 0
- 4 0
- 2 0
0
2 0
4 0
6 0
8 0
1 0 0 1 2 0 1 4 0 1 6 0 1 8 0
J
T , Junction Temperature (C)
R , Drain-to-Source On Resistance
DS(on)
(Normalized)
V = 10V
G S
A
I = 30A
D
IRL540NS/L
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
1
1 0
1 0 0
1 0 0 0
0 . 4
0 . 6
0 . 8
1 . 0
1 . 2
1 . 4
1 . 6
1 . 8
T = 25C
J
V = 0V
G S
V , Source-to-Drain Voltage (V)
I , Reverse Drain Current (A)
S D
SD
A
T = 1 7 5 C
J
1
1 0
1 0 0
1 0 0 0
1
1 0
1 0 0
1 0 0 0
V , Drain-to-Source Voltage (V)
D S
I , Drain Current (A)
O P E R A T I O N I N T H I S A R E A L I M I T E D
BY R
D
D S ( o n )
1 0 s
1 0 0 s
1 m s
1 0 m s
A
T = 25C
T = 175C
Single Pulse
C
J
0
3
6
9
1 2
1 5
0
2 0
4 0
6 0
8 0
1 0 0
Q , Total Gate Charge (nC)
G
V , Gate-to-Source Voltage (V)
GS
V = 80V
V = 50V
V = 20V
D S
D S
D S
A
FOR TEST CIRCUIT
SEE FIGURE 13
I = 18A
D
0
1 0 0 0
2 0 0 0
3 0 0 0
1
1 0
1 0 0
C, Capacitance (pF)
D S
V , Drain-to-Source Voltage (V)
A
V = 0V, f = 1MHz
C = C + C , C SHORTED
C = C
C = C + C
G S
iss gs gd ds
rss gd
oss ds gd
C
iss
C
oss
C
rss
IRL540NS/L
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig 10b. Switching Time Waveforms
V
DS
Pulse Width
1
s
Duty Factor
0.1 %
R
D
V
GS
R
G
D.U.T.
5.0V
+
-
V
DD
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
25
50
75
100
125
150
175
0
10
20
30
40
T , Case Temperature
( C)
I , Drain Current (A)
C
D
0.01
0.1
1
10
0.00001
0.0001
0.001
0.01
0.1
1
Notes:
1. Duty factor D =
t / t
2. Peak T = P
x Z
+ T
1
2
J
DM
thJC
C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response
(Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
PDF 
ZIP