<200V
HO
NC
VS
OCSET1
OC
V
CC
SD
DT/SD
COM
OCSET2
IN
VB
LO
IRS20124
NC
NC
<20V
<20V
IN
OC
D
IGITAL
A
UDIO
D
RIVER
WITH
D
ISCRETE
D
EAD
-
TIME
AND
P
ROTECTION
Product Summary
V
SUPPLY
200V max.
IO+/-
1A / 1.2A typ.
Selectable Dead Time
15/25/35/45ns typ.
Prop Delay Time
70ns typ.
Bi-directional Over
Current Sensing
Package
Typical Application Diagram
IRS20124S(PbF)
Data Sheet No. PD60240 revA
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1
14-Lead SOIC
Features
200V high voltage ratings deliver up to 1000W
output power in Class D audio amplifier
applications
Integrated dead-time generation and bi-directional
over current sensing simplify design
Programmable compensated preset dead-time for
improved THD performances over temperature
High noise immunity
Shutdown function protects devices from overload
conditions
Operates up to 1MHz
3.3V/5V logic compatible input
IRS20124S(PbF)
2
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Symbol
Definition
Min.
Max.
Units
V
B
High side floating supply voltage
-0.3
220
V
Vs
High side floating supply voltage
VB-20
VB+0.3
V
V
HO
High side floating output voltage
Vs-0.3
VB+0.3
V
V
CC
Low side fixed supply voltage
-0.3
20
V
V
LO
Low side output voltage
-0.3
Vcc+0.3
V
V
IN
Input voltage
-0.3
Vcc+0.3
V
V
OC
OC pin input voltage
-0.3
Vcc+0.3
V
V
OCSET1
OCSET1 pin input voltage
-0.3
Vcc+0.3
V
V
OCSET2
OCSET2 pin input voltage
-0.3
Vcc+0.3
V
dVs/dt
Allowable Vs voltage slew rate
-
50
V/ns
Pd
Maximum power dissipation
-
1.25
W
Rth
JA
Thermal resistance, Junction to ambient
-
100
C/W
T
J
Junction Temperature
-
150
C
T
S
Storage Temperature
-55
150
C
T
L
Lead temperature (Soldering, 10 seconds)
-
300
C
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters
are absolute voltages referenced to COM. All currents are defined positive into any lead. The thermal resistance and power
dissipation ratings are measured under board mounted and still air conditions.
Description
The IRS20124S is a high voltage, high speed power MOSFET driver with internal dead-time and shutdown
functions specially designed for Class D audio amplifier applications.
The internal dead time generation block provides accurate gate switch timing and enables tight dead-time
settings for better THD performances.
In order to maximize other audio performance characteristics, all switching times are designed for immunity
from external disturbances such as VCC perturbation and incoming switching noise on the DT pin. Logic
inputs are compatible with LSTTL output or standard CMOS down to 3.0V without speed degradation. The
output drivers feature high current buffers capable of sourcing 1.0A and sinking 1.2A. Internal delays are
optimized to achieve minimal dead-time variations. Proprietary HVIC and latch immune CMOS technologies
guarantee operation down to Vs= 4V, providing outstanding capabilities of latch and surge immunities with
rugged monolithic construction.
www.irf.com
3
IRS20124S(PbF)
Note 1: Logic operational for V
S
equal to -8V to 200V. Logic state held for V
S
equal to -8V to -V
BS
.
Recommended Operating Conditions
For Proper operation, the device should be used within the recommended conditions. The Vs and COM
offset ratings are tested with all supplies biased at 15V differential.
Symbol
Definition
Min.
Max.
Units
V
B
High side floating supply absolute voltage
Vs+10
Vs+18
V
V
S
High side floating supply offset voltage
Note 1
200
V
V
HO
High side floating output voltage
Vs
V
B
V
V
CC
Low side fixed supply voltage
10
18
V
V
LO
Low side output voltage
0
VCC
V
V
IN
Logic input voltage
0
VCC
V
V
OC
OC pin input voltage
0
VCC
V
V
OCSET1
OCSET1 pin input voltage
0
VCC
V
V
OCSET2
OCSET2 pin input voltage
0
VCC
V
T
A
Ambient Temperature
-40
125
C
Dynamic Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15V, C
L
= 1nF and T
A
= 25C unless otherwise specified. Figure 2 shows the timing definitions.
Symbol
Definition
Min. Typ.
Max. Units Test Conditions
ton
High & low side turn-on propagation delay
--
60
80
V
S
=0V
toff
High & low side turn-off propagation delay
--
60
80
V
S
=200V
tr
Turn-on rise time
--
25
40
tf
Turn-off fall time
--
15
35
tsd
Shutdown propagation delay
--
140
200
toc
Propagation delay time from Vs>Vsoc+ to OC
--
280
--
OC
SET1
=3.22V
OC
SET2
=1.20V
twoc min
OC pulse width
--
100
--
toc filt
OC input filter time
--
200
--
DT1
Deadtime: LO turn-off to HO turn-on (DT
LO-HO
)
& HO turn-off to LO turn-on (DT
HO-LO
)
0
15
40
V
DT
>V
DT1
DT2
Deadtime: LO turn-off to HO turn-on (DT
LO-HO
)
& HO turn-off to LO turn-on (DT
HO-LO
)
5
25
50
V
DT1
>V
DT
> V
DT2
DT3
Deadtime: LO turn-off to HO turn-on (DT
LO-HO
)
& HO turn-off to LO turn-on (DT
HO-LO
)
10
35
60
V
DT2
>V
DT
> V
DT3
DT4
Deadtime: LO turn-off to HO turn-on (DT
LO-HO
)
& HO turn-off to LO turn-on (DT
HO-LO
)V
D
T= V
DT4
15
45
70
V
DT3
>V
DT
> V
DT4
nsec
IRS20124S(PbF)
4
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Static Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15V and T
A
= 25C unless otherwise specified.
Symbol
Definition
Min. Typ. Max. Units Test Conditions
V
IH
Logic high input voltage
2.5
--
--
Vcc=10~20V
V
IL
Logic low input voltage
--
--
1.2
V
OH
High level output voltage, V
BIAS
V
O
--
--
1.2
Io=0A
V
OL
Low level output voltage, V
O
--
--
0.1
Io=0A
UV
CC+
Vcc supply UVLO positive threshold
8.3
9.0
9.7
UV
CC-
Vcc supply UVLO negative threshold
7.5
8.2
8.9
UV
BS+
High side well UVLO positive threshold
8.3
9.0
9.7
UV
BS-
High side well UVLO negative threshold
7.5
8.2
8.9
I
QBS
High side quiescent current
--
--
1
I
QCC
Low side quiescent current
--
--
4
V
DT
=Vcc
I
LK
High to Low side leakage current
--
--
50
V
B
=V
S
=200V
I
IN+
Logic "1" input bias current
--
3
10
V
IN
=3.3V
I
IN-
Logic "0" input bias current
--
0
1.0
V
IN
=0V
I
o+
Output high short circuit current (Source)
--
1.0
--
Vo=0V, PW<10S
I
o-
Output low short circuit current (Sink)
--
1.2
--
Vo=15V, PW<10S
V
DT1
DT mode select threshold 1
0.8xVcc 0.89xVcc 0.97xVcc
V
DT2
DT mode select threshold 2
0.51xVcc 0.57xVcc 0.63xVcc
V
DT3
DT mode select threshold 3
0.32xVcc 0.36xVcc 0.40xVcc
V
DT4
DT mode select threshold 4
0.21xVcc 0.23xVcc 0.25xVcc
V
SOC+
Positive OC threshold in Vs
0.75
1.0
1.25
OC
SET1
=3.22V
OC
SET
2=1.20
V
SOC-
Negative OC threshold in Vs
-1.25
-1.0
-0.75
OC
SET1
=3.22V
OC
SET2
=1.20V
A
mA
V
V
A
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5
IRS20124S(PbF)
14
13
12
11
10
9
8
1
2
3
4
5
6
7
IN
OCSET1
DT/SD
OCSET2
OC
COM
LO
V
CC
NC
VS
HO
VB
NC
NC
IR20124S 14 Lead SOIC (narrow body)
Lead Definitions
Symbol Description
VCC
Low side logic Supply voltage
VB
High side floating supply
HO
High side output
VS
High side floating supply return
IN
Logic input for high and low side gate driver outputs (HO and LO), in phase with HO
DT/SD
Input for programmable dead-time, referenced to COM. Shutdown LO and HO when tied to COM
COM
Low side supply return
LO
Low side output
OC
Over current output (negative logic)
OC
SET1
Input for setting negative over current threshold
OC
SET2
Input for setting positive over current threshold
IRS20124S(PbF)
6
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Block Diagram
SD
LEVEL
SHIFTER
UV
DETECT
VB
HO
VS
IN
DEAD
TIME
DT/SD
UV
Q
S
R
CURRENT
SENSING
UV
DETECT
DELAY
OC
O
C
SET
1
O
C
S
E
T
2
Vcc
LO
COM
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7
IRS20124S(PbF)
50%
50%
t
off(L)
t
on(L)
90%
10%
90%
10%
DT
HO-LO
t
off(H)
IN
HO
LO
t
on(H)
DT
LO-HO
DT/SD
HO
LO
V
SD
T
SD
90%
Figure 1. Switching Time Waveform Definitions
Figure 2. Shutdown Waveform Definitions
IRS20124S(PbF)
8
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Figure 4. OC Waveform Definitions
toc filt
HIGH
VS
OC
V
soct
COM
COM
twoc
VS
OC
V
Soc+
tdoc
COM
COM
LO
V
Soc-
IN
OCSET1
DT/SD
OCSET2
OC
COM
LO
V
CC
NC
VS
HO
VB
NC
NC
__
15V
15V
Vsoc+
Vsoc-
10k
OC
Vsoc+
Vsoc-
COM
VS
OC
Figure 5. OC Waveform Definitions
Figure 3. OC Input FilterTime Definitions
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9
IRS20124S(PbF)
Typ.
Max.
0
30
60
90
120
150
-50
-25
0
25
50
75
100
125
Temperature (
o
C)
Tu
r
n
-
O
f
f
Ti
m
e
(
n
s
)
Figure 7A. Turn-Off Time
vs. Temperature
Typ.
Max.
0
30
60
90
120
150
10
12
14
16
18
20
V
BIAS
Supply Voltage (V)
Tur
n
-
O
f
f
Ti
m
e
(
n
s
)
Figure 7B. Turn-Off Time
vs. Supply Voltage
0
40
80
120
160
200
-50
-25
0
25
50
75
100
125
Temperature (
o
C)
Turn-on Delay Time (ns)
Figure 6A. Turn-On Tim e
vs. Tem perature
0
40
80
120
160
200
10
12
14
16
18
20
V
BIAS
Supply Voltage (V)
Turn-on Delay Time (ns)
Figure 6B. Turn-On Tim e
vs. Supply Voltage
IRS20124S(PbF)
10
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10
20
30
40
50
60
-50
-25
0
25
50
75
100
125
Temperature (
o
C)
Turn-On Rise Time (ns)
Fiure 8A. Turn-On Rise Tim e
vs.Temperature
10
20
30
40
50
60
10
12
14
16
18
20
V
BIAS
Supply Voltage (V)
Turn-On Rise Time (ns)
Figure 8B. Turn-On Rise Time
vs. Supply Voltage
0
10
20
30
40
50
-50
-25
0
25
50
75
100
125
Temperature (
o
C)
Turn-Off Fall Time (ns)
Figure 9A. Turn-Off Fall Tim e
vs. Temperature
0
10
20
30
40
50
10
12
14
16
18
20
V
BIAS
Supply Voltage (V)
Turn-Off Fall Time (ns)
Figure 9B. Turn-Off Fall Tim e
vs. Supply Voltage
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11
IRS20124S(PbF)
Min.
1
2
3
4
5
10
12
14
16
18
20
V
CC
Supply Voltage (V)
I
n
pu
t
V
o
l
t
ag
e (
V
)
Figure 10B. Logic "1" Input Voltage
vs. Supply Voltage
Max.
0
1
2
3
4
-50
-25
0
25
50
75
100
125
Temperatre (
o
C)
I
n
pu
t
Vol
t
ag
e
(
V
)
Figure 11A. Logic "0" Input Voltage
vs. Temperature
Max.
0
1
2
3
4
10
12
14
16
18
20
V
CC
Supply Voltage (V)
I
n
p
u
t
Vol
t
ag
e (
V
)
Figure 11B. Logic "0" Input Voltage
vs. Supply Voltage
Min.
1
2
3
4
5
-50
-25
0
25
50
75
100
125
Temperature (
o
C)
I
npu
t
V
o
l
t
age
(
V
)
Figure 10A. Logic "1" Input Voltage
vs. Temperature
IRS20124S(PbF)
12
www.irf.com
Max.
-1
0
1
2
3
4
-50
-25
0
25
50
75
100
125
Temperature (
o
C)
H
i
g
h
Le
v
e
l
O
u
t
p
u
t
V
o
l
t
age
(
V
)
Figure 12A. High Level Output
vs. Temperature
Max.
0.00
0.05
0.10
0.15
0.20
0.25
-50
-25
0
25
50
75
100
125
Temperature (
o
C)
L
o
w
Le
v
e
l
O
u
t
p
u
t
Vo
l
t
ag
e
(
V
)
Figure 13A. Low Level Output
vs.Temperature
Max.
0.00
0.05
0.10
0.15
0.20
0.25
10
12
14
16
18
20
V
CC
Supply Voltage (V)
Lo
w
Le
v
e
l
O
u
t
p
u
t
V
o
l
t
ag
e
(
V
)
Figure 13B. Low Level Output
vs. Supply Voltage
Max.
0
1
2
3
4
10
12
14
16
18
20
V
CC
Supply Voltage (V)
H
i
gh Le
v
e
l
O
u
t
put
V
o
l
t
age
(
V
)
Figure 12B. High Level Output
vs. Supply Voltage
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13
IRS20124S(PbF)
Max.
0
50
100
150
200
250
300
-50
-25
0
25
50
75
100
125
Temperature (
o
C)
O
f
f
s
e
t
S
u
pp
l
y
Le
ak
a
g
e
C
u
r
r
ent
(
A)
Figure 14A. Offset Supply Leakage
Current vs. Temperature V
B
=200v
Max.
Typ.
-10
10
30
50
70
90
110
50
80
110
140
170
200
V
B
Boost Voltage (V)
O
f
f
s
e
t
Sup
p
l
y
Le
ak
ag
e C
u
r
r
en
t
(
A)
Figure 14B. Offset Supply Leakage
Current vs. Supply Voltage
0.0
0.5
1.0
1.5
2.0
2.5
-50
-25
0
25
50
75
100
125
Temperature (
o
C)
V
BS
Supply Current (
)
Figure 15A. V
BS
Supply Current
vs. Temperature
0
1
1
2
2
3
10
12
14
16
18
20
V
BS
Supply Voltage (V)
V
BS
Supply Current (
)
Figure 15B. V
BS
Supply Current
vs. Supply Voltage
IRS20124S(PbF)
14
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Max.
0
2
4
6
8
10
-50
-25
0
25
50
75
100
125
Temperature (
o
C)
V
cc
S
u
ppl
y
C
u
r
r
ent
(
A)
Figure 16A. V
CC
Supply Current
vs. Temperature
Max.
0
2
4
6
8
10
10
12
14
16
18
20
V
CC
Supply Voltage (V)
V
cc
S
u
p
p
l
y
C
u
r
r
e
n
t
(
)
Figure 16B. V
CC
Supply Current
vs. Supply Voltage
0
6
12
18
24
30
-50
-25
0
25
50
75
100
125
Temperature (
o
C)
Logic "1" Input Current (
)
Figure 17A. Logic "1" Input Current
vs. Temperature
0
6
12
18
24
30
10
12
14
16
18
20
V
CC
Supply Voltage (V)
Logic "1" Input Current (
)
Figure 17B. Logic "1" Input Current
vs. Supply Voltage
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15
IRS20124S(PbF)
Max.
0
1
2
3
4
5
-50
-25
0
25
50
75
100
125
Temperature (
o
C)
Lo
gi
c
"0
"
I
n
p
u
t
C
u
r
r
en
t
(
)
Figure 18A. Logic "0" Input Current
vs. Temperature
Max.
0
1
2
3
4
5
10
12
14
16
18
20
V
CC
Supply Voltage (V)
Lo
gi
c
"0"
I
npu
t
C
u
r
r
ent
(
)
Figure 18B. Logic "0" Input Current
vs. Supply Voltage
Typ.
Max.
Min.
6
7
8
9
10
11
-50
-25
0
25
50
75
100
125
Temperature (
o
C)
V
cc
S
u
ppl
y
C
u
r
r
ent
(
)
Figure 19. V
CC
Undervoltage Threshold (+)
vs. Temperature
Typ.
Max.
Min.
6
7
8
9
10
11
-50
-25
0
25
50
75
100
125
Temperature (
o
C)
V
cc
S
u
pp
l
y
C
u
r
r
en
t
(
)
Figure 20. V
CC
Undervoltage Threshold (-)
vs. Temperature
IRS20124S(PbF)
16
www.irf.com
Typ.
0.5
0.7
0.9
1.1
1.3
1.5
10
12
14
16
18
20
V
BIAS
Supply Voltage (V)
O
u
t
p
ut
S
o
ur
c
e
C
u
r
r
e
n
t
(
)
Figure 23. Output Source Current
vs. Supply Voltage
Typ.
0.5
0.7
0.9
1.1
1.3
1.5
10
12
14
16
18
20
V
BIAS
Supply Voltage (V)
O
u
t
p
ut
S
i
nk
C
u
r
r
en
t
(
)
Figure 24. Output Sink Current
vs. Supply Voltage
6
7
8
9
10
11
-50
-25
0
25
50
75
100
125
Temperature (
o
C)
V
BS
Supply Current (
)
Figure 21. V
BS
Undervoltage Threshold (+)
vs. Tem perature
6
7
8
9
10
11
-50
-25
0
25
50
75
100
125
Temperature (
o
C)
V
BS
Supply Current (
)
Figure 22. V
BS
Undervoltage Threshold (-)
vs. Tem perature
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17
IRS20124S(PbF)
Typ.
-15
-13
-11
-9
-7
-5
10
12
14
16
18
20
V
BS
Floting Supply Voltage (V)
V
S
O
f
f
s
et
S
u
p
p
l
y
V
o
l
t
ag
e (
V
)
Figure 25. Maximum VS Negative Offset
vs. Supply Voltage
Typ.
Max.
Min.
11
12
13
14
15
16
-50
-25
0
25
50
75
100
125
Temperature (
o
C)
VDT
1
(
V)
Figure 26. DT mode select Threshold (1)
vs. Temperature
Typ.
Max.
Min.
6
7
8
9
10
11
-50
-25
0
25
50
75
100
125
Temperature (
o
C)
VDT
2
(
V)
Figure 27. DT mode select Threshold (2)
vs. Temperature
Typ.
Max.
Min.
3
4
5
6
7
8
-50
-25
0
25
50
75
100
125
Temperature (
o
C)
VDT
3
(
V)
Figure 28. DT mode select Threshold (3)
vs. Temperature
IRS20124S(PbF)
18
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Typ.
20
28
36
44
52
60
-50
-25
0
25
50
75
100
125
Temperature (
o
C)
DT
LO
-
H
O
(
n
se
c)
Figure 30. DT LO turn-off to HO turn-on (3)
vs. Temperature
2.0
2.5
3.0
3.5
4.0
4.5
-50
-25
0
25
50
75
100
125
Temperature (
o
C)
VDT 4(V)
Figure 29. DT m ode select Threshold (4)
vs. Temperature
Typ.
Max.
Min.
-1.8
-1.5
-1.2
-0.9
-0.6
-0.3
-50
-25
0
25
50
75
100
125
Temperature (
o
C)
N
e
gat
i
v
e O
C
T
H
(
V
)
Figure 32. Negative OC Threshold(-) in VS
vs. Temperature
Typ.
Max.
Min.
0.0
0.4
0.8
1.2
1.6
2.0
-50
-25
0
25
50
75
100
125
Temperature (
o
C)
P
o
si
t
i
ve
O
C
T
H
(
V
)
Figure 31. Positive OC Threshold(+) in VS
vs. Temperature
www.irf.com
19
IRS20124S(PbF)
140V
70V
0V
15
25
35
45
55
65
1
10
100
1000
Frequency (KHZ)
T
e
m
p
er
at
ur
e (
o
C)
Figure 32. IRS20124s vs. Frequency (IRFBC20)
R
gate
=33
, V
CC
=12V
140v
70v
0v
15
25
35
45
55
65
1
10
100
1000
Frequency (KHZ)
T
e
m
p
er
at
ur
e
(
o
C)
Figure 33. IRS20124s vs. Frequency (IRFBC30)
R
gate
=22
, V
CC
=12V
140V
70V
0V
15
25
35
45
55
65
1
10
100
1000
Frequency (KHZ)
T
e
m
p
er
at
ur
e (
o
C)
Figure 34. IRS20124s vs. Frequency (IRFBC40)
R
gate
=15
, V
CC
=12V
140V
70V
0V
15
25
35
45
55
65
75
1
10
100
1000
Frequency (KHZ)
T
e
m
p
er
at
ur
e (
o
C)
Figure 35. IRS20124s vs. Frequency (IRFPE50)
R
gate
=10
, V
CC
=12V
33
.
34 .
3 5.
3 6.
IRS20124S(PbF)
20
www.irf.com
Functional description
Programmable Dead-time
The IRS20124 has an internal dead-time generation
block to reduce the number of external components
in the output stage of a Class D audio amplifier.
Selectable dead-time through the DT/SD pin volt-
age is an easy and reliable function, which re-
quires only two external resistors. The dead-time
generation block is also designed to provide a
constant dead-time interval, independent of Vcc
fluctuations. Since the timings are critical to the
audio performance of a Class D audio amplifier,
the unique internal dead-time generation block is
designed to be immune to noise on the DT/SD
pin and the Vcc pin. Noise-free programmable
dead-time function is available by selecting dead-
time from four preset values, which are optimized
and compensated.
How to Determine Optimal Dead-time
Please note that the effective dead-time in an actual
application differs from the dead-time specified in
this datasheet due to finite fall time, tf. The dead-
time value in this datasheet is defined as the time
period from the starting point of turn-off on one
side of the switching stage to the starting point of
turn-on on the other side as shown in Fig.5. The
fall time of MOSFET gate voltage must be sub-
tracted from the dead-time value in the datasheet
to determine the effective dead time of a Class D
audio amplifier.
(Effective dead-time)
= (Dead-time in datasheet) (fall time, tf)
HO (or LO)
LO (or HO)
tf
Dead-
time
Effective dead-time
10%
10%
90%
Figure 6. Effective Dead-time
A longer dead time period is required for a MOSFET
with a larger gate charge value because of the
longer tf. A shorter effective dead-time setting is
always beneficial to achieve better linearity in the
Class D switching stage. However, the likelihood
of shoot-through current increases with narrower
dead-time settings in mass production. Negative
values of effective dead-time may cause excessive
heat dissipation in the MOSFETs, potentially
leading to their serious damage. To calculate the
optimal dead-time in a given application, the fall
time tf for both output voltages, HO and LO, in the
actual circuit needs to be measured. In addition,
the effective dead-time can also vary with
temperature and device parameter variations.
Therefore, a minimum effective dead-time of 10nS
is recommended to avoid shoot-through current
over the range of operating temperatures and
supply voltages.
www.irf.com
21
IRS20124S(PbF)
DT/SD pin
DT/SD pin provides two functions: 1) setting dead-
time and 2) shutdown. The IRS20124 determines
its operation mode based on the voltage applied
to the DT/SD pin. An internal comparator
translates which mode is being used by comparing
internal reference voltages. Threshold voltages for
each mode are set internally by a resistive voltage
divider off Vcc, negating the need of using a precise
absolute voltage to set the mode.
The relationship between the operation mode and
the voltage at DT/SD pin is illustrated in the Fig.7.
Vcc
0.89xVcc
0.57xVcc
0.36xVcc
0.23xVcc
Shutdown
45nS
35nS
25nS
15nS
Operational Mode
V
DT
Dead-time
Figure 7. Dead-time Settings vs V
DT
Voltage
Design Example
Table 1 shows suggested values of resistance for
setting the dead-
time. Resistors with
up to 5% tolerance
can be used if these
listed values are fol-
lowed.
Vcc
COM
DT/SD
>0.5mA
R1
R2
IRS20124
Dead-
time
mode
R1 R2 DT/SD
voltage
DT1 <10k Open
1.0
x
Vcc
DT2 3.3k 8.2k
0.71
x
Vcc
DT3 5.6k 4.7k
0.46
x
Vcc
DT4 8.2k 3.3k
0.29
x
Vcc
Table 1. Suggested resistor values for dead-time
settings
Shutdown
Since IRS20124 has internal dead-time genera-
tion, independent inputs for HO and LO are no
longer provided. Shutdown mode is the only way
to turn off both MOSFETs simultaneously to pro-
tect them from over current conditions. If the DT/
SD pin detects an input voltage below the thresh-
old, V
DT4,
the IRS20124 will output 0V at both HO
and LO outputs, forcing the switching output node
to go into a high impedance state.
Over Current Sensing
In order to protect the power MOSFET, IRS20124
has a feature to detect over current conditions,
which can occur when speaker wires are shorted
together. The over current shutdown feature can
be configured by combining the current sensing
function with the shutdown mode via the DT/SD pin.
Load Current Direction in Class D
Audio
Application
In a Class D audio amplifier, the direction of the
load current alternates according to the audio in-
put signal. An over current condition can therefore
happen during either a positive current cycle or a
negative current cycle. Fig.9 shows the rela-
Figure 8. External Resistor
IRS20124S(PbF)
22
www.irf.com
tionship between output current direction and
the current in the low side MOSFET. It should be
noted that each MOSFET carries a part of the
load current in an audio cycle. Bi-directional cur-
rent sensing offers over current detection capa-
bilities in both cases by monitoring only the low
side MOSFET.
Load Current
0
Bi-directional Current Sensing
IRS20124 has an over current detection function
utilizing R
DS(ON)
of the low side switch as a current
sensing shunt resistor. Due to the proprietary HVIC
process, the IRS20124 is able to sense negative
as well as positive current flow, enabling bi-direc-
tional load current sensing without the need for
any additional external passive components.
Figure 9. Direction in MMOSFET Current and Load
Current
v
s
Vsoc+
Vsoc-
COM
~
~
~
~
~
~
~
~
~
~ ~
~
~
~ ~
~
~
~
~
~
~
~
(a ) Normal Operation
Condition
(b ) Over- Current in
Positive Load Current
(c ) Over- Current in
Negative Load Current
Figure 10. Vs Waveform in Over-current Condition
IRS20124 measures the current during the period
when the low side MOSFET is turned on. Fig.10
illustrates how an excessive voltage at Vs node
detects an over current condition. Under normal
operating conditions, Vs voltage for the low side
switch is well within the trip threshold boundaries,
V
SOC-
and V
SOC+.
In the case of Fig.9(b) which dem-
onstrates the amplifier sourcing too much current
to the load, the Vs node is found below the trip
level, V
SOC-
. In Fig.9(c) with opposite current direc-
tion, the amplifier sinks too much current from the
load, positioning Vs well above trip level, V
SOC+.
Once the voltage in Vs exceeds the preset thresh-
old, the OC pin pulls down to COM to detect an
over current condition.
Since the switching waveform usually contains
over/under shoot and associated oscillatory arti-
facts on their transient edges, a 200ns blanking
interval is inserted in the Vs voltage sensing block
at the instant the low side switch is engaged.
Because of this blanking interval, the OC function
will be unable to detect over current conditions if
the low side ON duration less than 200ns.
OC
SET1
OC
SET2
Vs
LO
OC
+
+
-
-
OR
AND
Figure 11. Simplified Functional Block Diagram of
Bi-Directional Current Sensing
As shown in Fig.11, bi-directional current sens-
ing block has an internal 2.0V level shifter feeding
the signal to the comparator. OC
SET1
sets the posi-
tive side threshold, and is given a trip level at V
SOC+
,
which is OC
SET1
- 2.0V. In same way, for a given
OC
SET2
, V
SOC-
is set at OC
SET2
2.0V
www.irf.com
23
IRS20124S(PbF)
Figure 12. External Resistor Network to set OC
Threshold
Vcc
COM
OC
SET1
>0.5mA
R3
R4
R5
OC
SET2
How to set OC Threshold
The positive and negative trip thresholds for bi-
directional current sensing are set by the voltages
at OC
SET1
and OC
SET2
. Fig.14 shows a typical re-
sistor voltage divider that can. be used to set
OC
SET1
and OC
SET2
.
The trip threshold voltages, V
SOC+
and V
SOC+,
are
determined by the required trip current levels, I
TRIP+
and
I
TRIP-
, and R
DS(ON)
in the low side MOSFET.
Since the sensed voltage of Vs is shifted up by
2.21V internally and compared with the voltages
fed to the OC
SET1
and OC
SET2
pins, the required
value of OC
SET1
with respect to COM is
V
OCSET1
= V
SOC+
+ 2.21 = I
TRIP+
x R
DS(ON)
+ 2.21
The same relation holds between OC
SET2
and V
SOC-,
V
OCSET2
= V
SOC-
+ 2.21 = I
TRIP-
x R
DS(ON)
+ 2.21
In general, R
DS(ON)
has a positive temperature co-
efficient that needs to be considered when the
threshold level is being set. Please also note that,
in the negative load current direction, the sensing
voltage at the Vs node is limited by the body di-
ode of the low side MOSFET as explained later.
Design Example
This example demonstrates how to use the ex-
ternal? resistor network to set I
TRIP+
and I
TRIP-
to
be 11A, using a MOSFET that has R
DS(ON)
=60m.
V
ISET1
= V
TH
+ + 2.21 = I
TRIP+
x R
DS(ON)
+ 2.21= 11
x 60m +2.21 = 2.87V
V
ISET2
= V
TH-
+ 2.21 = I
TRIP-
x R
DS(ON)
+ 2.21= (-11)
x 60m +2.21 = 1.55V
The total resistance of resistor network is based
on the voltage at the Vcc and required bias cur-
rent in this resistor network.
R
total
=R3 + R4 + R5 = Vcc / I
bias
= 12V / 1mA = 12K
The expected voltage across R3 is Vcc- V
ISET1
= 12-2.87=9.13V. Similarly, the voltages across
R4 is V
SOC+
- V
SOC-
= 2.87-1.55=1.32V, and the
voltage across R5 is V
ISET2
= 1.55V respectively.
R3 =9.13V/ I
bias
= 9.13K
R4 =1.32V/ I
bias
= 1.32K
R5 =1.55V/ I
bias
= 1.55K
Choose R3= 9.09K, R4=1.33K, R5=1.54K
from E-96 series.
Consequently, actual threshold levels are
V
SOC+
=2.88V gives I
TRIP+
= 11.2A
V
SOC-
=1.55V gives I
TRIP-
= -11.0A
Resisters with 1% tolerances are recommended.
IRS20124S(PbF)
24
www.irf.com
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 322 3331
Data and specifications subject to change without notice. 9/21/2005
OC Output Signal
The OC pin is a 20V open drain output. The OC
pin is pulled down to ground when an over current
condition is detected. A single external pull-up
resistor can be shared by multiple IRS20124 OC
pins to form the ORing logic. In order for a micro-
processor to read the OC signal, this information
is buffered with a mono stable multi vibrator to
ensure 100ns minimum pulse width.
Because of unpredictable logic status of the OC
pin, the OC signal should be ignored during power
up/down.
Limitation from Body Diode in MOSFET
When a Class D stage outputs a positive current,
flowing from the Class D amp to the load, the body
diode of the MOSFET will turn on when the Drain
to Source voltage of the MOSFET become larger
than the diode forward drop voltage. In such a
case, the sensing voltage at the Vs pin of the
IRS20124 is clamped by the body diode. This
means that the effective Rds(on) is now much
lower than expected from Rds(on) of the MOSFET,
and the Vs node my not able to reach the thresh-
old to turn the OC output on before the MOSFET
fails. Therefore, the region where body diode
clamping takes a place should be avoided when
setting V
SOC-
.
Voltage in Vs
Load
Current
Vsoc- should be
set in this region
}
0
Body Diode Clamp
For further application information for gate driver
IC please refer to AN-978 and DT98-2a. For fur-
ther application information for class D applica-
tion, please refer to AN-1070 and AN-1071.
Figure 13. Body Diode in MOSFET Clamps vs
Voltage
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