Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
1
Rev. C
04/15/05
IS61LV5128AL
ISSI
Copyright 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
512K x 8 HIGH-SPEED CMOS STATIC RAM
APRIL 2005
FEATURES
High-speed access times:
10, 12 ns
High-performance, low-power CMOS process
Multiple center power and ground pins for
greater noise immunity
Easy memory expansion with
CE
and
OE
options
CE
power-down
Fully static operation: no clock or refresh
required
TTL compatible inputs and outputs
Single 3.3V power supply
Packages available:
36-pin 400-mil SOJ
36-pin miniBGA
44-pin TSOP (Type II)
Lead-free available
DESCRIPTION
The
ISSI
IS61LV5128AL is a very high-speed, low power,
524,288-word by 8-bit CMOS static RAM. The
IS61LV5128AL is fabricated using
ISSI
's high-perform-
ance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields
higher performance and low power consumption devices.
When
CE
is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 250 W (typical) with CMOS input levels.
The IS61LV5128AL operates from a single 3.3V power
supply and all inputs are TTL-compatible.
The IS61LV5128AL is available in 36-pin 400-mil SOJ, 36-
pin mini BGA, and 44-pin TSOP (Type II) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A18
CE
OE
WE
512K X 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
V
DD
I/O
DATA
CIRCUIT
I/O0-I/O7
2
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. C
04/15/05
IS61LV5128AL
ISSI
PIN CONFIGURATION
36 mini BGA
PIN DESCRIPTIONS
A0-A18
Address Inputs
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Bidirectional Ports
V
DD
Power
GND
Ground
NC
No Connection
TRUTH TABLE
Mode
WE
WE
WE
WE
WE
CE
CE
CE
CE
CE
OE
OE
OE
OE
OE
I/O Operation
V
DD
Current
Not Selected
X
H
X
High-Z
I
SB
1
, I
SB
2
(Power-down)
Output Disabled H
L
H
High-Z
I
CC
Read
H
L
L
D
OUT
I
CC
Write
L
L
X
D
IN
I
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
A0
A1
A2
A3
A4
CE
I/O0
I/O1
V
DD
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
V
DD
I/O5
I/O4
A14
A13
A12
A11
A10
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
A0
A1
A2
A3
A4
CE
I/O0
I/O1
V
DD
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
NC
NC
NC
NC
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
V
DD
I/O5
I/O4
A14
A13
A12
A11
A10
NC
NC
NC
44
43
42
41
44-Pin TSOP (Type II)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
A0
I/O4
I/O5
GND
V
DD
I/O6
I/O7
A9
A1
A2
OE
A10
NC
WE
NC
A18
CE
A11
A3
A4
A5
A17
A16
A12
A6
A7
A15
A13
A8
I/O0
I/O1
V
DD
GND
I/O2
I/O3
A14
36-Pin SOJ
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
3
Rev. C
04/15/05
IS61LV5128AL
ISSI
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
TERM
Terminal Voltage with Respect to GND
0.5 to V
DD
+ 0.5
V
T
STG
Storage Temperature
65 to +150
C
P
T
Power Dissipation
1.0
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-
nent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
OPERATING RANGE
V
DD
Range
Ambient Temperature
10ns
12ns
Commercial
0C to +70C
3.3V +10%, -5%
3.3V +10%
Industrial
-40C to +85C
3.3V +10%, -5%
3.3V +10%
CAPACITANCE
(1,2)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
I/O
Input/Output Capacitance
V
OUT
= 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25C, f = 1 MHz, V
DD
= 3.3V.
4
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. C
04/15/05
IS61LV5128AL
ISSI
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
DD
= Min., I
OH
= 4.0 mA
2.4
--
V
V
OL
Output LOW Voltage
V
DD
= Min., I
OL
= 8.0 mA
--
0.4
V
V
IH
Input HIGH Voltage
2.0
V
DD
+ 0.3
V
V
IL
Input LOW Voltage
(1)
0.3
0.8
V
I
LI
Input Leakage
GND
V
IN
V
DD
Com.
2
2
A
Ind.
5
5
I
LO
Output Leakage
GND
V
OUT
V
DD
, Outputs Disabled
Com.
2
2
A
Ind.
5
5
Note:
1. V
IL
= 3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-10
-12
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Unit
I
CC
V
DD
Dynamic Operating
V
DD
= Max.,
Com.
--
90
--
85
mA
Supply Current
I
OUT
= 0 mA, f = f
MAX
Ind.
--
95
--
90
I
SB
TTL Standby Current
V
DD
= Max.,
Com.
--
40
--
35
mA
(TTL Inputs)
V
IN
= V
IH
or V
IL
Ind.
--
45
--
40
CE
V
IH
, f = f
MAX
.
I
SB
1
TTL Standby Current
V
DD
= Max.,
Com.
--
20
--
20
mA
(TTL Inputs)
V
IN
= V
IH
or V
IL
Ind.
--
25
--
25
CE
V
IH
, f = 0
I
SB
2
CMOS Standby
V
DD
= Max.,
Com.
--
15
--
15
mA
Current (CMOS Inputs)
CE
V
DD
0.2V,
Ind.
--
20
--
20
V
IN
V
DD
0.2V, or
V
IN
0.2V, f = 0
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
5
Rev. C
04/15/05
IS61LV5128AL
ISSI
AC TEST LOADS
AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 3.0V
Input Rise and Fall Times
3 ns
Input and Output Timing
1.5V
and Reference Levels
Output Load
See Figures 1 and 2
Figure 1
Figure 2
319
30 pF
Including
jig and
scope
353
OUTPUT
3.3V
319
5 pF
Including
jig and
scope
353
OUTPUT
3.3V
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-10
-12
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
t
RC
Read Cycle Time
10
--
12
--
ns
t
AA
Address Access Time
--
10
--
12
ns
t
OHA
Output Hold Time
2
--
2
--
ns
t
ACE
CE
Access Time
--
10
--
12
ns
t
DOE
OE
Access Time
--
4
--
5
ns
t
HZOE
(2)
OE
to High-Z Output
--
4
--
5
ns
t
LZOE
(2)
OE
to Low-Z Output
0
--
0
--
ns
t
HZCE
(2
CE
to High-Z Output
0
4
0
6
ns
t
LZCE
(2)
CE
to Low-Z Output
3
--
3
--
ns
t
PU
Power Up Time
0
--
0
--
ns
t
PD
Power Down Time
--
10
--
12
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0V to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage.
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