Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
1
Rev. A
11/11/02
IS61NF12832
IS61NF12836
IS61NF25618
IS61NLF12832 IS61NLF12836 IS61NLF25618
ISSI
ISSI reserves the right to make changes this specification herein and it products at any time without notice. ISSI assumes no responsibility or liability arising out of the application or use of any information,
product or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Copyright 2000, Integrated Silicon Solution, Inc
FEATURES
100 percent bus utilization
No wait cycles between Read and Write
Internal self-timed write cycle
Individual Byte Write Control
Single R/W (Read/Write) control pin
Clock controlled, registered address,
data and control
Interleaved or linear burst sequence control
using MODE input
Three chip enables for simple depth expansion
and address pipelining for TQFP
Power Down mode
Common data inputs and data outputs
CKE
pin to enable clock and suspend operation
JEDEC 100-pin TQFP, 119 PBGA package
Single +3.3V power supply ( 5%)
NF Version: 3.3V I/O Supply Voltage
NLF Version: 2.5V I/O Supply Voltage
Industrial temperature available
DESCRIPTION
The 4 Meg 'NF' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
network and communications customers. They are
organized as 131,072 words by 32 bits, 131,072 words
by 36 bits and 262,144 words by 18 bits, fabricated with
ISSI
's advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable,
CKE
is HIGH. In this state the internal
device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the
ADV input. When the ADV is HIGH the internal burst
counter is incremented. New external addresses can be
loaded when ADV is LOW.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when
WE
is LOW.
Separate byte enables allow individual bytes to be written.
A burst mode pin (MODE) defines the order of the burst
sequence. When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
128K x 32, 128K x 36 and 256K x 18
FLOW-THROUGH 'NO WAIT' STATE BUS
SRAM
NOVEMBER 2002
FAST ACCESS TIME
Symbol
Parameter
-8.5
-9
-10
Units
t
KQ
Clock Access Time
8.5
9
10
ns
t
KC
Cycle Time
10
12
12
ns
Frequency
100
83
83
MHz
2
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. A
11/11/02
IS61NF12832
IS61NF12836
IS61NF25618
IS61NLF12832
IS61NLF12836
IS61NLF25618
ISSI
BLOCK DIAGRAM
ADV
WE
}
BWY
X
(X=a,b,c,d or a,b)
CE
CE2
CE2
CONTROL
LOGIC
128Kx32; 125Kx36;
256Kx18
MEMORY ARRAY
WRITE
ADDRESS
REGISTER
CONTROL
LOGIC
BUFFER
ADDRESS
REGISTER
A [0:16] or
A [0:17]
CLK
CKE
A2-A16 or A2-A17
A0-A1
A'0-A'1
BURST
ADDRESS
COUNTER
MODE
DATA-IN
REGISTER
CONTROL
REGISTER
OE
ZZ
32, 36 or 18
K
DQa0-DQd7 or DQa0-DQb8
DQPa-DQPd
K
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
3
Rev. A
11/11/02
IS61NF12832
IS61NF12836
IS61NF25618
IS61NLF12832
IS61NLF12836
IS61NLF25618
ISSI
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A16
Synchronous Address Inputs
CLK
Synchronous Clock
ADV
Synchronous Burst Address Advance
BWa
-
BWd
Synchronous Byte Write Enable
WE
Write Enable
CKE
Clock Enable
CE
,
CE2
, CE2 Synchronous Chip Enable
OE
Output Enable
DQa-DQd
Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
V
CC
+3.3V Power Supply
GND
Ground
V
CCQ
Isolated Output Buffer Supply: +3.3V/2.5V
ZZ
Snooze Enable
PIN CONFIGURATION
119-pin PBGA (Top View) and 100-Pin TQFP
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCCQ
NC
NC
DQc1
DQc2
VCCQ
DQc5
DQc7
VCCQ
DQd1
DQd4
VCCQ
DQd6
DQd8
NC
NC
VCCQ
A6
CE2
A7
NC
DQc3
DQc4
DQc6
DQc8
VCC
DQd2
DQd3
DQd5
DQd7
NC
A5
NC
NC
A4
A3
A2
GND
GND
GND
BWc
GND
NC
GND
BWd
GND
GND
GND
MODE
A10
NC
NC
ADV
VCC
NC
CE
OE
NC
WE
VCC
CLK
NC
CKE
A1
A0
VCC
A11
NC
A8
A9
A12
GND
GND
GND
BWb
GND
NC
GND
BWa
GND
GND
GND
NC
A14
NC
A16
CE2
A15
NC
DQb6
DQb5
DQb4
DQb2
VCC
DQa7
DQa5
DQa4
DQa3
NC
A13
NC
NC
VCCQ
NC
NC
DQb8
DQb7
VCCQ
DQb3
DQb1
VCCQ
DQa8
DQa6
VCCQ
DQa2
DQa1
NC
ZZ
VCCQ
1 2 3 4 5 6 7
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
GND
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
GND
VCC
VCC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
46 47 48 49 50
A6
A7
CE
CE2
BWd
BWc
BWb
BWa
CE2
VCC
GND
CLK
WE
CKE
OE
ADV
NC
NC
A8
A9
128K x 32
4
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. A
11/11/02
IS61NF12832
IS61NF12836
IS61NF25618
IS61NLF12832
IS61NLF12836
IS61NLF25618
ISSI
PIN CONFIGURATION
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A16
Synchronous Address Inputs
CLK
Synchronous Clock
ADV
Synchronous Burst Address Advance
BWa
-
BWd
Synchronous Byte Write Enable
WE
Write Enable
CKE
Clock Enable
CE
,
CE2
, CE2 Synchronous Chip Enable
OE
Output Enable
DQa-DQd
Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
V
CC
+3.3V Power Supply
GND
Ground
V
CCQ
solated Output Buffer Supply: +3.3V/2.5V
ZZ
Snooze Enable
DQPa-DQPd
Parity Data I/O
128K x 36
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCCQ
NC
NC
DQc1
DQc2
VCCQ
DQc5
DQc7
VCCQ
DQd1
DQd4
VCCQ
DQd6
DQd8
NC
NC
VCCQ
A6
CE2
A7
DQPc
DQc3
DQc4
DQc6
DQc8
VCC
DQd2
DQd3
DQd5
DQd7
DQPd
A5
NC
NC
A4
A3
A2
GND
GND
GND
BWc
GND
NC
GND
BWd
GND
GND
GND
MODE
A10
NC
NC
ADV
VCC
NC
CE
OE
NC
WE
VCC
CLK
NC
CKE
A1
A0
VCC
A11
NC
A8
A9
A12
GND
GND
GND
BWb
GND
NC
GND
BWa
GND
GND
GND
NC
A14
NC
A16
CE2
A15
DQPb
DQb6
DQb5
DQb4
DQb2
VCC
DQa7
DQa5
DQa4
DQa3
DQPa
A13
NC
NC
VCCQ
NC
NC
DQb8
DQb7
VCCQ
DQb3
DQb1
VCCQ
DQa8
DQa6
VCCQ
DQa2
DQa1
NC
ZZ
VCCQ
1 2 3 4 5 6 7
119-pin PBGA (Top View) and 100-Pin TQFP
DQPb
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
GND
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
DQPa
DQPc
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
GND
VCC
VCC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
46 47 48 49 50
A6
A7
CE
CE2
BWd
BWc
BWb
BWa
CE2
VCC
GND
CLK
WE
CKE
OE
ADV
NC
NC
A8
A9
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
5
Rev. A
11/11/02
IS61NF12832
IS61NF12836
IS61NF25618
IS61NLF12832
IS61NLF12836
IS61NLF25618
ISSI
PIN CONFIGURATION
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A17
Synchronous Address Inputs
CLK
Synchronous Clock
ADV
Synchronous Burst Address Advance
BWa
-
BWb
Synchronous Byte Write Enable
WE
Write Enable
CKE
Clock Enable
CE
, CE2,
CE2
Synchronous Chip Enable
OE
Output Enable
DQ1-DQ16
Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
V
CC
+3.3V Power Supply
GND
Ground
V
CCQ
Isolated Output Buffer Supply: +3.3V/2.5V
ZZ
Snooze Enable
DQP1-DQP2
Parity Data I/O DQP1 is parity for
DQ1-8; DQP2 is parity for DQ9-16
256K x 18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
NC
VCCQ
GND
NC
NC
DQ9
DQ10
GND
VCCQ
DQ11
DQ12
GND
VCC
VCC
GND
DQ13
DQ14
VCCQ
GND
DQ15
DQ16
DQP2
NC
GND
VCCQ
NC
NC
NC
A10
NC
NC
VCCQ
GND
NC
DQP1
DQ8
DQ7
GND
VCCQ
DQ6
DQ5
GND
GND
VCC
ZZ
DQ4
DQ3
VCCQ
GND
DQ2
DQ1
NC
NC
GND
VCCQ
NC
NC
NC
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A11
A12
A13
A14
A15
A16
A17
A6
A7
CE
CE2
NC
NC
BWb
BWa
CE2
VCC
GND
CLK
WE
CKE
OE
ADV
NC
NC
A8
A9
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCCQ
NC
NC
DQ9
NC
VCCQ
NC
DQ12
VCCQ
NC
DQ14
VCCQ
DQ16
NC
NC
NC
VCCQ
A6
CE2
A7
NC
DQ10
NC
DQ11
NC
VCC
DQ13
NC
DQ15
NC
DQP2
A5
A10
NC
A4
A3
A2
GND
GND
GND
BWb
GND
NC
GND
NC
GND
GND
GND
MODE
A11
NC
NC
ADV
VCC
NC
CE
OE
NC
WE
VCC
CLK
NC
CKE
A1
A0
VCC
NC
NC
A8
A9
A12
GND
GND
GND
NC
GND
NC
GND
BWa
GND
GND
GND
NC
A14
NC
A16
CE2
A15
DQP1
NC
DQ7
NC
DQ5
VCC
NC
DQ3
NC
DQ2
NC
A13
A17
NC
VCCQ
NC
NC
NC
DQ8
VCCQ
DQ6
NC
VCCQ
DQ4
NC
VCCQ
NC
DQ1
NC
ZZ
VCCQ
1 2 3 4 5 6 7
119-pin PBGA (Top View)
100-Pin TQFP
6
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. A
11/11/02
IS61NF12832
IS61NF12836
IS61NF25618
IS61NLF12832
IS61NLF12836
IS61NLF25618
ISSI
SYNCHRONOUS TRUTH TABLE
(1)
Address
Operation
Used
CS
CS
CS
CS
CS
1
CS2
CS
CS
CS
CS
CS
2
ADV
WE
WE
WE
WE
WE
BW
BW
BW
BW
BW
x
OE
OE
OE
OE
OE
CKE
CKE
CKE
CKE
CKE
CLK
Not Selected Continue
N/A
X
X
X
H
X
X
X
L
Begin Burst Read
External Address
L
H
L
L
H
X
L
L
Continue Burst Read
Next Address
X
X
X
H
X
X
L
L
NOP/Dummy Read
External Address
L
H
L
L
H
X
H
L
Dummy Read
Next Address
X
X
X
H
X
X
H
L
Begin Burst Write
External Address
L
H
L
L
L
L
X
L
Continue Burst Write
Next Address
X
X
X
H
X
L
X
L
NOP/Write Abort
N/A
L
H
L
L
L
H
X
L
Write Abort
Next Address
X
X
X
H
X
H
X
L
Ignore Clock
Current Address
X
X
X
X
X
X
X
H
Notes:
1. "X" means don't care.
2. The rising edge of clock is symbolized by
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4.
WE
= L means Write operation in Write Truth Table.
WE
= H means Read operation in Write Truth Table.
5. Operation finally depends on status of asynchronous pins (ZZ and
OE
).
BURST
READ
DESELECT
BURST
WRITE
BEGIN
READ
BEGIN
WRITE
READ
WRITE
READ
WRITE
BURST
BURST
BURST
DS
DS
DS
READ
DS
DS
READ
WRITE
WRITE
BURST
BURST
WRITE
READ
STATE DIAGRAM
Integrated Silicon Solution, Inc. -- www.issi.com --
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Rev. A
11/11/02
IS61NF12832
IS61NF12836
IS61NF25618
IS61NLF12832
IS61NLF12836
IS61NLF25618
ISSI
ASYNCHRONOUS TRUTH TABLE
(1)
Operation
ZZ
OE
OE
OE
OE
OE
I/O STATUS
Sleep Mode
H
X
High-Z
Read
L
L
DQ
L
H
High-Z
Write
L
X
Din, High-Z
Deselected
L
X
High-Z
Notes:
1. X means "Don't Care".
2. For write cycles following read cycles, the output buffers must be disabled with
OE
,
otherwise data bus contention will occur.
3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle
time.
4. Deselected means power Sleep Mode where stand-by current depends on cycle time.
WRITE TRUTH TABLE
(x18)
Operation
WE
WE
WE
WE
WE
BW
BW
BW
BW
BW
a
BW
BW
BW
BW
BW
b
READ
H
X
X
WRITE BYTE a
L
L
H
WRITE BYTE b
L
H
L
WRITE ALL BYTEs
L
L
L
WRITE ABORT/NOP
L
H
H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
WRITE TRUTH TABLE
(x32/x36)
Operation
WE
WE
WE
WE
WE
BW
BW
BW
BW
BW
a
BW
BW
BW
BW
BW
b
BW
BW
BW
BW
BW
c
BW
BW
BW
BW
BW
d
READ
H
X
X
X
X
WRITE BYTE a
L
L
H
H
H
WRITE BYTE b
L
H
L
H
H
WRITE BYTE c
L
H
H
L
H
WRITE BYTE d
L
H
H
H
L
WRITE ALL BYTEs
L
L
L
L
L
WRITE ABORT/NOP
L
H
H
H
H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
8
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. A
11/11/02
IS61NF12832
IS61NF12836
IS61NF25618
IS61NLF12832
IS61NLF12836
IS61NLF25618
ISSI
INTERLEAVED BURST ADDRESS TABLE
(MODE = V
CC
)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A1 A0
A1 A0
A1 A0
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
LINEAR BURST ADDRESS TABLE
(MODE = GND)
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
T
STG
Storage Temperature
65 to +150
C
P
D
Power Dissipation
1.6
W
I
OUT
Output Current (per I/O)
100
mA
V
IN
, V
OUT
Voltage Relative to GND for I/O Pins
0.5 to V
CCQ
+ 0.3
V
V
IN
Voltage Relative to GND for
0.3 to 4.6
V
for Address and Control Inputs
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-
nent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specifi-
cation is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or
electric fields; however, precautions may be taken to avoid application of any voltage higher
than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
0,0
1,0
0,1
A1', A0' = 1,1
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
9
Rev. A
11/11/02
IS61NF12832
IS61NF12836
IS61NF25618
IS61NLF12832
IS61NLF12836
IS61NLF25618
ISSI
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-8.5
-9
-10
MAX
MAX
MAX
Symbol
Parameter
Test Conditions
x18
x32/36
x18
x32/36
x18
x32/36
Unit
I
CC
AC Operating
Device Selected,
Com.
305
305
290
290
275
275
mA
Supply Current
OE
= V
IH
, ZZ
V
IL
,
I
ND
.
--
--
305
305
290
290
All Inputs
0.2V
OR
V
CC
0.2V,
Cycle Time
t
KC
min.
I
SB
Standby Current
Device Deselected,
C
OM
.
90
90
80
80
70
70
mA
TTL Input
V
CC
= Max.,
Ind.
--
--
90
90
80
80
All Inputs
0.2V
OR
V
CC
0.2V,
ZZ
V
IL
, f = Max.
I
SBI
Standby Current
Device Deselected,
Com.
10
10
10
10
10
10
mA
CMOS Input
V
CC
= Max.,
Ind.
--
--
15
15
15
15
V
IN
GND + 0.2V or
V
CC
0.2V
f = 0
Note:
1. MODE pin has an internal pullup and should be tied to Vcc or GND. It exhibits 30 A maximum leakage current when
tied to
GND + 0.2V or
Vcc 0.2V.
OPERATING RANGE
Range
Ambient Temperature
V
CC
V
CCQ
Commercial
0C to +70C
3.3V 5%
3.3V 5%
3.3V 5%
2.5V 5%
Industrial
-40C to +85C
3.3V 5%
3.3V 5%
3.3V 5%
2.5V 5%
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
2.5V
3.3V
Symbol
Parameter
Test Conditions
Min.
Max.
Min.
Max.
Unit
V
OH
Output HIGH Voltage
I
OH
= 4.0 mA (3.3V)
2.0
--
2.4
--
V
I
OH
= 1.0 mA
(2.5V)
V
OL
Output LOW Voltage
I
OL
= 8.0 mA (3.3V)
--
0.4
--
0.4
V
I
OL
= 1.0 mA (2.5V)
V
IH
Input HIGH Voltage
1.7
V
CC
+ 0.3
2.0
V
CC
+ 0.3
V
V
IL
Input LOW Voltage
0.3
0.7
0.3
0.8
V
I
LI
Input Leakage Current
GND
V
IN
V
CC
(1)
5
5
5
5
A
I
LO
Output Leakage Current
GND
V
OUT
V
CCQ
,
OE
= V
I
5
5
5
5
A
10
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11/11/02
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ISSI
CAPACITANCE
(1,2)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Input/Output Capacitance
V
OUT
= 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25C, f = 1 MHz, Vcc = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 3.0V
Input Rise and Fall Times
1.5 ns
Input and Output Timing
1.5V
and Reference Level
Output Load
See Figures 1 and 2
3.3V I/O OUTPUT LOAD EQUIVALENT
Z
O
= 50
1.5V
50
OUTPUT
317
5 pF
Including
jig and
scope
351
OUTPUT
+3.3V
Figure 1
Figure 2
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ISSI
2.5V I/O AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 2.5V
Input Rise and Fall Times
1.5 ns
Input and Output Timing
1.25V
and Reference Level
Output Load
See Figures 3 and 4
2.5V I/O OUTPUT LOAD EQUIVALENT
Z
O
= 50
1.25V
50
OUTPUT
1,667
5 pF
Including
jig and
scope
1,538
OUTPUT
+2.5V
Figure 3
Figure 4
12
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ISSI
READ/WRITE CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-8.5
-9
-10
Symbol
Parameter
Min. Max.
Min. Max.
Min. Max.
Unit
fmax
Clock Frequency
--
100
--
83
--
83
MHz
t
KC
Cycle Time
10
--
12
--
12
--
ns
t
KH
Clock High Time
3
--
3
--
3
--
ns
t
KL
Clock Low Time
3
--
3
--
3
--
ns
t
KQ
Clock Access Time
--
8.5
--
9
--
10
ns
t
KQX
(2)
Clock High to Output Invalid
3
--
3
--
3
--
ns
t
KQLZ
(2,3)
Clock High to Output Low-Z
2.5
--
2.5
--
2.5
--
ns
t
KQHZ
(2,3)
Clock High to Output High-Z
--
5
--
5
--
6
ns
t
OEQ
Output Enable to Output Valid
--
3.5
--
3.5
--
3.5
ns
t
OELZ
(2,3)
Output Enable to Output Low-Z
0
--
0
--
0
--
ns
t
OEHZ
(2,3)
Output Disable to Output High-Z
--
3.5
--
3.5
--
4
ns
t
AS
Address Setup Time
2
--
2
--
2
--
ns
t
WS
Read/Write Setup Time
2
--
2
--
2
--
ns
t
CES
Chip Enable Setup Time
2
--
2
--
2
--
ns
t
SE
Clock Enable Setup Time
2
--
2
--
2
--
ns
t
AVS
Address Advance Setup Time
2
--
2
--
2
--
ns
t
DS
Data Setup Time
2
--
2
--
2
--
ns
t
AH
Address Hold Time
0.5
--
0.5
--
0.5
--
ns
t
HE
Clock EnableHold Time
0.5
--
0.5
--
0.5
--
ns
t
WH
Write Hold Time
0.5
--
0.5
--
0.5
--
ns
t
CEH
Chip Enable Hold Time
0.5
--
0.5
--
0.5
--
ns
t
ADVH
Address Advance Hold Time
0.5
--
0.5
--
0.5
--
ns
t
DH
Data Hold Time
0.5
--
0.5
--
0.5
--
ns
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
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Rev. A
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ISSI
SLEEP MODE TIMING
Don't Care
Deselect or Read Only
Deselect or Read Only
t
RZZI
K
ZZ
Isupply
All Inputs
(except ZZ)
Outputs
(Q)
I
SB2
ZZ setup cycle
ZZ recovery cycle
Normal
operation
cycle
t
PDS
t
PUS
t
ZZI
High-Z
SLEEP MODE ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Min.
Max.
Unit
I
SB
2
Current during SLEEP MODE
ZZ
Vih
10
mA
t
PDS
ZZ active to input ignored
2
cycle
t
PUS
ZZ inactive to input sampled
2
cycle
t
ZZI
ZZ active to SLEEP current
2
cycle
t
RZZI
ZZ inactive to exit SLEEP current
0
ns
14
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ISSI
READ CYCLE TIMING
t
DS
Clock
ADV
A16 - A0 or
A17 - A0
WE
CKE
CE
OE
Data Out
A1
A2
A3
t
KH
t
KL
t
KC
Q3-3
Q3-4
Q3-2
Q3-1
Q2-4
Q2-3
Q2-2
Q2-1
Don't Care
Undefined
NOTES:
WE
= L and
BW
X = L
CE
= L means
CE
1 = L, CE2 = H and
CE
2 = L
CE
= H means
CE
1 = H, or
CE
1 = L and
CE
2 = H, or
CE
1 = L and CE2 = L
t
OEHZ
Q1-1
t
SE
t
HE
t
AS
t
AH
t
WS
t
WH
t
CES
t
CEH
t
KQHZ
t
KQ
t
OEQ
t
OEHZ
t
ADVS
t
ADVH
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ISSI
t
DS
t
DH
A1
A2
A3
t
KH
t
KL
t
KC
t
SE
t
HE
D3-3
D3-4
D3-2
D3-1
D2-4
D2-3
D2-2
D2-1
D1-1
Q0-4
Don't Care
Undefined
NOTES:
WE
= L and
BW
X = L
CE
= L means
CE
1 = L, CE2 = H and
CE
2 = L
CE
= H means
CE
1 = H, or
CE
1 = L and
CE
2 = H, or
CE
1 = L and CE2 = L
t
OEHZ
Clock
ADV
A16 - A0 or
A17 - A0
WE
CKE
CE
OE
Data In
Data Out
WRITE CYCLE TIMING
16
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ISSI
SINGLE READ/WRITE CYCLE TIMING
Clock
CKE
Address
WRITE
CS
ADV
OE
Data Out
Data In
D5
t
SE
t
HE
t
KH
t
KL
t
KC
Don't Care
Undefined
NOTES:
WRITE
= L means
WE
= L and
BW
x = L
CS
= L means
CS
1
= L, CS
2
= H and
CS
2
= L
CS
= H means
CS
1
= H, or
CS
1
= L and
CS
2
= H, or
CS
1
= L and CS
2
= L
D2
t
OELZ
t
OEQ
A1 A2 A3
A4 A5 A6 A7
A8 A9
Q1 Q3 Q4
Q6
Q7
t
DS
t
DH
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ISSI
CKE
CKE
CKE
CKE
CKE
OPERATION TIMING
A1 A2 A3
A4 A5
A6
Q1 Q3
Q4
Clock
CKE
Address
WRITE
CS
ADV
OE
Data Out
Data In
D2
t
SE
t
HE
t
KH
t
KL
t
KC
t
KQLZ
t
KQHZ
t
KQ
t
DH
t
DS
Don't Care
Undefined
NOTES:
WRITE
= L means
WE
= L and
BW
x = L
CS
= L means
CS
1
= L, CS
2
= H and
CS
2
= L
CS
= H means
CS
1
= H, or
CS
1
= L and
CS
2
= H, or
CS
1
= L and CS
2
= L
18
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11/11/02
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ISSI
CS
CS
CS
CS
CS
OPERATION TIMING
Don't Care
Undefined
Clock
CKE
Address
WRITE
CS
ADV
OE
Data Out
Data In
t
SE
t
HE
t
KH
t
KL
t
KC
NOTES:
WRITE
= L means
WE
= L and
BW
x = L
CS
= L means
CS
1
= L, CS
2
= H and
CS
2
= L
CS
= H means
CS
1
= H, or
CS
1
= L and
CS
2
= H, or
CS
1
= L and CS
2
= L
D5
D2
t
DH
t
DS
t
OELZ
t
OEQ
Q1 Q2
Q4
t
KQHZ
t
KQLZ
t
KQ
A1 A2
A3
A4
A5
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Rev. A
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ISSI
ORDERING INFORMATION (6INFxxxxx)
Commercial Range: 0C to +70C
Frequency
Order Part Number
Package
128Kx32
8.5
IS61NF12832-8.5TQ
TQFP
IS61NF12832-8.5B
PBGA
10
IS61NF12832-10TQ
TQFP
IS61NF12832-10B
PBGA
128Kx36
8.5
IS61NF12836-8.5TQ
TQFP
IS61NF12836-8.5B
PBGA
10
IS61NF12836-10TQ
TQFP
256Kx18
8.5
IS61NF25618-8.5TQ
TQFP
IS61NF25618-8.5B
PBGA
10
IS61NF25618-10TQ
TQFP
Industrial Range: -40C to +85C
Frequency
Order Part Number
Package
128Kx32
10
IS61NF12832-10TQI
TQFP
IS61NF12832-10BI
PBGA
128Kx36
10
IS61NF12836-10TQI
TQFP
IS61NF12836-10BI
PBGA
256Kx18
10
IS61NF25618-10TQI
TQFP
IS61NF25618-10BI
PBGA
20
Integrated Silicon Solution, Inc. -- www.issi.com --
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Rev. A
11/11/02
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ISSI
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
ORDERING INFORMATION
(IS61NLFxxxxx)
Commercial Range: 0C to +70C
Frequency
Order Part Number
Package
128Kx32
8.5
IS61NLF12832-8.5TQ
TQFP
IS61NLF12832-8.5B
PBGA
128Kx36
8.5
IS61NLF12836-8.5TQ
TQFP
IS61NLF12836-8.5B
PBGA
10
IS61NLF12836-10TQ
TQFP
256Kx18
8.5
IS61NLF25618-8.5TQ
TQFP
IS61NLF25618-8.5B
PBGA
10
IS61NLF25618-10TQ
TQFP
IS61NLF25618-10B
PBGA
Industrial Range: -40C to +85C
Frequency
Order Part Number
Package
128Kx32
10
IS61NLF12832-10TQI
TQFP
128Kx36
10
IS61NLF12836-10TQI
TQFP
IS61NLF12836-10BI
PBGA
256Kx18
10
IS61NLF25618-10TQI
TQFP
IS61NLF25618-10BI
PBGA
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