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ADVANCED INFORMATION Rev. 00A
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IS61NVVP25672
IS61NVVP51236

ISSI

Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.

FEATURES

· 100 percent bus utilization

· No wait cycles between Read and Write

· Internal self-timed write cycle

· Individual Byte Write Control

· Single R/W (Read/Write) control pin

· Clock controlled, registered address,

data and control

· Interleaved or linear burst sequence control

using MODE input

· Power Down mode

· Common data inputs and data outputs

CKE

pin to enable clock and suspend operation

· JEDEC 119-ball PBGA (x36) and

209-ball (x72) PBGA packages

· Single +1.8V (± 5%) power supply

· JTAG Boundary Scan

· Industrial temperature available

DESCRIPTION

The 16 Meg 'NVVP' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
network and communications customers. They are
organized as 256K words by 72 bits, 512K words
by 36 bits and are fabricated with

ISSI

's advanced CMOS

technology.

Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.

All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable,

CKE

is HIGH. In this state the internal

device will hold their previous values.

All Read, Write and Deselect cycles are initiated by the
ADV input. When the ADV is HIGH the internal burst
counter is incremented. New external addresses can be
loaded when ADV is LOW.

Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when

is LOW.

Separate byte enables allow individual bytes to be written.

A burst mode pin (MODE) defines the order of the burst
sequence. When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.

256K x 72 and 512K x 36, 18Mb
PIPELINE 'NO WAIT' STATE BUS SRAM

ADVANCE INFORMATION

JULY 2002

FAST ACCESS TIME

Symbol

Parameter

-250

-200

Units

Clock Access Time

2.6

3.2

Cycle Time

Frequency

250

200

MHz

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IS61NVVP25672
IS61NVVP51236

ISSI

PIN DESCRIPTIONS

Synchronous Address Inputs

A0, A1

Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.

ADV

Synchronous Burst Address Advance

Synchronous Byte Write Enable

CE2

, CE2 Synchronous Chip Enable

CLK

Synchronous Clock

CKE

Clock Enable

DQa-DQh

Synchronous Data Input/Output

DQPa-DQPh

Parity Data Input/Output

GND

Ground

MODE

Burst Sequence Mode Selection

Output Enable

TCK, TDI

JTAG Boundary Scan Pins

TDO, TMS

+1.8V Power Supply

CCQ

Isolated Output Buffer Supply: 1.8V

Write Enable

Snooze Enable

PIN CONFIGURATION -- 256K X 72, 209-Ball PBGA (TOP VIEW)

DQg

CE2

ADV

CE2

DQb

DQg

DQb

DQg

DQb

DQg

GND

DQb

DQPg

DQPc

CCQ

DQPf

DQPb

DQc

GND

DQf

DQc

CCQ

DQf

DQc

GND

DQf

DQc

CCQ

DQf

CLK

GND

CKE

GND

DQh

CCQ

VCC

CCQ

DQa

DQh

GND

DQa

DQh

CCQ

VCC

CCQ

DQa

DQh

GND

DQa

DQPd

DQPh

CCQ

DQPa

DQPe

DQd

GND

MODE

GND

DQe

DQd

DQe

DQd

DQe

DQd

TMS

TDI

TDO

TCK

DQe

11 x 19 Ball BGA--14 x 22 mm

Body--1 mm Ball Pitch

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IS61NVVP25672
IS61NVVP51236

ISSI

PIN CONFIGURATION

119-pin PBGA (Top View)

512K x 36

PIN DESCRIPTIONS

Synchronous Address Inputs

A0, A1

Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.

ADV

Synchronous Burst Address Advance

Synchronous Byte Write Enable

CE2

, CE2 Synchronous Chip Enable

CLK

Synchronous Clock

CKE

Clock Enable

DQa-DQd

Synchronous Data Input/Output

DQPa-DQPd

Parity Data Input/Output

GND

Ground

MODE

Burst Sequence Mode Selection

Output Enable

TCK, TDI

JTAG Boundary Scan Pins

TDO, TMS

1.8V Power Supply

CCQ

Isolated Output Buffer Supply: 1.8V

Write Enable

Snooze Enable

VCCQ

DQc

VCCQ

DQc

VCCQ

DQd

VCCQ

DQd

VCCQ

CE2

DQPc

DQc

VCC

DQd

DQPd

TMS

GND

MODE

TDI

ADV

VCC

CLK

CKE

VCC

TCK

GND

TDO

CE2

DQPb

DQb

VCC

DQa

DQPa

VCCQ

DQb

VCCQ

DQb

VCCQ

DQa

VCCQ

DQa

VCCQ

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IS61NVVP25672
IS61NVVP51236

ISSI

SYNCHRONOUS TRUTH TABLE

(1)

Address

Operation

Used

CS2

ADV

CKE

CLK

Not Selected Continue

N/A

Not Selected

N/A

Not Selected

N/A

Not Selected

N/A

Begin Burst Read

External Address

Continue Burst Read

Next Address

NOP/Dummy Read

External Address

Dummy Read

Next Address

Begin Burst Write

External Address

Continue Burst Write

Next Address

NOP/Write Abort

N/A

Write Abort

Next Address

Ignore Clock

Current Address

Notes:
1. "X" means don't care.
2. The rising edge of clock is symbolized by

3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4.

= L means Write operation in Write Truth Table.

= H means Read operation in Write Truth Table.

5. Operation finally depends on status of asynchronous pins (ZZ and

STATE DIAGRAM

BURST

READ

DESELECT

BURST

WRITE

BEGIN

READ

BEGIN

WRITE

READ

WRITE

READ

WRITE

BURST

READ

WRITE

BURST

WRITE

READ

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IS61NVVP25672
IS61NVVP51236

ISSI

ASYNCHRONOUS TRUTH TABLE

(1)

Operation

I/O STATUS

Sleep Mode

High-Z

Read

High-Z

Write

Din, High-Z

Deselected

High-Z

Notes:

1. X means "Don't Care".
2. For write cycles following read cycles, the output buffers must be disabled with

otherwise data bus contention will occur.

3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle

time.

4. Deselected means power Sleep Mode where stand-by current depends on cycle time.

WRITE TRUTH TABLE

(x36)

Operation

READ

WRITE BYTE a

WRITE BYTE b

WRITE BYTE c

WRITE BYTE d

WRITE ALL BYTEs

WRITE ABORT/NOP

Notes:

1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.

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IS61NVVP25672
IS61NVVP51236

ISSI

INTERLEAVED BURST ADDRESS TABLE

(MODE = V

)

External Address

1st Burst Address

2nd Burst Address

3rd Burst Address

A1 A0

WRITE TRUTH TABLE

(x72)

Operation

READ

WRITE BYTE a

WRITE BYTE b

WRITE BYTE c

WRITE BYTE d

WRITE BYTE e

WRITE BYTE f

WRITE BYTE g

WRITE BYTE h

WRITE ALL BYTEs

WRITE ABORT/NOP

Notes:

1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.

LINEAR BURST ADDRESS TABLE

(MODE = GND)

0,0

1,0

0,1

A1', A0' = 1,1

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IS61NVVP51236

ISSI

OPERATING RANGE

Range

Ambient Temperature

CCQ

Commercial

0°C to +70°C

1.8V ± 5%

Industrial

-40°C to +85°C

1.8V ± 5%

DC ELECTRICAL CHARACTERISTICS

(Over Operating Range)

1.8V

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

Output HIGH Voltage

= 4.0 mA

CCQ

0.4

Output LOW Voltage

= 4.0 mA

0.4

Input HIGH Voltage

1.1

+ 0.3

Input LOW Voltage

0.3

0.6

Input Leakage Current

GND

(1)

µA

Output Leakage Current

GND

OUT

CCQ

= V

µA

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Parameter

Value

Unit

OPR

Operating Temperature

Com

0 to +70

°C

Ind

-40 to +85

STG

Storage Temperature

65 to +150

°C

Power Dissipation

1.6

OUT

Output Current (per I/O)

100

, V

OUT

Voltage Relative to GND for I/O Pins

0.5 to V

CCQ

+ 0.3

Voltage Relative to GND for

0.5 to V

CCQ

+ 0.3

for Address and Control Inputs

Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-

nent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specifi-
cation is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.

2. This device contains circuity to protect the inputs against damage due to high static voltages or

electric fields; however, precautions may be taken to avoid application of any voltage higher
than maximum rated voltages to this high-impedance circuit.

3. This device contains circuitry that will ensure the output devices are in High-Z at power up.

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IS61NVVP25672
IS61NVVP51236

ISSI

POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-250

-200

MAX

Symbol

Parameter

Test Conditions

x36

x72

x36

x72

Unit

AC Operating

Device Selected,

Com.

450

500

400

450

Supply Current

= V

, ZZ

500

550

450

500

All Inputs

0.2V

0.2V,

Cycle Time

min.

Standby Current

Device Deselected,

225

250

175

200

TTL Input

= Max.,

Ind.

200

230

All Inputs

0.2V

0.2V,

, f = Max.

SBI

Standby Current

Device Deselected,

Com.

150

CMOS Input

= Max.,

Ind.

200

GND + 0.2V or

0.2V

f = 0

Note:
1. MODE pin has an internal pullup and should be tied to Vcc or GND. It exhibits ±30 µA maximum leakage current when tied

GND + 0.2V or

Vcc 0.2V.

CAPACITANCE

(1,2)

Symbol

Parameter

Conditions

Max.

Unit

Input Capacitance

= 0V

OUT

Input/Output Capacitance

OUT

= 0V

Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T

= 25°C, f = 1 MHz, Vcc = 3.3V.

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IS61NVVP25672
IS61NVVP51236

ISSI

READ/WRITE CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

-250

-200

Symbol

Parameter

Min. Max.

Unit

fmax

Clock Frequency

250

200

MHz

Cycle Time

4.0

Clock High Time

1.7

Clock Low Time

1.7

Clock Access Time

2.6

3.0

KQX

(2)

Clock High to Output Invalid

0.8

1.5

KQLZ

(2,3)

Clock High to Output Low-Z

0.8

KQHZ

(2,3)

Clock High to Output High-Z

2.6

3.0

OEQ

Output Enable to Output Valid

2.6

3.0

OELZ

(2,3)

Output Enable to Output Low-Z

OEHZ

(2,3)

Output Disable to Output High-Z

2.6

3.0

Address Setup Time

1.0

1.2

Read/Write Setup Time

1.0

1.2

CES

Chip Enable Setup Time

1.0

1.2

Clock Enable Setup Time

1.0

1.2

ADVS

Address Advance Setup Time

1.0

1.2

Data Setup Time

1.0

1.2

Address Hold Time

0.5

Clock EnableHold Time

0.5

Write Hold Time

0.5

CEH

Chip Enable Hold Time

0.5

ADVH

Address Advance Hold Time

0.5

Data Hold Time

0.5

PDS

ZZ High to Power Down

cyc

PUS

ZZ Low to Power Down

cyc

Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.

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IS61NVVP25672
IS61NVVP51236

ISSI

IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)

The IS61NVVP51236 and IS61NVVP25672 have a serial
boundary scan Test Access Port (TAP) in the PBGA
package only. This port operates in accordance with IEEE
Standard 1149.1-1900, but does not include all functions
required for full 1149.1 compliance. These functions from
the IEEE specification are excluded because they place
added delay in the critical speed path of the SRAM. The
TAP controller operates in a manner that does not conflict
with the performance of other devices using 1149.1 fully
compliant TAPs. The TAP operates using JEDEC standard
1.8V I/O logic levels.

DISABLING THE JTAG FEATURE

The SRAM can operate without using the JTAG feature. To
disable the TAP controller, TCK must be tied LOW (GND)
to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be disconnected. They may
alternately be connected to V

through a pull-up resistor.

TDO should be left disconnected. On power-up, the
device will start in a reset state which will not interfere with
the device operation.

TEST ACCESS PORT (TAP) - TEST CLOCK

The test clock is only used with the TAP controller. All
inputs are captured on the rising edge of TCK and outputs
are driven from the falling edge of TCK.

TEST MODE SELECT (TMS)

The TMS input is used to send commands to the TAP
controller and is sampled on the rising edge of TCK. This
pin may be left disconnected if the TAP is not used. The
pin is internally pulled up, resulting in a logic HIGH level.

TEST DATA-IN (TDI)

The TDI pin is used to serially input information to the
registers and can be connected to the input of any
register. The register between TDI and TDO is chosen by
the instruction loaded into the TAP instruction register.
For information on instruction register loading, see the
TAP Controller State Diagram. TDI is internally pulled up
and can be disconnected if the TAP is unused in an
application. TDI is connected to the Most Significant Bit
(MSB) on any register.

TAP CONTROLLER BLOCK DIAGRAM

31 30 29

. . .

2 1 0

. . . . .

2 1 0

Bypass Register

Instruction Register

Identification Register

Boundary Scan Register*

TAP CONTROLLER

Selection Circuitry

TDO

TDI

TCK

TMS

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TEST DATA OUT (TDO)

The TDO output pin is used to serially clock data-out from
the registers. The output is active depending on the
current state of the TAP state machine (see TAP Controller
State Diagram). The output changes on the falling edge of
TCK and TDO is connected to the Least Significant Bit
(LSB) of any register.

PERFORMING A TAP RESET

A Reset is performed by forcing TMS HIGH (V

) for five

rising edges of TCK. RESET may be performed while the
SRAM is operating and does not affect its operation. At
power-up, the TAP is internally reset to ensure that TDO
comes up in a high-Z state.

TAP REGISTERS

Registers are connected between the TDI and TDO pins
and allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time
through the instruction registers. Data is serially loaded
into the TDI pin on the rising edge of TCK and output on the
TDO pin on the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the
instruction register. This register is loaded when it is
placed between the TDI and TDO pins. (See TAP Controller
Block Diagram) At power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded with
the IDCODE instruction if the controller is placed in a reset
state as previously described.

When the TAP controller is in the CaptureIR state, the two
least significant bits are loaded with a binary "01" pattern
to allow for fault isolation of the board level serial test path.

Bypass Register

To save time when serially shifting data through registers,
it is sometimes advantageous to skip certain states. The
bypass register is a single-bit register that can be placed
between TDI and TDO pins. This allows data to be shifted
through the SRAM with minimal delay. The bypass register

is set LOW (GND) when the BYPASS instruction is
executed.

Boundary Scan Register

The boundary scan register is connected to all input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a 84-bit-long
register and the x72 configuration has a 123-bit-long reg-
ister. The boundary scan register is loaded with the con-
tents of the RAM Input and Output ring when the TAP
controller is in the Capture-DR state and then placed
between the TDI and TDO pins when the controller is moved
to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD
and SAMPLE Z instructions can be used to capture the
contents of the Input and Output ring.

The Boundary Scan Order tables show the order in which
the bits are connected. Each bit corresponds to one of the
bumps on the SRAM package. The MSB of the register is
connected to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit
code during the Capture-DR state when the IDCODE
command is loaded to the instruction register. The IDCODE
is hardwired into the SRAM and can be shifted out when
the TAP controller is in the Shift-DR state. The ID register
has vendor code and other information described in the
Identification Register Definitions table.

Scan Register Sizes

Register Name

Bit Size (x36)

Bit Size (x72)

Instruction

Bypass

Boundary Scan

123

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ISSI

IDENTIFICATION (ID) REGISTER

The ID Register is a 32-bit register that is loaded with a
device and vendor specific 32-bit code when the controller
is put in Capture-DR state with the IDCODE command
loaded in the Instruction Register. The code is loaded from

a 32-bit on-chip ROM. It describes various attributes of the
RAM as indicated below. The register is then placed
between the TDI and TDO pins when the controller is moved
into Shift-DR state. Bit 0 in the register is the LSB and the
first to reach TDO when shifting begins.

ID REGISTER CONTENTS

Die

I/O

ISSI Technology

Revision

Not Used

Configuration

JEDEC Vendor

Code

ID Code

Presence Register

Bit #

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

x72

X X X X

0 0

x36

X X X X 0 0

0 0

0 0 0

0 0

0 1 0

0 0

0 0 0 1

0 1 0

1 0

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ISSI

TAP INSTRUCTION SET

Eight instructions are possible with the three-bit instruction
register and all combinations are listed in the Instruction
Code table. Three instructions are listed as RESERVED
and should not be used and the other five instructions are
described below. The TAP controller used in this SRAM is
not fully compliant with the 1149.1 convention because
some mandatory instructions are not fully implemented.
The TAP controller cannot be used to load address, data or
control signals and cannot preload the Input or Output
buffers. The SRAM does not implement the 1149.1 com-
mands EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; instead it performs a capture of the
Inputs and Output ring when these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed
between TDI and TDO. During this state, instructions are
shifted from the instruction register through the TDI and
TDO pins. To execute an instruction once it is shifted in,
the TAP controller must be moved into the Update-IR
state.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with
all 0s. Because EXTEST is not implemented in the TAP
controller, this device is not 1149.1 standard compliant.
The TAP controller recognizes an all-0 instruction. When
an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is a difference between
the instructions, unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit
code to be loaded into the instruction register. It also
places the instruction register between the TDI and TDO
pins and allows the IDCODE to be shifted out of the device
when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a
test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan
register to be connected between the TDI and TDO pins
when the TAP controller is in a Shift-DR state. It also
places all SRAM outputs into a High-Z state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction.
The PRELOAD portion of this instruction is not imple-
mented, so the TAP controller is not fully 1149.1 compli-
ant. When the SAMPLE/PRELOAD instruction is loaded
to the instruction register and the TAP controller is in the
Capture-DR state, a snapshot of data on the inputs and
output pins is captured in the boundary scan register.

It is important to realize that the TAP controller clock
operates at a frequency up to 10 MHz, while the SRAM
clock runs more than an order of magnitude faster.
Because of the clock frequency differences, it is possible
that during the Capture-DR state, an input or output will
under-go a transition. The TAP may attempt a signal
capture while in transition (metastable state). The device
will not be harmed, but there is no guarantee of the value
that will be captured or repeatable results.

To guarantee that the boundary scan register will capture
the correct signal value, the SRAM signal must be
stabilized long enough to meet the TAP controller's
capture set-up plus hold times (t

and t

). To insure that

the SRAM clock input is captured correctly, designs need
a way to stop (or slow) the clock during a SAMPLE/
PRELOAD instruction. If this is not an issue, it is possible
to capture all other signals and simply ignore the value of
the CLK and

CLK

captured in the boundary scan register.

Once the data is captured, it is possible to shift out the data
by putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.

Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the Update-DR
state while performing a SAMPLE/PRELOAD instruction
will have the same effect as the Pause-DR command.

BYPASS

When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the
bypass register is placed between the TDI and TDO pins.
The advantage of the BYPASS instruction is that it
shortens the boundary scan path when multiple devices
are connected together on a board.

RESERVED

These instructions are not implemented but are reserved
for future use. Do not use these instructions.

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IS61NVVP51236

ISSI

TAP ELECTRICAL CHARACTERISTICS Over the Operating Range

(1,2)

Symbol

Parameter

Test Conditions

Min.

Max.

Units

OH1

Output HIGH Voltage

= 100 µA

Vcc 0.1

OH2

Output HIGH Voltage

= 8 mA

Vcc 0.4

OL1

Output LOW Voltage

= 100 µA

0.1

OL2

Output LOW Voltage

= 8 mA

0.4

Input HIGH Voltage

1.2

+0.3

Input LOW Voltage

OLT

= 2mA

0.3

0.6

Input Leakage Current

GND

V I

DDQ

µA

Notes:

1. All Voltage referenced to Ground.
2. Overshoot: V

(AC)

+1.5V for t

TCYC

/2,

Undershoot:V

(AC)

0.5V for t

TCYC

/2,

Power-up: V

< 2.6V and V

< 2.4V and V

DDQ

< 1.4V for t < 200 ms.

JTAG TAP INSTRUCTION SET SUMMARY

Instruction

Code

Description

EXTEST

(1)

000

Places the Boundary Scan Register between TDI and TDO. When EXTEST is
selected, data will be driven out of the DQ pad.

IDCODE

(1,2)

001

Preloads ID Register and places it between TDI and TDO.

SAMPLE-Z

(1)

010

Captures I/O ring contents. Places the Boundary Scan Register between TDI
and TDO. Forces all Data and Clock output drivers to High-Z.

RFU

(1)

011

Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruc-
tion. Places Bypass Register between TDI and TDO.

SAMPLE/PRELOAD

(1)

100

Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.

Private

(1)

101

Private instruction.

RFU

(1)

110

Do not use this instruction; Reserved for Future Use.

BYPASS

(1)

111

Places Bypass Register between TDI and TDO.

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in Test-Logic-Reset state.

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

ADVANCED INFORMATION Rev. 00A
07/17/02

IS61NVVP25672
IS61NVVP51236

ISSI

TAP AC ELECTRICAL CHARACTERISTICS

(1)

(OVER OPERATING RANGE)

Symbol Parameter

Min.

Max.

Unit

TCYC

TCK Clock cycle time

100

TCK Clock frequency

MHz

TCK Clock HIGH

TCK Clock LOW

TMSS

TMS setup to TCK Clock Rise

TDIS

TDI setup to TCK Clock Rise

Capture setup to TCK Rise

TMSH

TMS hold after TCK Clock Rise

TDIH

TDI Hold after Clock Rise

Capture hold after Clock Rise

TDOV

TCK LOW to TDO valid

TDOX

TCK LOW to TDO invalid

Notes:

7. t

and t

refer to the set-up and hold time requirements of latching data from the boundary scan register.

8. Test conditions are specified using the load in TAP AC test conditions. t

= 1 ns.

TAP CONTROLLER STATE DIAGRAM

Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

Test Logic Reset

Run Test/Idle

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

ADVANCED INFORMATION Rev. 00A
07/17/02

IS61NVVP25672
IS61NVVP51236

ISSI

BOUNDARY SCAN ORDER ASSIGNMENTS (by Exit Sequence) PH =Place Holder

X72

X36

Sequence

Pkg. Ball

Ball Location

Sequence

Pkg. Ball

Ball Location

(1)

Mode

(2)

CKE

(1)

ADV

CE2

(2)

CE2

(1)

(2)

Notes:

1.Input of PH register connected to VSS
2. NC = Don't care

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

ADVANCED INFORMATION Rev. 00A

07/17/02

IS61NVVP25672
IS61NVVP51236

ISSI

BOUNDARY SCAN ORDER ASSIGNMENTS (by Exit Sequence) Continued:

X72

X36

Sequence

Pkg. Ball

Ball Location

Sequence

Pkg. Ball

Ball Location

(2)

DQd

DQPd

DQPh

DQh

(2)

DQc

Notes:

1.Input of PH register connected to VSS

2. NC = Don't care

Integrated Silicon Solution, Inc. -- www.issi.com --

1-800-379-4774

ADVANCED INFORMATION Rev. 00A
07/17/02

IS61NVVP25672
IS61NVVP51236

ISSI

BOUNDARY SCAN ORDER ASSIGNMENTS (by Exit Sequence) Continued:

X72

X36

Sequence

Pkg. Ball

Ball Location

Sequence

Pkg. Ball

Ball Location

DQc

DQPc

DQPg

DQg

DQb

A10

DQb

A11

DQb

B10

DQb

B11

DQb

C10

DQb

C11

DQb

D10

DQb

D11

DQb

DQPb

E11

DQPb

DQPf

E10

DQf

F10

DQf

F11

DQf

G10

DQf

G11

100

DQf

H10

101

DQf

H11

102

DQf

J10

103

DQf

J11

104

(2)

K11

(2)

105

(2)

K10

(2)

106

DQa

L10

DQa

107

DQa

L11

DQa

108

DQa

M10

DQa

109

DQa

M11

DQa

110

DQa

N10

DQa

Notes:

1.Input of PH register connected to VSS

2. NC = Don't care

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IS61NVVP25672-250B

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IS61NVVP25672-250B