IS61NW6432

Integrated Silicon Solution, Inc.

ADVANCE INFORMATION

SR050-0B

07/15/98

This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible
product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.

FEATURES

· Fast access time:

5 ns-100 MHz; 6 ns-83 MHz;
7 ns-75 MHz; 8 ns-66 MHz

· No wait cycles between Read and Write

· Internal self-timed write cycle

· Individual Byte Write Control

· Clock controlled, registered address, data and

control

· PentiumTM or linear burst sequence control

using MODE input

· Three chip enables for simple depth expansion

and address pipelining

· Common data inputs and data outputs

· JEDEC 100-pin TQFP and PQFP package

· Single +3.3V power supply

· Optional data strobe pin (#80) for latching data

(See page 12 for detailed timing)

DESCRIPTION

The IS61NW6432 is a high-speed, low-power synchronous
static RAM designed to provide a burstable, high-
performance, 'no-wait' bus, secondary cache for the Pentium,
680X0, and Power PC microprocessors. It is organized as
65,536 words by 32 bits, fabricated with

ISSI

's advanced

CMOS technology.

Incorporating a 'no-wait' bus, wait cycles are eliminated when
the bus switches from read to write, or write to read. This
device integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single monolithic
circuit.

All synchronous inputs pass through registers controlled by a
positive-edge-triggered clock input. Operations may be
suspended and all synchronous inputs ignored when Clock
Enable,

CEN

is HIGH. In this state the internal device will hold

their previous values.

When the ADV/

is HIGH the internal burst counter is

incremented. New external addresses can be loaded when
ADV/

is LOW.

Write cycles are internally self-timed and are initiated by the
rising edge of the clock inputs and when RD/

is LOW.

Separate byte enables allow individual bytes to be written.

BW1

controls I/O1-I/O8;

BW2

controls I/O9-I/O16;

BW3

controls

I/O17-I/O24;

BW4

controls I/O25-I/O32. All Bytes are written

when

BW1

BW2

BW3

, and

BW4

are LOW.

MODE pin upon power up is in interleave burst mode. It can be
connected to GNDQ or VCCQ to alter power up state.

IS61NW6432

64K x 32 SYNCHRONOUS STATIC RAM
WITH NO-WAIT STATE BUS FEATURE

ADVANCE INFORMATION

JULY 1998

ISSI

IS61NW6432

Integrated Silicon Solution, Inc.

ADVANCE INFORMATION

SR050-0B

07/15/98

NC
I/O16
I/O15
VCCQ
GNDQ
I/O14
I/O13
I/O12
I/O11
GNDQ
VCCQ
I/O10
I/O9
GND
VCC
VCC
GND
I/O8
I/O7
VCCQ
GNDQ
I/O6
I/O5
I/O4
I/O3
GNDQ
VCCQ
I/O2
I/O1
NC

CE1

CE2

BW4

BW3

BW2

BW1

CE3

VCC

GND

CLK

R/W

CEN

ADV/LD

I/O17
I/O18

VCCQ

GNDQ

I/O19
I/O20
I/O21
I/O22

GNDQ

VCCQ

I/O23
I/O24

VCC
VCC
VCC

GND

I/O25
I/O26

VCCQ

GNDQ

I/O27
I/O28
I/O29
I/O30

GNDQ

VCCQ

I/O31
I/O32

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

MODE

GND

VCC

A10

A11

A12

A13

A14

A15

46 47 48 49 50

PIN CONFIGURATION

100-Pin TQFP and PQFP (Top View)

PIN DESCRIPTIONS

A0-A15

Address Inputs

CLK

Clock

CEN

Clock Enable

ADV/

Advance Load

BW1

BW4

Synchronous Byte Write Enable

Read/Write

CE1

, CE2,

CE3

Synchronous Chip Enable

Output Enable

(1)

Data Strobe

I/O1-I/O32

Data Input/Output

MODE

Burst Sequence Mode

+3.3V Power Supply

GND

Ground

CCQ

Isolated Output Buffer Supply: +3.3V

GND

Isolated Output Buffer Ground

No Connect

Note:
1. Optional, NC or DS.

IS61NW6432

Integrated Silicon Solution, Inc.

ADVANCE INFORMATION

SR050-0B

07/15/98

TRUTH TABLE

(1)

Address

Operation

Used

CEx

ADV/

CEN

BWx

CLK

Begin New Write Cycle

External

Valid

L-H

Begin New Read Cycle

External

L-H

Advance Burst Counter

(2)

Internal

Valid

L-H

(Burst Write)

Advance Burst Counter

Internal

L-H

(Burst Read)

Deselect (2 Cycle)

(3)

L-H

Hold/NOOP

(4)

L-H

Notes:
1. "X" Means don't care.
2. When ADV/

signal is sampled HIGH, the internal burst counter is incremented. The R/

signal is ignored when the

counter is advanced. Therefore, the nature of the burst cycle (Read or Write) is determined by the status of the R/

signal

when the first address is loaded at the beginning of the burst cycle.

3. Deselect cycle is initiated when

CEx

is sampled HIGH and ADV/

sampled LOW at rising edge of clock. The data bus will

tri-state two cycles after deselect is initiated.

4. When

CEN

is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part.

The state of all the internal registers remains unchanged.

PARTIAL TRUTH TABLE

(Non-burst)

Function

BW1

BW2

BW3

BW4

CEx

ADV/

Read

Write Byte 1

Write Byte 2

Write Byte 3

Write Byte 4

Write All Bytes

n+29

n+30

n+31

n+32

n+33

n+34

n+35

n+36

n+37

CLOCK

ADDRESS

(A0-A15)

CONTROL

(BWx, R/W, ADV/LD)

DATA

(I/O1-I/O32)

CYCLE

A29

A30

A31

A32

A33

A34

A35

A36

A37

C29

C30

C31

C32

C33

C34

C35

C36

C37

D27

D28

D29

D30

D31

D32

D33

D34

D35

FUNCTIONAL TIMING DIAGRAM

IS61NW6432

Integrated Silicon Solution, Inc.

ADVANCE INFORMATION

SR050-0B

07/15/98

TYPICAL OPERATION

(

CE1

CE3

and

CEN

are LOW, CE2 is HIGH, Non-Burst Operation)

Cycle Address

ADV/

CEx

CEN

BWx

I/O

Comments

n+1

n+2

Data Out

n+3

Data In

n+4

Data Out

n+5

Data In

n+6

Data Out

n+7

Data In

n+8

Data Out

n+9

Data In

n+10

A10

Data Out

n+11

A11

Data In

n+12

A12

D10

Data Out

n+13

A13

D11

Data Out

n+14

A14

D12

Data In

n+15

A15

D13

Data In

n+16

A16

D14

Data Out

n+17

A17

D15

Data Out

n+18

A18

D16

Data Out

n+19

A19

D17

Data In

n+20

A20

D18

Data In

n+21

A21

D19

Data In

Note:
1. H = High; L = Low; X = Don't Care; ? = Don't Know; Z = High Impedance

IS61NW6432

Integrated Silicon Solution, Inc.

ADVANCE INFORMATION

SR050-0B

07/15/98

READ OPERATION

Cycle

Address

ADV/

LD CEx

CEx

CEN

BWx

I/O

Comments

Address and Control meet setup

n+1

Clock Setup Valid

n+2

Contents of Address A0 Read Out

BURST READ OPERATION

Cycle

Address

ADV/

LD CEx

CEx

CEN

BWx

I/O

Comments

Address and Control meet setup

n+1

Clock Setup Valid, Advance Counter

n+2

Address A0 Read Out, Inc. Count

n+3

D0+1

Address A0+1 Read Out, Inc. Count

n+4

D0+2

Address A0+2 Read Out, Inc. Count

n+5

D0+3

Address A0+3 Read Out, Load A1

n+6

Address A0 Read Out, Inc. Count

n+7

Address A1 Read Out, Inc. Count

n+8

D1+1

Address A1+1 Read Out, Load A2

WRITE OPERATION

Cycle

Address

ADV/LD

CEx

CEN

BWx

I/O

Comments

Address and Control meet setup

n+1

Clock Setup Valid

n+2

Write D0 to Address A0

BURST WRITE OPERATION

Cycle

Address

ADV/

LD CEx

CEx

CEN

BWx

I/O

Comments

Address and Control meet setup

n+1

Clock Setup Valid, Inc. Count

n+2

Address A0 Write, Inc. Count

n+3

D0+1

Address A0+1 Write, Inc. Count

n+4

D0+2

Address A0+2 Write, Inc. Count

n+5

D0+3

Address A0+3 Write, Load A1

n+6

Address A0 Write, Inc. Count

n+7

Address A1 Write, Inc. Count

n+8

D1+1

Address A1+1 Write, Load A2

Note:
1. H = High; L = Low; X = Don't Care; ? = Don't Know; Z = High Impedance

IS61NW6432

Integrated Silicon Solution, Inc.

ADVANCE INFORMATION

SR050-0B

07/15/98

READ OPERATION WITH CLOCK ENABLE USED

Cycle

Address

ADV/

LD CEx

CEx

CEN

BWx

I/O

Comments

Address and Control meet setup

n+1

Clock n+1 Ignored

n+2

Clock Valid

n+3

Clock Ignored. Data D0 is on the bus

n+4

Clock Ignored. Data D0 is on the bus

n+5

Address A0 Read Out (bus trans.)

n+6

Address A1 Read Out (bus trans.)

n+7

Address A2 Read Out (bus trans.)

WRITE OPERATION WITH CLOCK ENABLE USED

Cycle

Address

ADV/

LD CEx

CEx

CEN

BWx

I/O

Comments

Address and Control meet setup

n+1

Clock n+1 Ignored

n+2

Clock Valid

n+3

Clock Ignored.

n+4

Clock Ignored.

n+5

Write data D0 (bus trans.)

n+6

Write data D1 (bus trans.)

n+7

Write data D2 (bus trans.)

Note:
1. H = High; L = Low; X = Don't Care; ? = Don't Know; Z = High Impedance; di could be D0 if desired.

IS61NW6432

Integrated Silicon Solution, Inc.

ADVANCE INFORMATION

SR050-0B

07/15/98

INTERLEAVED BURST ADDRESS TABLE

(MODE = V

CCQ

or No Connect)

External Address

1st Burst Address

2nd Burst Address

3rd Burst Address

A1 A0

LINEAR BURST ADDRESS TABLE

(MODE = GND

)

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Parameter

Value

Unit

BIAS

Temperature Under Bias

10 to +85

STG

Storage Temperature

55 to +150

Power Dissipation

1.8

OUT

Output Current (per I/O)

100

, V

OUT

Voltage Relative to GND for I/O Pins

0.5 to V

CCQ

+ 0.3

Voltage Relative to GND for

0.5 to 5.5

for Address and Control Inputs

Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

2. This device contains circuity to protect the inputs against damage due to high static

voltages or electric fields; however, precautions may be taken to avoid application of
any voltage higher than maximum rated voltages to this high-impedance circuit.

3. This device contains circuitry that will ensure the output devices are in High-Z at power

up.

0,0

1,0

0,1

A1', A0' = 1,1

IS61NW6432

Integrated Silicon Solution, Inc.

ADVANCE INFORMATION

SR050-0B

07/15/98

OPERATING RANGE

Range

Ambient Temperature

Commercial

C to +70

3.3V +10%, 5%

DC ELECTRICAL CHARACTERISTICS

(1)

(Over Operating Range)

Symbol Parameter

Test Conditions

Min.

Max.

Unit

Output HIGH Voltage

= 5.0 mA

2.4

Output LOW Voltage

= 5.0 mA

0.4

Input HIGH Voltage

2.0

CCQ

+ 0.3

Input LOW Voltage

0.3

0.8

Input Leakage Current

GND

CCQ

(2)

Com.

Output Leakage Current

GND

OUT

CCQ

= V

Com.

POWER SUPPLY CHARACTERISTICS

(Over Operating Range)

-5

-6

-7

-8

Symbol Parameter

Test Conditions

Min. Max.

Min. Max. Unit

AC Operating

Device Selected,

Com.

230

220

210

200

Supply Current

All Inputs = V

or V

= V

, Cycle Time

min.

Standby Current

Device Deselected,

Com.

= Max.,

All Inputs = V

or V

CLK Cycle Time

min.,

CEN

= V

Notes:
1. MODE pin has an internal pull up. This pin may be a No Connect, tied to GND, or tied to V

CCQ

2. MODE pin should be tied to Vcc or GND. It exhibits

A maximum leakage current when

tied to

GND + 0.2V or

Vcc 0.2V.

IS61NW6432

Integrated Silicon Solution, Inc.

ADVANCE INFORMATION

SR050-0B

07/15/98

CAPACITANCE

(1,2)

Symbol

Parameter

Conditions

Max.

Unit

Input Capacitance

= 0V

OUT

Input/Output Capacitance

OUT

= 0V

Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T

= 25

C, f = 1 MHz, Vcc = 3.3V.

AC TEST CONDITIONS

Parameter

Unit

Input Pulse Level

0V to 3.0V

Input Rise and Fall Times

1.5 ns

Input and Output Timing

1.5V

and Reference Level

Output Load

See Figures 1 and 2

AC TEST LOADS

Figure 1

Output
Buffer

= 50

1.5V

30 pF

317

5 pF

Including

jig and

scope

351

OUTPUT

3.3V

Figure 2

IS61NW6432

Integrated Silicon Solution, Inc.

ADVANCE INFORMATION

SR050-0B

07/15/98

READ/WRITE CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

-5

-6

-7

-8

Symbol

Parameter

Min. Max.

Min.

Max.

Unit

fmax

Clock Frequency

100

MHz

Cycle Time

Clock High Time

Clock Low Time

Clock Access Time

KQX

(2)

Clock High to Output Invalid

1.5

KQLZ

(2,3)

Clock High to Output Low-Z

2.0

KQHZ

(2,3)

Clock High to Output High-Z

1.5

3.5

OEQ

Output Enable to Output Valid

OEQX

(2)

Output Disable to Output Invalid

OELZ

(2,3)

Output Enable to Output Low-Z

OEHZ

(2,3)

Output Disable to Output High-Z

3.5

Address Setup Time

2.0

Read/Write Setup Time

2.0

CES

Chip Enable Setup Time

2.0

Clock Enable Setup Time

2.0

AVS

Address Advance Setup Time

2.0

Address Hold Time

0.5

Clock EnableHold Time

0.5

Write Hold Time

0.5

CEH

Chip Enable Hold Time

0.5

ALS

Advance/Load (ADV/

) Setup Time

2.0

ALH

Advance/Load (ADV/

) Hold Time

0.5

tds

Data Setup Time

2.0

tdh

Data Hold Time

0.5

tzq

I/O From Tri-State to Valid

1.5

2.5

1.5

2.5

1.5

2.5

1.5

2.5

Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.

IS61NW6432

Integrated Silicon Solution, Inc.

ADVANCE INFORMATION

SR050-0B

07/15/98

READ/WRITE CYCLE TIMING

Single Read

Single Write

High-Z

DATA

OUT

DATA
STROBE

DATA

CE3

CE2

CE1

BW4-BW1

R/W

A15-A0

ADV/LD

CLK

CEN

RD1

RD2

RD3

WR1

Unselected

Burst Read

KQX

ALS

ALH

AVS

RD4

RD5

CES

CEH

CES

CEH

CES

CEH

Unselected with CE3

OEQ

OELZ

KQLZ

KQX

KQHZ

OEQX

OEHZ

High-Z

IS61NW6432

Integrated Silicon Solution, Inc.

ADVANCE INFORMATION

SR050-0B

07/15/98

ORDERING INFORMATION

Commercial Range: 0

C to +70

Speed (ns)

Order Part Number

Package

IS61NW6432-5TQ

TQFP

IS61NW6432-5PQ

PQFP

IS61NW6432-6TQ

TQFP

IS61NW6432-6PQ

PQFP

IS61NW6432-7TQ

TQFP

IS61NW6432-7PQ

PQFP

IS61NW6432-8TQ

TQFP

IS61NW6432-8PQ

PQFP

NOTICE

Integrated Silicon Solution, Inc., reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. Integrated Silicon Solution, Inc. assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits
are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may
vary depending upon a user's specific application. While the information in this publication has been carefully checked,
Integrated Silicon Solution, Inc. shall not be liable for any damages arising as a result of any error or omission.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure
or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect
its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc.
receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes
all such risks; and (c) potential liability of Integrated Silicon Solution, Inc. is adequately protected under the circumstances.

Reproduction in whole or in part, without the prior written consent of Integrated Silicon Solution, Inc., is prohibited.

Integrated Silicon Solution, Inc.

2231 Lawson Lane

Santa Clara, CA 95054

Tel: 1-800-379-4774
Fax: (408) 588-0806

e-mail: sales@issi.com

http://www.issi.com

ISSI

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