IS61SF25616
IS61SF25618
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
1
Rev. A
04/17/01
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. Copyright 2001, Integrated Silicon Solution, Inc.
FEATURES
Fast access times: 8 ns, 8.5 ns, 10 ns, and 12 ns
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data inputs
and control signals
Pentium
TM
or linear burst sequence control
using MODE input
Three chip enables for simple depth expansion
and address pipelining
Common data inputs and data outputs
JEDEC 100-Pin TQFP and
119-pin PBGA package
Single +3.3V +10%, 5% power supply
Power-down snooze mode
256K x 16, 256K x 18 SYNCHRONOUS
FLOW-THROUGH STATIC RAM
APRIL 2001
FAST ACCESS TIME
Symbol
Parameter
8
8.5
10
12
Units
t
KQ
Clock Access Time
8
8.5
10
12
ns
t
KC
Cycle Time
10
11
15
15
ns
Frequency
100
90
66
66
MHz
DESCRIPTION
The
ISSI
IS61SF25616 and IS61SF25618 is a high-speed,
low-power synchronous static RAM designed to provide
a burstable, high-performance memory for high speed
networking and communication applications. It is organized
as 262,144 words by 16 bits and 18 bits, fabricated with
ISSI
's advanced CMOS technology. The device integrates
a 2-bit burst counter, high-speed SRAM core, and high-drive
capability outputs into a single monolithic circuit. All
synchronous inputs pass through registers controlled by
a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be from
one to four bytes wide as controlled by the write control
inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQ1-8, BW2 controls DQ9-16, conditioned
by
BWE being LOW. A LOW on GW input would cause all
bytes to be written.
Bursts can be initiated with either
ADSP (Address Status
Processor) or
ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally by the IS61SF25616 and controlled by the
ADV
(burst address advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
IS61SF25616
IS61SF25618
ISSI
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A
04/17/01
BLOCK DIAGRAM
BURST
COUNTER
A2-A17
A1
A0
GW
MODE
ADSC
ADSP
ADDRESS
REGISTER
BW1
BYTE WRITE
REGISTER
BW2
BYTE WRITE
REGISTER
ENABLE
REGISTER
ENABLE
REGISTER
BWE
BW1
BW2
256K x 16, 256K x 18
MEMORY ARRAY
16
or
18
DATA INPUT
REGISTER
CLK
16
or
18
2
ADV
CLK
2
18
18
16
2
CLK2
CLK2
CLK
OE
CE1
CE2
CE2
CLR
DQ1-DQ16
or
DQ1-DQ18
IS61SF25616
IS61SF25618
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
3
Rev. A
04/17/01
PIN CONFIGURATION
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A17
Synchronous Address Inputs
CLK
Synchronous Clock
ADSP
Synchronous Processor Address
Status
ADSC
Synchronous Controller Address
Status
ADV
Synchronous Burst Address Advance
BW1-BW2
Synchronous Byte Write Enable
BWE
Synchronous Byte Write Enable
GW
Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE
Output Enable
DQ1-DQ16
Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
V
CC
+3.3V Power Supply
GND
Ground
V
CCQ
Isolated Output Buffer Supply: +3.3V
ZZ
Snooze Enable
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCCQ
NC
NC
DQ9
NC
VCCQ
NC
DQ12
VCCQ
NC
DQ14
VCCQ
DQ16
NC
NC
NC
VCCQ
A6
CE2
A7
NC
DQ10
NC
DQ11
NC
VCC
DQ13
NC
DQ15
NC
NC
A5
A11
NC
A4
A3
A2
GND
GND
GND
BW2
GND
NC
GND
GND
GND
GND
GND
MODE
A10
NC
ADSP
ADSC
VCC
NC
CE
OE
ADV
GW
VCC
CLK
NC
BWE
A1
A0
VCC
NC
NC
A8
A9
A12
GND
GND
GND
GND
GND
NC
GND
BW1
GND
GND
GND
GND
A14
NC
A16
CE2
A15
NC
NC
DQ7
NC
DQ5
VCC
NC
DQ3
NC
DQ2
NC
A13
A17
NC
VCCQ
NC
NC
NC
DQ8
VCCQ
DQ6
NC
VCCQ
DQ4
NC
VCCQ
NC
DQ1
NC
ZZ
VCCQ
1 2 3 4 5 6 7
A17
NC
NC
VCCQ
GND
NC
NC
DQ8
DQ7
GND
VCCQ
DQ6
DQ5
GND
NC
VCC
ZZ
DQ4
DQ3
VCCQ
GND
DQ2
DQ1
NC
NC
GND
VCCQ
NC
NC
NC
A6
A7
CE
CE2
NC
NC
BW2
BW1
CE2
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
NC
NC
NC
VCCQ
GND
NC
NC
DQ9
DQ10
GND
VCCQ
DQ11
DQ12
GND
VCC
NC
GND
DQ13
DQ14
VCCQ
GND
DQ15
DQ16
NC
NC
GND
VCCQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
46 47 48 49 50
256K x 16
119-pin PBGA (Top View)
100-Pin TQFP
IS61SF25616
IS61SF25618
ISSI
4
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A
04/17/01
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A17
Synchronous Address Inputs
CLK
Synchronous Clock
ADSP
Synchronous Processor Address
Status
ADSC
Synchronous Controller Address
Status
ADV
Synchronous Burst Address Advance
BW1-BW2
Synchronous Byte Write Enable
BWE
Synchronous Byte Write Enable
GW
Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE
Output Enable
DQ1-DQ16
Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
V
CC
+3.3V Power Supply
GND
Ground
V
CCQ
Isolated Output Buffer Supply: 3.3V
ZZ
Snooze Enable
DQP1-DQP2
Parity Data I/O DQP1 is parity for
DQ1-8; DQP2 is parity for DQ9-16
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCCQ
NC
NC
DQ9
NC
VCCQ
NC
DQ12
VCCQ
NC
DQ14
VCCQ
DQ16
NC
NC
NC
VCCQ
A6
CE2
A7
NC
DQ10
NC
DQ11
NC
VCC
DQ13
NC
DQ15
NC
DQP2
A5
A11
NC
A4
A3
A2
GND
GND
GND
BW2
GND
NC
GND
GND
GND
GND
GND
MODE
A10
NC
ADSP
ADSC
VCC
NC
CE
OE
ADV
GW
VCC
CLK
NC
BWE
A1
A0
VCC
NC
NC
A8
A9
A12
GND
GND
GND
GND
GND
NC
GND
BW1
GND
GND
GND
GND
A14
NC
A16
CE2
A15
DQP1
NC
DQ7
NC
DQ5
VCC
NC
DQ3
NC
DQ2
NC
A13
A17
NC
VCCQ
NC
NC
NC
DQ8
VCCQ
DQ6
NC
VCCQ
DQ4
NC
VCCQ
NC
DQ1
NC
ZZ
VCCQ
1 2 3 4 5 6 7
A17
NC
NC
VCCQ
GND
NC
DQP1
DQ8
DQ7
GND
VCCQ
DQ6
DQ5
GND
NC
VCC
ZZ
DQ4
DQ3
VCCQ
GND
DQ2
DQ1
NC
NC
GND
VCCQ
NC
NC
NC
A6
A7
CE
CE2
NC
NC
BW2
BW1
CE2
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
NC
NC
NC
VCCQ
GND
NC
NC
DQ9
DQ10
GND
VCCQ
DQ11
DQ12
GND
VCC
NC
GND
DQ13
DQ14
VCCQ
GND
DQ15
DQ16
DQP2
NC
GND
VCCQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
46 47 48 49 50
256K x 18
119-pin PBGA (Top View)
100-Pin TQFP
IS61SF25616
IS61SF25618
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
5
Rev. A
04/17/01
TRUTH TABLE
Address
Operation
Used
CE
CE2
CE2
ADSP ADSC
ADV WRITE
OE
DQ
Deselected, Power-down
None
H
X
X
X
L
X
X
X
High-Z
Deselected, Power-down
None
L
X
H
L
X
X
X
X
High-Z
Deselected, Power-down
None
L
L
X
L
X
X
X
X
High-Z
Deselected, Power-down
None
X
X
H
H
L
X
X
X
High-Z
Deselected, Power-down
None
X
L
X
H
L
X
X
X
High-Z
Read Cycle, Begin Burst
External
L
H
L
L
X
X
X
X
Q
Read Cycle, Begin Burst
External
L
H
L
H
L
X
Read
X
Q
Write Cycle, Begin Burst
External
L
H
L
H
L
X
Write
X
D
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
Read
L
Q
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
Read
H
High-Z
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
Read
L
Q
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
Read
H
High-Z
Write Cycle, Continue Burst
Next
X
X
X
H
H
L
Write
X
D
Write Cycle, Continue Burst
Next
H
X
X
X
H
L
Write
X
D
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
Read
L
Q
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
Read
H
High-Z
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
Read
L
Q
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
Read
H
High-Z
Write Cycle, Suspend Burst
Current
X
X
X
H
H
H
Write
X
D
Write Cycle, Suspend Burst
Current
H
X
X
X
H
H
Write
X
D
PARTIAL TRUTH TABLE
Function
GW
BWE
BW1
BW2
Read
H
H
X
X
Read
H
L
H
H
Write Byte 1
H
L
L
H
Write All Bytes
H
L
L
L
Write All Bytes
L
X
X
X
IS61SF25616
IS61SF25618
ISSI
6
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A
04/17/01
INTERLEAVED BURST ADDRESS TABLE (MODE = V
CC
or No Connect)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A1 A0
A1 A0
A1 A0
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = GND)
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
T
BIAS
Temperature Under Bias
40 to +85
C
T
STG
Storage Temperature
55 to +150
C
P
D
Power Dissipation
1.6
W
I
OUT
Output Current (per I/O)
100
mA
V
IN
, V
OUT
Voltage Relative to GND for I/O Pins
0.5 to V
CCQ
+ 0.3
V
V
IN
Voltage Relative to GND for
0.5 to V
CC
+ 0.5
V
for Address and Control Inputs
V
CC
Voltage on Vcc Supply Relatiive to GND
0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. This device contains circuitry to protect the inputs against damage due to high static
voltages or electric fields; however, precautions may be taken to avoid application of any
voltage higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
0,0
1,0
0,1
A1', A0' = 1,1
IS61SF25616
IS61SF25618
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
7
Rev. A
04/17/01
OPERATING RANGE
Range
Ambient Temperature
V
CC
Commercial
0C to +70C
3.3V
+10%, 5%
Industrial
40C to +85C
3.3V
+10%, 5%
DC ELECTRICAL CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
I
OH
= 4.0 mA
2.4
--
V
V
OL
Output LOW Voltage
I
OL
= 8.0 mA
--
0.4
V
V
IH
Input HIGH Voltage
2.0
V
CC
+ 0.3
V
V
IL
Input LOW Voltage
0.3
0.8
V
I
LI
Input Leakage Current
GND
V
IN
V
CCQ
(2)
Com.
2
2
A
Ind.
5
5
I
LO
Output Leakage Current
GND
V
OUT
V
CCQ
,
OE = V
IH
Com.
2
2
A
Ind.
5
5
POWER SUPPLY CHARACTERISTICS
(Over Operating Range)
8
8.5
10
12
Symbol
Parameter
Test Conditions
Max.
Max.
Max.
Max.
Unit
I
CC
AC Operating
Device Selected,
Com.
180
170
160
150
mA
Supply Current
All Inputs = V
IL
or V
IH
Ind.
--
180
170
160
OE = V
IH
, Vcc = Max.
Cycle Time
t
KC
min.
I
SB
Standby Current
Device Deselected,
Com.
50
50
50
50
mA
V
CC
= Max.,
Ind.
--
60
60
60
All Inputs = V
IH
or V
IL
CLK Cycle Time
t
KC
min.
I
ZZ
Power-down
ZZ = V
CCQ
Com.
10
10
10
10
mA
Mode Current
Clock Running
Ind.
--
15
15
15
All Inputs
GND + 0.2V
or
Vcc 0.2V
Notes:
1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to GND, or tied to V
CC
.
2. The MODE pin should be tied to Vcc or GND. It exhibits 10 A maximum leakage current when tied to
GND + 0.2V
or
Vcc 0.2V.
IS61SF25616
IS61SF25618
ISSI
8
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A
04/17/01
CAPACITANCE
(1,2)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Input/Output Capacitance
V
OUT
= 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25C, f = 1 MHz, Vcc = 3.3V.
AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 3.0V
Input Rise and Fall Times
1.5 ns
Input and Output Timing
1.5V
and Reference Level
Output Load
See Figures 1 and 2
AC TEST LOADS
Figure 2
Figure 1
Output
Buffer
Z
O
= 50
1.5V
50
30 pF
317
5 pF
Including
jig and
scope
351
OUTPUT
3.3V
IS61SF25616
IS61SF25618
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
9
Rev. A
04/17/01
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
8
8.5
10
12
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
f
MAX
(3)
Clock Frequency
--
100
--
90
--
66
--
66
MHz
t
KC
(3)
Cycle Time
10
--
11
--
15
--
15
--
ns
t
KH
Clock High Time
4
--
4.5
--
4.5
--
4.5
--
ns
t
KL
(3)
Clock Low Time
4
--
4.5
--
4.5
--
4.5
--
ns
t
KQ
(3)
Clock Access Time
--
8
--
8.5
--
10
--
12
ns
t
KQX
(1)
Clock High to Output Invalid
2
--
2
--
2
--
2
--
ns
t
KQLZ
(1,2)
Clock High to Output Low-Z
0
--
0
--
0
--
0
--
ns
t
KQHZ
(1,2)
Clock High to Output High-Z
2
3.5
2
3.5
2
3.5
2
3.5
ns
t
OEQ
(3)
Output Enable to Output Valid
--
3.5
--
3.5
--
3.5
--
5
ns
t
OELZ
(1,2)
Output Enable to Output Low-Z
0
--
0
--
0
--
0
--
ns
t
OEHZ
(1,2)
Output Disable to Output High-Z
--
3.5
--
3.5
--
3.5
--
3.5
ns
t
AS
(3)
Address Setup Time
2
--
2
--
2
--
4
--
ns
t
SS
(3)
Address Status Setup Time
2
--
2
--
2
--
4
--
ns
t
WS
(3)
Write Setup Time
2
--
2
--
2
--
4
--
ns
t
CES
(3)
Chip Enable Setup Time
2
--
2
--
2
--
4
--
ns
t
AVS
(3)
Address Advance Setup Time
2
--
2
--
2
--
4
--
ns
t
AH
(3)
Address Hold Time
0.5
--
0.5
--
0.5
--
1.5
--
ns
t
SH
(3)
Address Status Hold Time
0.5
--
0.5
--
0.5
--
1.5
--
ns
t
WH
(3)
Write Hold Time
0.5
--
0.5
--
0.5
--
1.5
--
ns
t
CEH
(3)
Chip Enable Hold Time
0.5
--
0.5
--
0.5
--
1.5
--
ns
t
AVH
(3)
Address Advance Hold Time
0.5
--
0.5
--
0.5
--
1.5
--
ns
Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
3. Tested with load in Figure 1.
IS61SF25616
IS61SF25618
ISSI
10
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A
04/17/01
READ/WRITE CYCLE TIMING
Single Read
Flow-through
Single Write
High-Z
High-Z
DATA
OUT
DATA
IN
OE
CE2
CE2
CE
BW2-BW1
BWE
GW
A17-A0
ADV
ADSC
ADSP
CLK
RD1
WR1
WR1
1a
1a
2a
2b
2c
2d
Unselected
Burst Read
t
KQX
t
KC
t
KL
t
KH
t
SS
t
SH
ADSP is blocked by CE inactive
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
t
WS
t
WH
RD2
RD3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE2 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2
t
OEQX
t
KQ
t
OEHZ
t
KQX
t
KQHZ
t
DS
t
DH
t
KQHZ
t
KQLZ
IS61SF25616
IS61SF25618
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
11
Rev. A
04/17/01
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
8
8.5
10
12
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
KC
(1)
Cycle Time
10
--
11
--
15
--
15
--
ns
t
KH
(1)
Clock High Time
4
--
4.5
--
4.5
--
4.5
--
ns
t
KL
(1)
Clock Low Time
4
--
4.5
--
4.5
--
4.5
--
ns
t
AS
(1)
Address Setup Time
2
--
2
--
2
--
4
--
ns
t
SS
(1)
Address Status Setup Time
2
--
2
--
2
--
4
--
ns
t
WS
(1)
Write Setup Time
2
--
2
--
2
--
4
--
ns
t
DS
(1)
Data In Setup Time
2
--
2
--
2
--
4
--
ns
t
CES
(1)
Chip Enable Setup Time
2
--
2
--
2
--
4
--
ns
t
AVS
(1)
Address Advance Setup Time
2
--
2
--
2
--
4
--
ns
t
AH
(1)
Address Hold Time
0.5
--
0.5
--
0.5
--
1.5
--
ns
t
SH
(1)
Address Status Hold Time
0.5
--
0.5
--
0.5
--
1.5
--
ns
t
DH
(1)
Data In Hold Time
0.5
--
0.5
--
0.5
--
1.5
--
ns
t
WH
(1)
Write Hold Time
0.5
--
0.5
--
0.5
--
1.5
--
ns
t
CEH
(1)
Chip Enable Hold Time
0.5
--
0.5
--
0.5
--
1.5
--
ns
t
AVH
(1)
Address Advance Hold Time
0.5
--
0.5
--
0.5
--
1.5
--
ns
Notes:
1. Tested with load in Figure 1.
IS61SF25616
IS61SF25618
ISSI
12
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A
04/17/01
WRITE CYCLE TIMING
Single Write
DATA
OUT
DATA
IN
OE
CE2
CE2
CE
BW2-BW1
BWE
GW
A17-A0
ADV
ADSC
ADSP
CLK
WR1
WR2
Unselected
Burst Write
t
KC
t
KL
t
KH
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
WR3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE3 only sampled with ADSP or ADSC
CE1 Masks ADSP
Unselected with CE2
ADSC initiate Write
ADSP is blocked by CE1 inactive
t
AVH
t
AVS
ADV must be inactive for ADSP Write
WR1
WR2
t
WS
t
WH
WR3
t
WS
t
WH
High-Z
High-Z
1a
3a
t
DS
t
DH
BW4-BW1 only are applied to first cycle of WR2
Write
2c
2d
2b
2a
IS61SF25616
IS61SF25618
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
13
Rev. A
04/17/01
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
8
8.5
10
12
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
KC
(3)
Cycle Time
10
--
11
--
15
--
15
--
ns
t
KH
(3)
Clock High Time
4
--
4.5
--
4.5
--
4.5
--
ns
t
KL
(3)
Clock Low Time
4
--
4.5
--
4.5
--
4.5
--
ns
t
KQ
(3)
Clock Access Time
--
8
--
8.5
--
10
--
12
ns
t
KQX
(1)
Clock High to Output Invalid
2
--
2
--
2
--
2
--
ns
t
KQLZ
(1,2)
Clock High to Output Low-Z
0
--
0
--
0
--
0
--
ns
t
KQHZ
(1,2)
Clock High to Output High-Z
2
3.5
2
3.5
2
3.5
2
3.5
ns
t
OEQ
(3)
Output Enable to Output Valid
--
3.5
--
3.5
--
3.5
--
5
ns
t
OELZ
(1,2)
Output Enable to Output Low-Z
0
--
0
--
0
--
0
--
ns
t
OEHZ
(1,2)
Output Disable to Output High-Z
--
3.5
--
3.5
--
3.5
--
3.5
ns
t
AS
(3)
Address Setup Time
2
--
2
--
2
--
4
--
ns
t
SS
(3)
Address Status Setup Time
2
--
2
--
2
--
4
--
ns
t
CES
(3)
Chip Enable Setup Time
2
--
2
--
2
--
4
--
ns
t
AH
(3)
Address Hold Time
0.5
--
0.5
--
0.5
--
1.5
--
ns
t
SH
(3)
Address Status Hold Time
0.5
--
0.5
--
0.5
--
1.5
--
ns
t
CEH
(3)
Chip Enable Hold Time
0.5
--
0.5
--
0.5
--
1.5
--
ns
t
ZZS
ZZ Standby
2
--
2
--
2
--
2
--
cyc
t
ZZREC
ZZ Recovery
2
--
2
--
2
--
2
--
cyc
Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
3. Tested with load in Figure 1.
IS61SF25616
IS61SF25618
ISSI
14
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A
04/17/01
SNOOZE AND RECOVERY CYCLE TIMING
Single Read
High-Z
High-Z
DATA
OUT
DATA
IN
OE
CE2
CE2
CE
BW2-BW1
BWE
GW
A17-A0
ADV
ADSC
ADSP
CLK
RD1
1a
Read
Snooze with Data Retention
t
KC
t
KL
t
KH
t
SS
t
SH
t
AS
t
AH
RD2
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
t
OEQ
t
OEQX
t
OELZ
t
KQLZ
t
KQ
t
OEHZ
t
KQX
t
KQHZ
ZZ
t
ZZS
t
ZZREC
IS61SF25616
IS61SF25618
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
15
Rev. A
04/17/01
ORDERING INFORMATION
Commercial Range: 0C to +70C
Frequency
Order Part Number
Package
8
IS61SF25616-8TQ
TQFP
IS61SF25616-8B
PBGA
8.5
IS61SF25616-8.5TQ
TQFP
IS61SF25616-8.5B
PBGA
10
IS61SF25616-10TQ
TQFP
IS61SF25616-10B
PBGA
12
IS61SF25616-12TQ
TQFP
IS61SF25616-12B
PBGA
Industrial Range: 40C to +85C
Frequency
Order Part Number
Package
8.5
IS61SF25616-8.5TQI
TQFP
10
IS61SF25616-10TQI
TQFP
12
IS61SF25616-12TQI
TQFP
IS61SF25616
IS61SF25618
ISSI
16
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A
04/17/01
ORDERING INFORMATION
Commercial Range: 0C to +70C
Frequency
Order Part Number
Package
8
IS61SF25618-8TQ
TQFP
IS61SF25618-8B
PBGA
8.5
IS61SF25618-8.5TQ
TQFP
IS61SF25618-8.5B
PBGA
10
IS61SF25618-10TQ
TQFP
IS61SF25618-10B
PBGA
12
IS61SF25618-12TQ
TQFP
IS61SF25618-12B
PBGA
Industrial Range: 40C to +85C
Frequency
Order Part Number
Package
8.5
IS61SF25618-8.5TQI
TQFP
10
IS61SF25618-10TQI
TQFP
12
IS61SF25618-12TQI
TQFP
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
PDF 
ZIP