Integrated Silicon Solution, Inc. -- 1-800-379-4774
1
Rev. B
02/01/02
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. Copyright 2001, Integrated Silicon Solution, Inc.
IS61SP6464
ISSI
FEATURES
Fast access time:
117, 100 MHz; 6 ns (83 MHz);
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and
control
PentiumTM or linear burst sequence control
using MODE input
Five chip enables for simple depth expansion
and address pipelining
Common data inputs and data outputs
Power-down control by ZZ input
JEDEC 128-Pin TQFP 14mm x 20mm
package
Single +3.3V power supply
Control pins mode upon power-up:
MODE in interleave burst mode
ZZ in normal operation mode
These control pins can be connected to GND
Q
or V
CCQ
to alter their power-up state
DESCRIPTION
The
ISSI
IS61SP6464 is a high-speed, low-power synchro-
nous static RAM designed to provide a burstable, high-
performance, secondary cache for the i486TM, PentiumTM,
680X0TM, and PowerPCTM microprocessors. It is organized
as 65,536 words by 64 bits, fabricated with
ISSI
's advanced
CMOS technology. The device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs into
a single monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
eight bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls I/O1-I/O8, BW2 controls I/O9-I/O16, BW3 con-
trols I/O17-I/O24,
BW4 controls I/O25-I/O32, BW5 controls
I/O33-I/O40,
BW6 controls I/O41-I/O48, BW7 controls I/O49-
I/O56,
BW8 controls I/O57-I/O64, conditioned by BWE being
LOW. A LOW on
GW input would cause all bytes to be written.
Bursts can be initiated with either
ADSP (Address Status
Processor) or
ADSC (Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated inter-
nally by the IS61SP6464 and controlled by the
ADV (burst
address advance) input pin.
Asynchronous signals include output enable (
OE), sleep mode
input (ZZ), and burst mode input (MODE). A HIGH input on the
ZZ pin puts the SRAM in the power-down state. When ZZ is
pulled LOW (or no connect), the SRAM normally operates
after the wake-up period. A LOW input, i.e., GND
Q
, on MODE
pin selects LINEAR Burst. A V
CCQ
(or no connect) on MODE
pin selects INTERLEAVED Burst.
64K x 64 SYNCHRONOUS
PIPELINE STATIC RAM
FEBRUARY 2002
IS61SP6464
ISSI
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B
02/01/02
BLOCK DIAGRAM
16
BINARY
COUNTER
A15-A0
BW1
GW
CLR
CE
CLK
Q0
Q1
MODE
A0'
A0
A1
A1'
CLK
ADV
ADSC
ADSP
14
16
ADDRESS
REGISTER
CE
D
CLK
Q
DQ57-DQ64
BYTE WRITE
REGISTERS
D
CLK
Q
DQ8-DQ1
BYTE WRITE
REGISTERS
D
CLK
Q
ENABLE
REGISTER
CE
D
CLK
Q
ENABLE
DELAY
REGISTER
D
CLK
Q
BWE
BW8
CE
CE2
CE2
CE3
CE3
64K x 64
MEMORY
ARRAY
64
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
64
OE
8
64
OE
DATA[64:1]
IS61SP6464
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
3
Rev. B
02/01/02
PIN CONFIGURATION
128-Pin TQFP
VCCQ
I/O
32
I/O
31
I/O
30
I/O
29
I/O
28
I/O
27
I/O
26
I/O
25
I/O
24
I/O
23
I/O
22
GNDQ
VCCQ
I/O
21
I/O
20
I/O
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
I/O
12
GNDQ
VCCQ
I/O
11
I/O
10
I/O
9
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
GNDQ
VCCQ
CE3
CE2
CE3
CE2
GND
VCC
CE
BW8
BW7
BW6
BW5
OE
CLK
BWE
GW
BW4
BW3
GND
VCC
BW2
BW1
ADSC
ADSP
ADV
GNDQ
GNDQ
I/O
33
I/O
34
I/O
35
I/O
36
I/O
37
I/O
38
I/O
39
I/O
40
I/O
41
I/O
42
I/O
43
VCCQ
GNDQ
I/O
44
I/O
45
I/O
46
I/O
47
I/O
48
I/O
49
I/O
50
I/O
51
I/O
52
I/O
53
VCCQ
GNDQ
I/O
54
I/O
55
I/O
56
I/O
57
I/O
58
I/O
59
I/O
60
I/O
61
I/O
62
I/O
63
I/O
64
VCCQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
GNDQ
NC
MODE
A15
A14
A13
VCC
GND
A12
A11
A10
A9
A8
NC
A7
A6
A5
A4
A3
VCC
GND
A2
A1
A0
ZZ
VCCQ
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
PIN DESCRIPTIONS
A0-A15
Address Inputs
CLK
Clock
ADSP
Processor Address Status
ADSC
Controller Address Status
ADV
Burst Address Advance
BW1-BW8
Synchronous Byte Write Enable
BWE
Byte Write Enable
GW
Global Write Enable
CE, CE2, CE2,
Synchronous Chip Enable
CE3,
CE3
OE
Output Enable
I/O1-I/O64
Data Input/Output
ZZ
Sleep Mode
MODE
Burst Sequence Mode
V
CC
+3.3V Power Supply
GND
Ground
V
CCQ
Isolated Output Buffer Supply:
+3.3V
NC
No Connect
GND
Q
Isolated Output Buffer Ground
IS61SP6464
ISSI
4
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B
02/01/02
TRUTH TABLE
ADDRESS
OPERATION
USED
CE3
CE2
CE3
CE2
CE
ADSP ADSC ADV WRITE
OE CLK
I/O
Deselected, Power-down
None
X
X
X
X
H
X
L
X
X
X
L-H
High-Z
Deselected, Power-down
None
L
X
X
X
L
L
X
X
X
X
L-H
High-Z
Deselected, Power-down
None
X
L
X
X
L
L
X
X
X
X
L-H
High-Z
Deselected, Power-down
None
X
X
H
X
L
L
X
X
X
X
L-H
High-Z
Deselected, Power-down
None
X
X
X
H
L
L
X
X
X
X
L-H
High-Z
Deselected, Power-down
None
L
X
X
X
L
H
L
X
X
X
L-H
High-Z
Deselected, Power-down
None
X
L
X
X
L
H
L
X
X
X
L-H
High-Z
Deselected, Power-down
None
X
X
H
X
L
H
L
X
X
X
L-H
High-Z
Deselected, Power-down
None
X
X
X
H
L
H
L
X
X
X
L-H
High-Z
Read Cycle, Begin Burst
External
H
H
L
L
L
L
X
X
X
L
L-H
Dout
Read Cycle, Begin Burst
External
H
H
L
L
L
L
X
X
X
H
L-H
High-Z
Write Cycle, Begin Burst
External
H
H
L
L
L
H
L
X
L
X
L-H
Din
Read Cycle, Begin Burst
External
H
H
L
L
L
H
L
X
H
L
L-H
Dout
Read Cycle, Begin Burst
External
H
H
L
L
L
H
L
X
H
H
L-H
High-Z
Read Cycle, Continue Burst
Next
X
X
X
X
X
H
H
L
H
L
L-H
Dout
Read Cycle, Continue Burst
Next
X
X
X
X
X
H
H
L
H
H
L-H
High-Z
Read Cycle, Continue Burst
Next
X
X
X
X
H
X
H
L
H
L
L-H
Dout
Read Cycle, Continue Burst
Next
X
X
X
X
H
X
H
L
H
H
L-H
High-Z
Write Cycle, Continue Burst
Next
X
X
X
X
X
H
H
L
L
X
L-H
Din
Write Cycle, Continue Burst
Next
X
X
X
X
H
X
H
L
L
X
L-H
Din
Read Cycle, Suspend Burst
Current
X
X
X
X
X
H
H
H
H
L
L-H
Dout
Read Cycle, Suspend Burst
Current
X
X
X
X
X
H
H
H
H
H
L-H
High-Z
Read Cycle, Suspend Burst
Current
X
X
X
X
H
X
H
H
H
L
L-H
Dout
Read Cycle, Suspend Burst
Current
X
X
X
X
H
X
H
H
H
H
L-H
High-Z
Write Cycle, Suspend Burst
Current
X
X
X
X
X
H
H
H
L
X
L-H
Din
Write Cycle, Suspend Burst
Current
X
X
X
X
H
X
H
H
L
X
L-H
Din
Notes:
1. All inputs except
OE must meet setup and hold times for the Low-to-High transition of clock (CLK).
2. Wait states are inserted by suspending burst.
3. X means don't care.
WRITE=L means any one or more byte write enable signals (BW1-BW8) and BWE are LOW or GW is LOW.
WRITE=H means all byte write enable signals are HIGH.
4. For a Write operation following a Read operation,
OE must be HIGH before the input data required setup time and held HIGH
throughout the input data hold time.
5.
ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more
byte write enable signals and
BWE LOW or GW LOW for the subsequent L-H edge of clock.
IS61SP6464
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
5
Rev. B
02/01/02
ASYNCHRONOUS TRUTH TABLE
Operation
ZZ
OE
I/O STATUS
Pipelined
Read
L
L
Dout
Pipelined
Read
L
H
High-Z
Write
L
L
High-Z
Write
L
H
Din
Deselect
L
X
High-Z
Sleep
H
X
High-Z
WRITE TRUTH TABLE
Operation
GW
BWE
BW8
BW7
BW6
BW5
BW4
BW3
BW2
BW1
Read
H
H
X
X
X
X
X
X
X
X
Read
H
L
H
H
H
H
H
H
H
H
Write all bytes
H
L
L
L
L
L
L
L
L
L
Write all bytes
L
X
X
X
X
X
X
X
X
X
Write Byte 1
H
L
H
H
H
H
H
H
H
L
Write Byte 2
H
L
H
H
H
H
H
H
L
H
Write Byte 3
H
L
H
H
H
H
H
L
H
H
Write Byte 4
H
L
H
H
H
H
L
H
H
H
Write Byte 5
H
L
H
H
H
L
H
H
H
H
Write Byte 6
H
L
H
H
L
H
H
H
H
H
Write Byte 7
H
L
H
L
H
H
H
H
H
H
Write Byte 8
H
L
L
H
H
H
H
H
H
H
INTERLEAVED BURST ADDRESS TABLE
(MODE = V
CC
or No Connect)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A1 A0
A1 A0
A1 A0
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
IS61SP6464
ISSI
6
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B
02/01/02
LINEAR BURST ADDRESS TABLE
(MODE = GND
Q
)
0,0
1,0
0,1
A1', A0' = 1,1
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
T
BIAS
Temperature Under Bias
40 to +85
C
T
STG
Storage Temperature
55 to +150
C
P
D
Power Dissipation
1.0
W
I
OUT
Output Current (per I/O)
100
mA
V
IN
, V
OUT
Voltage Relative to GND for I/O Pins
0.5 to V
CCQ
+ 0.3
V
V
IN
Voltage Relative to GND for
0.5 to 5.5
V
for Address and Control Inputs
V
CC
Voltage on Vcc Supply Relatiive to GND
0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages
or electric fields; however, precautions may be taken to avoid application of any voltage
higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
OPERATING RANGE
Range
Ambient Temperature
V
CC
Commercial
0C to +70C
3.3V +10%, 5%
Industrial
40C to +85C
3.3V +10%, 5%
IS61SP6464
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
7
Rev. B
02/01/02
DC ELECTRICAL CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
I
OH
= 4.0 mA
2.4
--
V
V
OL
Output LOW Voltage
I
OL
= 8 mA
--
0.4
V
V
IH
Input HIGH Voltage
2.0
V
CCQ
+ 0.3
V
V
IL
Input LOW Voltage
0.3
0.8
V
I
LI
Input Leakage Current
GND - V
IN
- V
CCQ
(2)
Com.
2
2
A
Ind.
10
10
I
LO
Output Leakage Current
GND - V
OUT
- V
CCQ
,
OE = V
IH
Com.
2
2
A
Ind.
10
10
CAPACITANCE
(1,2)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
5
pF
C
OUT
Input/Output Capacitance
V
OUT
= 0V
7
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25C, f = 1 MHz, Vcc = 3.3V.
AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 3.0V
Input Rise and Fall Times
1.5 ns
Input and Output Timing
1.5V
and Reference Level
Output Load
See Figures 1 and 2
AC TEST LOADS
Output
Buffer
Z
O
= 50
1.5V
50
30 pF
Figure 1
Figure 2
317
5 pF
Including
jig and
scope
351
OUTPUT
3.3V
IS61SP6464
ISSI
8
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B
02/01/02
POWER SUPPLY CHARACTERISTICS
(Over Operating Range)
-117
-100
-6
Symbol Parameter
Test Conditions
Max.
Max.
Max.
Unit
I
CC
AC Operating
Device Selected,
Com.
270
250
200
mA
Supply Current
All Inputs = V
IL
or V
IH
Ind.
270
220
OE = V
IH
,
Cycle Time t
KC
min.
I
SB
1
Standby Current
Device Deselected,
Com.
70
70
70
mA
TTL Inputs
V
CC
= Max.,
Ind.
80
80
All Inputs = V
IH
or V
IL
CLK Cycle Time t
KC
min.
I
SB
2
Standby Current
Device Deselected,
Com.
20
20
20
mA
CMOS Inputs
V
CC
= Max.,
Ind.
30
30
V
IN
= V
CC
0.2V, or V
IN
- 0.2V
CLK Cycle Time t
KC
min.
I
ZZ
Power-Down Mode
ZZ = V
CCQ
, CLK Running
Com.
20
20
20
mA
Current
All Inputs - GND + 0.2V
Ind.
30
30
or V
CC
0.2V
Notes:
1. The MODE pin has an internal pullup. ZZ pin has an internal pull-down. This pin may be a No Connect, tied to GND, or tied to
V
CCQ
.
2. The MODE pin should be tied to Vcc or GND. It exhibits 10 A maximum leakage current when tied to - GND + 0.2V
or Vcc 0.2V.
IS61SP6464
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
9
Rev. B
02/01/02
READ CYCLE SWITCHING CHARACTERISTICS
(Over Operating Range)
-117 MHz
-100 MHz
-6ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
KC
Cycle Time
9.2
--
10
--
12
--
`ns
t
KH
Clock High Time
3.4
--
4
--
4.5
--
ns
t
KL
Clock Low Time
3.4
--
4
--
4.5
--
ns
t
KQ
Clock Access Time
--
5
--
5
--
6
ns
t
KQX
(1)
Clock High to Output Invalid
1.5
--
2.5
--
2.5
--
ns
t
KQLZ
(1,2)
Clock High to Output Low-Z
0
--
0
--
0
--
ns
t
KQHZ
(1,2)
Clock High to Output High-Z
2
5
2
5
2
5
ns
t
OEQ
Output Enable to Output Valid
--
5
--
5
--
5
ns
t
OEQX
(1)
Output Disable to Output Invalid
0
--
0
--
0
--
ns
t
OELZ
(1,2)
Output Enable to Output Low-Z
0
--
0
--
0
--
ns
t
OEHZ
(1,2)
Output Disable to Output High-Z
2
5
2
5
2
5
ns
t
AS
Address Setup Time
2.5
--
2.5
--
2.5
--
ns
t
SS
Address Status Setup Time
2.5
--
2.5
--
2.5
--
ns
t
WS
Write Setup Time
2.5
--
2.5
--
2.5
--
ns
t
CES
Chip Enable Setup Time
2.5
--
2.5
--
2.5
--
ns
t
AVS
Address Advance Setup Time
2.5
--
2.5
--
2.5
--
ns
t
AH
Address Hold Time
0.5
--
0.5
--
0.5
--
ns
t
SH
Address Status Hold Time
0.5
--
0.5
--
0.5
--
ns
t
WH
Write Hold Time
0.5
--
0.5
--
0.5
--
ns
t
CEH
Chip Enable Hold Time
0.5
--
0.5
--
0.5
--
ns
t
AVH
Address Advance Hold Time
0.5
--
0.5
--
0.5
--
ns
Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
IS61SP6464
ISSI
10
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B
02/01/02
READ CYCLE TIMING
Single Read
High-Z
High-Z
DATA
OUT
DATA
IN
OE
CE2, CE3
CE2, CE3
CE
BW8-BW1
BWE
GW
A15-A0
ADV
ADSC
ADSP
CLK
RD1
RD2
1a
2c
2d
3a
Unselected
Burst Read
t
KQX
t
KC
t
KL
t
KH
t
SS
t
SH
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
RD3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE3, CE2 and CE2, CE3 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2, CE3
t
OEQ
t
OEQX
t
OELZ
t
KQLZ
t
KQ
t
OEHZ
t
KQHZ
ADSC initiate read
ADSP is blocked by CE inactive
t
AVH
t
AVS
Suspend Burst
Pipelined Read
2a
2b
IS61SP6464
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
11
Rev. B
02/01/02
WRITE CYCLE SWITCHING CHARACTERISTICS
(Over Operating Range)
-117MHz
-100
MHz
-6
MHz
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
KC
Cycle Time
9.2
--
10
--
12
--
ns
t
KH
Clock High Time
3.4
--
4
--
4.5
--
ns
t
KL
Clock Low Time
3.4
--
4
--
4.5
--
ns
t
AS
Address Setup Time
2.5
--
2.5
--
2.5
--
ns
t
SS
Address Status Setup Time
2.5
--
2.5
--
2.5
--
ns
t
WS
Write Setup Time
2.5
--
2.5
--
2.5
--
ns
t
DS
Data In Setup Time
2.5
--
2.5
--
2.5
--
ns
t
CES
Chip Enable Setup Time
2.5
--
2.5
--
2.5
--
ns
t
AVS
Address Advance Setup Time
2.5
--
2.5
--
2.5
--
ns
t
AH
Address Hold Time
0.5
--
0.5
--
0.5
--
ns
t
SH
Address Status Hold Time
0.5
--
0.5
--
0.5
--
ns
t
DH
Data In Hold Time
0.5
--
0.5
--
0.5
--
ns
t
WH
Write Hold Time
0.5
--
0.5
--
0.5
--
ns
t
CEH
Chip Enable Hold Time
0.5
--
0.5
--
0.5
--
ns
t
AVH
Address Advance Hold Time
0.5
--
0.5
--
0.5
--
ns
IS61SP6464
ISSI
12
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B
02/01/02
WRITE CYCLE TIMING
Single Write
DATA
OUT
DATA
IN
OE
CE2, CE3
CE2, CE3
CE
BW8-BW1
BWE
GW
A15-A0
ADV
ADSC
ADSP
CLK
WR1
WR2
Unselected
Burst Write
t
KC
t
KL
t
KH
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
WR3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE3, CE2 and CE2, CE3 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2, CE3
ADSC initiate Write
ADSP is blocked by CE inactive
t
AVH
t
AVS
ADV must be inactive for ADSP Write
WR1
WR2
t
WS
t
WH
WR3
t
WS
t
WH
High-Z
High-Z
1a
3a
t
DS
t
DH
BW8-BW1 only are applied to first cycle of WR2
Write
2c
2d
2b
2a
IS61SP6464
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
13
Rev. B
02/01/02
READ/WRITE CYCLE SWITCHING CHARACTERISTICS
(Over Operating Range)
-117 MHz
-100 MHz
-6 MHz
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
KC
Cycle Time
9.2
--
10
--
12
--
ns
t
KH
Clock High Time
3.4
--
4
--
4.5
--
ns
t
KL
Clock Low Time
3.4
--
4
--
4.5
--
ns
t
KQ
Clock Access Time
--
5
--
5
--
6
ns
t
KQX
(1)
Clock High to Output Invalid
1.5
--
2.5
--
2.5
--
ns
t
KQLZ
(1,2)
Clock High to Output Low-Z
0
--
0
--
0
--
ns
t
KQHZ
(1,2)
Clock High to Output High-Z
2
5
2
5
2
5
ns
t
OEQ
Output Enable to Output Valid
--
5
--
5
--
5
ns
t
OEQX
(1)
Output Disable to Output Invalid
0
--
0
--
0
--
ns
t
OELZ
(1,2)
Output Enable to Output Low-Z
0
--
0
--
0
--
ns
t
OEHZ
(1,2)
Output Disable to Output High-Z
2
5
2
5
2
5
ns
t
AS
Address Setup Time
2.5
--
2.5
--
2.5
--
ns
t
SS
Address Status Setup Time
2.5
--
2.5
--
2.5
--
ns
t
WS
Write Setup Time
2.5
--
2.5
--
2.5
--
ns
t
CES
Chip Enable Setup Time
2.5
--
2.5
--
2.5
--
ns
t
AH
Address Hold Time
0.5
--
0.5
--
0.5
--
ns
t
SH
Address Status Hold Time
0.5
--
0.5
--
0.5
--
ns
t
WH
Write Hold Time
0.5
--
0.5
--
0.5
--
ns
t
CEH
Chip Enable Hold Time
0.5
--
0.5
--
0.5
--
ns
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
IS61SP6464
ISSI
14
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B
02/01/02
READ/WRITE CYCLE TIMING
Single Read
Single Write
High-Z
High-Z
DATA
OUT
DATA
IN
OE
CE2, CE3
CE2, CE3
CE
BW8-BW1
BWE
GW
A15-A0
ADV
ADSC
ADSP
CLK
RD1
WR1
WR1
1a
1a
2a
2b
2c
2d
Unselected
Burst Read
t
KQX
t
KC
t
KL
t
KH
t
SS
t
SH
ADSP is blocked by CE inactive
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
t
WS
t
WH
RD2
RD3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2, CE3 and CE2, CE3 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2, CE3
t
OEQ
t
OEQX
t
OELZ
t
KQLZ
t
KQ
t
OEHZ
t
KQX
t
KQHZ
t
DS
t
DH
t
KQHZ
IS61SP6464
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
15
Rev. B
02/01/02
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS
(Over Operating Range)
-117 MHz
-100 MHz
-6 MHz
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
KC
Cycle Time
9.2
--
10
--
12
--
ns
t
KH
Clock High Time
3.4
--
4
--
4.5
--
ns
t
KL
Clock Low Time
3.4
--
4
--
4.5
--
ns
t
KQ
Clock Access Time
--
5
--
5
--
6
ns
t
KQX
(3)
Clock High to Output Invalid
1.5
--
2.5
--
2.5
--
ns
t
KQLZ
(3,4)
Clock High to Output Low-Z
0
--
0
--
0
--
ns
t
KQHZ
(3,4)
Clock High to Output High-Z
2
5
2
5
2
5
ns
t
OEQ
Output Enable to Output Valid
--
5
--
5
--
5
ns
t
OEQX
(3)
Output Disable to Output Invalid
0
--
0
--
0
--
ns
t
OELZ
(3,4)
Output Enable to Output Low-Z
0
--
0
--
0
--
ns
t
OEHZ
(3,4)
Output Disable to Output High-Z
2
5
2
5
2
5
ns
t
AS
Address Setup Time
2.5
--
2.5
--
2.5
--
ns
t
SS
Address Status Setup Time
2.5
--
2.5
--
2.5
--
ns
t
CES
Chip Enable Setup Time
2.5
--
2.5
--
2.5
--
ns
t
AH
Address Hold Time
0.5
--
0.5
--
0.5
--
ns
t
SH
Address Status Hold Time
0.5
--
0.5
--
0.5
--
ns
t
CEH
Chip Enable Hold Time
0.5
--
0.5
--
0.5
--
ns
t
ZZS
ZZ Standby
(1)
2
--
2
--
2
--
cyc
t
ZZREC
ZZ Recovery
(2)
2
--
2
--
2
--
cyc
Notes:
1. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data
retention is guaranteed when ZZ is asserted and clock remains active.
2.
ADSC and ADSP must not be asserted for at least 2 cyc after leaving ZZ state.
3. Guaranteed but not 100% tested. This parameter is periodically sampled.
4. Tested with load in Figure 2.
IS61SP6464
ISSI
16
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B
02/01/02
SNOOZE AND RECOVERY CYCLE TIMING
Single Read
High-Z
High-Z
DATA
OUT
DATA
IN
OE
CE2, CE3
CE2, CE3
CE
BW8-BW1
BWE
GW
A15-A0
ADV
ADSC
ADSP
CLK
RD1
1a
Read
Snooze with Data Retention
t
KC
t
KL
t
KH
t
SS
t
SH
t
AS
t
AH
RD2
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
t
OEQ
t
OEQX
t
OELZ
t
KQLZ
t
KQ
t
OEHZ
t
KQX
t
KQHZ
ZZ
t
ZZS
t
ZZREC
IS61SP6464
ISSI
Integrated Silicon Solution, Inc. -- 1-800-379-4774
17
Rev. B
02/01/02
ORDERING INFORMATION
Commercial Range: 0C to +70C
Speed
Order Part Number
Package
117
IS61SP6464-117TQ
TQFP
IS61SP6464-117PQ
PQFP
100
IS61SP6464-100TQ
TQFP
IS61SP6464-100PQ
PQFP
83
IS61SP6464-6TQ
TQFP
IS61SP6464-6PQ
PQFP
Industrial Range: 40C to +85C
Speed
Order Part Number
Package
100
IS61SP6464-100TQI
TQFP
IS61SP6464-100PQI
PQFP
83
IS61SP6464-6TQI
TQFP
IS61SP6464-6PQI
PQFP
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
PDF 
ZIP