IS63LV1024L
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
1
Rev. B
08/07/02
Copyright 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
128K x 8 HIGH-SPEED CMOS STATIC RAM
3.3V REVOLUTIONARY PINOUT
FEATURES
High-speed access times:
8, 10, 12 ns
High-performance, low-power CMOS process
Multiple center power and ground pins for
greater noise immunity
Easy memory expansion with
CE
and
OE
options
CE
power-down
Fully static operation: no clock or refresh
required
TTL compatible inputs and outputs
Single 3.3V power supply
Packages available:
32-pin 300-mil SOJ
32-pin 400-mil SOJ
DESCRIPTION
The
ISSI
IS63LV1024L is a very high-speed, low power,
131,072-word by 8-bit CMOS static RAM in revolutionary
pinout. The IS63LV1024L is fabricated using
ISSI
's
high-performance CMOS technology. This highly reliable
process coupled with innovative circuit design
techniques, yields higher performance and low power
consumption devices.
When
CE
is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 250 W (typical) with CMOS input levels.
The IS63LV1024L operates from a single 3.3V power
supply and all inputs are TTL-compatible.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
CE
OE
WE
128K X 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
AUGUST 2002
32-pin TSOP (Type II)
32-pin STSOP (Type I)
36-pin BGA (8mmx10mm)
2
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. B
08/07/02
IS63LV1024L
ISSI
PIN CONFIGURATION
32-Pin SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A0
A1
A2
A3
CE
I/O0
I/O1
Vcc
GND
I/O2
I/O3
WE
A4
A5
A6
A7
A16
A15
A14
A13
OE
I/O7
I/O6
GND
Vcc
I/O5
I/O4
A12
A11
A10
A9
A8
PIN DESCRIPTIONS
A0-A16
Address Inputs
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Bidirectional Ports
Vcc
Power
GND
Ground
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A0
A1
A2
A3
CE
I/O0
I/O1
Vcc
GND
I/O2
I/O3
WE
A4
A5
A6
A7
A16
A15
A14
A13
OE
I/o7
I/O6
GND
Vcc
I/O5
I/O4
A12
A11
A10
A9
A8
PIN CONFIGURATION
32-Pin TSOP (Type II) (T)
32-Pin STSOP (Type I) (H)
PIN CONFIGURATION
36-mini BGA (B) (8 mm x 10 mm)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
A0
A1
NC
A3
A6
A8
I/O4
A2
WE
A4
A7
I/O
0
I/O5
NC
A5
I/O
1
GND
Vcc
Vcc
GND
I/O6
NC
NC
I/O
2
I/O7
OE
CE
A16
A15
I/O
3
A9
A10
A11
A12
A13
A14
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
3
Rev. B
08/07/02
IS63LV1024L
ISSI
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
TERM
Terminal Voltage with Respect to GND
0.5 to Vcc + 0.5
V
T
BIAS
Temperature Under Bias
55 to +125
C
T
STG
Storage Temperature
65 to +150
C
P
T
Power Dissipation
1.0
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
TRUTH TABLE
Mode
WE
WE
WE
WE
WE
CE
CE
CE
CE
CE
OE
OE
OE
OE
OE
I/O Operation
Vcc Current
Not Selected
X
H
X
High-Z
I
SB
1
, I
SB
2
(Power-down)
Output Disabled
H
L
H
High-Z
I
CC
1
, I
CC
2
Read
H
L
L
D
OUT
I
CC
1
, I
CC
2
Write
L
L
X
D
IN
I
CC
1
, I
CC
2
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
= 4.0 mA
2.4
--
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 8.0 mA
--
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+ 0.3
V
V
IL
Input LOW Voltage
(1)
0.3
0.8
V
I
LI
Input Leakage
GND
V
IN
V
CC
Com.
1
1
A
Ind.
5
5
I
LO
Output Leakage
GND
V
OUT
V
CC
, Outputs Disabled
Com.
1
1
A
Ind.
5
5
Notes:
1. V
IL
= 3.0V for pulse width less than 10 ns.
OPERATING RANGE
Range
Ambient Temperature
V
CC
Commercial
0C to +70C
3.3V 0.3V
Industrial
40C to +85C
3.3V 0.15V
4
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. B
08/07/02
IS63LV1024L
ISSI
CAPACITANCE
(1,2)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
I/O
Input/Output Capacitance
V
OUT
= 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25C, f = 1 MHz, Vcc = 3.3V.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-8 ns
-10 ns
-12 ns
Symbol Parameter
Test Conditions
Min.
Max.
Min.
Max.
Min.
Max.
Unit
I
CC
1
Vcc Operating
V
CC
= Max.,
CE
= V
IL
Com.
--
100
--
95
--
90
mA
Supply Current
I
OUT
= 0 mA, f = Max.
Ind.
--
110
--
105
--
100
I
SB
TTL Standby
V
CC
= Max.,
Com.
--
35
--
30
--
25
mA
Current
V
IN
= V
IH
or V
IL
Ind.
--
40
--
35
--
30
(TTL Inputs)
CE
V
IH
, f = Max
I
SB
1
TTL Standby
V
CC
= Max.,
Com.
--
15
--
15
--
15
mA
Current
V
IN
= V
IH
or V
IL
Ind.
--
20
--
20
--
20
(TTL Inputs)
CE
V
IH
, f = 0
I
SB
2
CMOS Standby
V
CC
= Max.,
Com.
--
1
--
1
--
1
mA
Current
CE
V
CC
0.2V,
Ind.
--
1.5
--
1.5
--
1.5
(CMOS Inputs)
V
IN
V
CC
0.2V, or
V
IN
0.2V, f = 0
Notes:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
5
Rev. B
08/07/02
IS63LV1024L
ISSI
AC TEST LOADS
AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 3.0V
Input Rise and Fall Times
3 ns
Input and Output Timing
1.5V
and Reference Levels
Output Load
See Figures 1a and 1b
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-8 ns
-10 ns
-12 ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
RC
Read Cycle Time
8
--
10
--
12
--
ns
t
AA
Address Access Time
--
8
--
10
--
12
ns
t
OHA
Output Hold Time
2
--
2
--
2
--
ns
t
ACE
CE
Access Time
--
8
--
10
--
12
ns
t
DOE
OE
Access Time
--
4
--
5
--
6
ns
t
LZOE
(2)
OE
to Low-Z Output
0
--
0
--
0
--
ns
t
HZOE
(2)
OE
to High-Z Output
0
4
0
5
0
6
ns
t
LZCE
(2)
CE
to Low-Z Output
3
--
3
--
3
--
ns
t
HZCE
(2)
CE
to High-Z Output
0
4
0
5
0
6
ns
t
PU
CE
to Power Up Time
0
--
0
--
0
--
ns
t
PD
CE
to Power Down Time
--
8
--
10
--
12
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and C1
output loading specified in Figure 1.
2. Tested with the C2 load in Figure 1. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
Figure 1
OUTPUT
V
T
= 1.5V
Z
OUT
= 50
50
317
5 pF
Including
jig and
scope
351
OUTPUT
3.3V
Figure 2
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