First Release

Ordering Information

General Description

The IXDN430/IXDI430/IXDD430/IXDS430 are high speed high
current gate drivers specifically designed to drive MOSFETs
and IGBTs to their minimum switching time and maximum
practical frequency limits. The IXD_430 can source and sink
30A of peak current while producing voltage rise and fall times
of less than 30ns. The input of the drivers are compatible with
TTL or CMOS and are fully immune to latch up over the entire
operating range. Designed with small internal delays, cross
conduction/current shoot-through is virtually eliminated in all
configurations. Their features and wide safety margin in
operating voltage and power make the drivers unmatched in
performance and value.

The IXD_430 incorporates a unique ability to disable the output
under fault conditions. The standard undervoltage lockout is at
12.5V which can also be set to 8.5V in the IXDS430SI. When a
logical low is forced into the Enable inputs, both final output
stage MOSFETs (NMOS and PMOS) are turned off. As a
result, the output of the IXDD430 enters a tristate mode and
enables a Soft Turn-Off of the MOSFET when a short circuit is
detected. This helps prevent damage that could occur to the
MOSFET if it were to be switched off abruptly due to a dv/dt
over-voltage transient.

The IXDN430 is configured as a noninverting gate driver, and the
IXDI430 is an inverting gate driver. The IXDS430 can be configured
either as a noninverting or inverting driver. The IXD_430 are available
in the standard 28-pin SIOC (SI-CT), 5-pin TO-220 (CI), and in the
TO-263 (YI) surface mount packages. CT or 'Cool Tab' for the 28-
pin SOIC package refers to the backside metal heatsink tab.

Features

· Built using the advantages and compatibility
of CMOS and IXYS HDMOS

processes

· Latch-Up Protected
· High Peak Output Current: 30A Peak
· Wide Operating Range: 8.5V to 35V
· Under Voltage Lockout Protection
· Ability to Disable Output under Faults
· High Capacitive Load
Drive Capability: 5600 pF in <25ns
· Matched Rise And Fall Times
· Low Propagation Delay Time
· Low Output Impedance
· Low Supply Current

Applications

· Driving MOSFETs and IGBTs
· Motor Controls
· Line Drivers
· Pulse Generators
· Local Power ON / OFF Switch
· Switch Mode Power Supplies (SMPS)
· DC to DC Converters
· Pulse Transformer Driver
· Limiting di/dt Under Short Circuit
· Class D Switching Amplifiers

P a rt N u m b e r

P a c k a g e T yp e

T e m p . R a n g e

C o n fig u ra tio n

IX D D 4 3 0 Y I 5 -p in

T O -2 6 3

IX D D 4 3 0 C I 5 -p in

T O -2 2 0

-5 5 °C to + 1 2 5 °

N o n In ve rtin g w ith

E n a b le

IX D I4 3 0 Y I 5 -p in

T O -2 6 3

IX D I4 3 0 C I 5 -p in

T O -2 2 0

-5 5 °C to + 1 2 5 °

In ve rtin g

IX D N 4 3 0 Y I 5 -p in

T O -2 6 3

IX D N 4 3 0 C I 5 -p in

T O -2 2 0

-5 5 °C to + 1 2 5 °

N o n In ve rtin g

IX D S 4 3 0 S I 2 8 -p in

S O IC

-5 5 °C to + 1 2 5 °

In ve rtin g / N o n

In ve rtin g w ith E n a b le

a n d U V S E L

30 Amp Low-Side Ultrafast MOSFET / IGBT Driver

IXDN430 / IXDI430 / IXDD430 / IXDS430

DS99045B(8/04)

IXDN430 / IXDI430 / IXDD430 / IXDS430

Unless otherwise noted, T

= 25

C, 8.5V

35V .

All voltage measurements with respect to GND. IXDD430 configured as described in Test Conditions.

Electrical Characteristics

S ym bol Param eter

T est

C onditio n s

M in

T yp

M ax U nits

High input v oltage

4.5V

C C

18V

3.5 V

Low

input

v oltage 4.5V

C C

18V

0.8

Input

v oltage

range

-5

C C

+ 0.3

Input

current

C C

-10 10

µA

High

output

v oltage

C C

- 0.025

Low

output

v oltage

0.025

O utput

resistance

@ O utput high

C C

= 18V

0.3

0.4

O utput

resistance

@ O utput Low

C C

= 18V

0.2

0.3

PEA K

Peak

output

current V

C C

= 18V

30 A

D C

Continuous

output

current

Lim ited by package power
dissipation

Enable v oltage range

IXD D430 O nly

- 0.3

Vcc + 0.3

ENH

High E n Input V oltage

IXD D430 O nly

2/3 V cc

ENL

Low En Input V oltage

IXD D430 O nly

1/3 V cc

EN Input R esistance

IXD S430 O nly

400

K ohm

INV

INV Voltage Range

IXD S430 O nly

- 0.3

Vcc + 0.3

INVH

High IN V Input Voltage

IXD S430 O nly

2/3 V cc

INVL

Low IN V Input V oltage

IXD S430 O nly

1/3 V cc

INV

INV Input R esistance

IXD S430 O nly

400

K ohm

Rise

tim e

= 5600pF V cc= 18V

Fall

tim e

= 5600pF V cc= 18V

O ND LY

O n-tim e

propagation

delay

= 5600pF V cc= 18V

O FFD LY

Off-tim e

propagation

delay

= 5600pF V cc= 18V

E NO H

Enable to output high
delay tim e

IXD D430 O nly, Vcc=18V

D OLD

Disable to output low
delay tim e

IXD D430 O nly, Vcc=18V

120

C C

Power

supply

v oltage

8.5 18 35 V

C C

Power supply current

= 3.5V

= 0V

= + V

10
10

m A

µA
µA

Absolute Maximum Ratings

(Note 1)

Parameter

Value

Supply Voltage

40 V

All Other Pins

-0.3 V to VCC + 0.3 V

Power Dissipation, T

AMBIENT

25 oC

TO220 (CI), TO263 (YI)

Derating Factors (to Ambient)

TO220 (CI), TO263 (YI)

0.016W/oC

Storage Temperature

-65 oC to 150 oC

Lead Temperature (10 sec)

300 oC

Operating Ratings

P aram eter

V alue

M axim um Junction Tem perature

150 oC

O perating Tem perature R ange

-55 oC to 125 oC

Therm al Im pedance TO 220 (C I), TO 263 (Y I)

(Junction To C ase)

0.95 oC /W

(Junction To Am bient)

62.5 oC /W

Therm al Im pedance 28 pin S O IC with H eat S lug (S I)

(Junction To C ase)

3 oC /W

Specifications Subject To Change Without Notice

Note 1: Operating the device beyond parameters with listed "absolute maximum ratings" may cause permanent
damage to the device. Typical values indicate conditions for which the device is intended to be functional, but do not
guarantee specific performance limits. The guaranteed specifications apply only for the test conditions listed.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

IXDN430 / IXDI430 / IXDD430 / IXDS430

Symbol Parameter

Test

Conditions

Min

Typ

Max Units

High input voltage

4.5V

18V

3.2 V

Low

input

voltage 4.5V V

18V

1.1

Input

voltage

range

-5

+ 0.3

Output

resistance

@ Output high

= 18V

0.46

Output

resistance

@ Output Low

= 18V

0.4

Rise

time

=5600pF Vcc=18V

Fall

time

=5600pF Vcc=18V

ONDLY

On-time

propagation

delay

=5600pF Vcc=18V

OFFDLY

Off-time

propagation

delay

=5600pF Vcc=18V

Power

supply

voltage

8.5 18 35 V

Electrical Characteristics

Unless otherwise noted, temperature over -55

C to +125

C, 4.5

35V .

All voltage measurements with respect to GND. IXDD430 configured as described in Test Conditions.

NOTE: Mounting tabs, solder tabs, or heat sink metalization on all packages are connected to ground.

5-lead TO-220 Outline (IXD_430CI)

28-pin SOIC Outline (IXD_430SI)

5-lead TO-263 Outline (IXD_430YI)

IXDN430 / IXDI430 / IXDD430 / IXDS430

Pin Description

SYMBOL FUNCTION

DESCRIPTION

VCC Supply

Voltage

Positive power-supply voltage input. This pin provides power to the
entire chip. The range for this voltage is from 8.5V to 35V.

Input

Input signal-TTL or CMOS compatible.

EN *

Enable

The system enable pin. This pin, when driven low, disables the chip,
forcing high impedance state to the output (IXDD430 Only).

INV Invert

Forcing INV low causes the IXDS430 to become non-inverted, while
forcing INV high causes the IXDS430 to become inverted.

OUT P
OUT N

Output

Respective P and N driver outputs. For application purposes this pin
is connected, through a resistor, to Gate of a MOSFET/IGBT. The P
and N output pins are connected together in the TO-263 and TO-220
packages.

GND Ground

The system ground pin. Internally connected to all circuitry, this pin
provides ground reference for the entire chip. This pin should be
connected to a low noise analog ground plane for optimum
performance.

UVSEL

Select Under

Voltage Level

With UVSEL connected to Vcc, IXDS430 outputs go low at Vcc <
8.5V; W ith UVSEL open, under voltage level is set at Vcc < 12.5V

Figure 2 - Characteristics Test Diagram

* This pin is used only on the IXDD430, and is N/C (not connected) on the IXDI430 and IXDN430.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD procedures when
handling and assembling this component.

TO220 (CI)
TO263 (YI)

Vcc

OUT
GND

EN *

1
2

3
4
5

Pin Configurations

(SI-CT)

28 Pin SOIC

Vcc 4

Vcc 3

Vcc 2

Vcc 1

25 Vcc

26 Vcc

27 Vcc

28 Vcc

18 GND

GND 11

16 GND

17 GND

15 GND

GND 13

GND 12

22 OUT P

23 OUT P

24 OUT P

19 OUT N

20 OUT N

21 OUT N

GND 14

N/C 7

N/C 5

UVSEL 6

IN 8
EN 9

INV 10

Vin

Vcc

GND

OUT

Vcc

IXDD430

LOAD

BYPASS/

FILTER

IXDN430 / IXDI430 / IXDD430 / IXDS430

Rise and Fall Times vs. Temperature

= 5600 pF, Vcc = 18V

-60

-10

140

190

Temperature (C)

(

s
)

Output Rise Times vs. Load Capacitance

1000

3000

5000

7000

9000

11000

13000

15000

Load Capacitance (pF)

se T

i
me (ns)

13V

18V

35V

Output Fall Times vs. Load Capacitance

1000

3000

5000

7000

9000

11000

13000

15000

Load Capacitance (pF)

l
l
Ti

e
(n

s
)

13V

18V

35V

Rise Times vs. Supply Voltage

Supply Voltage (V)

i
se

i
m

e
(

n
s)

1000 pF

5600 pF

10000 pF

15000 pF

Fall Times vs. Supply Voltage

Supply Voltage (V)

l
l
Ti

e
(n

s
)

1000 pF

5600 pF

10000 pF

15000 pF

Typical Performance Characteristics

Fig. 3

Fig. 4

Fig. 5

Fig. 6

Fig. 7

Fig. 8

Max / Min Input vs. Temperature

CL = 5600pF, Vcc = 18V

0.5

1.5

2.5

3.5

-60

-10

140

190

Temperature (C)

a
x /

i
n I

nput

Vol

t
age

Min Input High

Max Input Low

IXDN430 / IXDI430 / IXDD430 / IXDS430

Supply Current vs. Frequency

Vcc = 25V

0.1

100

1000

100

1000

10000

Frequency (kHz)

upply Current

)

1000 pF

5600 pF

10000 pF

15000 pF

Supply Current vs. Load Capacitance

Vcc = 25V

100

150

200

250

300

350

400

1000

10000

100000

Load Capacitance (pF)

uppl

y C

r
r
ent

(

)

10 kHz

50 kHz

100 kHz

500 kHz

1 MHz

2 MHz

Supply Current vs. Frequency

Vcc = 18V

0.1

100

1000

100

1000

10000

Frequency (kHz)

upply C

u
rrent (mA

)

1000 pF

5600 pF

10000 pF

15000 pF

Supply Current vs. Load Capacitance

Vcc = 18V

100

150

200

250

300

1000

10000

100000

Load Capacitance (pF)

uppl

y C

r
r
ent

(

)

2 MHz

1 MHz

500 kHz

100 kH

50 kHz

10 kHz

Supply Current vs. Load Capacitance

Vcc = 13V

100

150

200

250

300

1000

10000

100000

Load Capacitance (pF)

uppl

y Current (m

)

10 kHz

50 kHz

100 kHz

500 kHz

1 MHz

2 MHz

Supply Current vs. Frequency

Vcc = 13V

0.1

100

1000

100

1000

10000

Frequency (kHz)

Supply Current

(mA)

1000 pF

5600 pF

10000 pF

15000 pF

Fig. 10

Fig. 11

Fig. 12

Fig. 14

Fig. 9

Fig. 13

IXDN430 / IXDI430 / IXDD430 / IXDS430

Supply Current vs. Load Capacitance

Vcc = 35V

100

150

200

250

300

350

400

1000

10000

100000

Load Capacitance (pF)

Supply C

r
r
ent

(

10 kHz

50 kHz

100 kHz

500 kHz

1 MHz

Supply Current vs. Frequency

Vcc = 35V

100

1000

100

1000

10000

Frequency (kHz)

Supply C

u
rrent (mA)

1000 pF

5600 pF

10000 pF

15000 pF

Fig. 16

Fig. 17

Fig. 18

Fig. 19

Fig. 20

Fig. 15

Quiescent Supply Current vs. Temperature
Vcc = 18V, Vin = 15V@1kHz, C

= 5600pF

0.1

0.2

0.3

0.4

0.5

0.6

-60

-10

140

190

Temperature (C)

i
e
sce

n
t
V

cc I

n
p
u
t
Cu

r
r
e
n
t
(

)

Propagation Delay Times vs. Temperature

= 5600pF, Vcc = 18V

-60

-10

140

190

Temperature (C)

Time (ns)

ONDLY

OFFDLY

Propagation Delay vs. Supply Voltage

= 5600 pF Vin = 15V@1kHz

Supply Voltage (V)

r
opagation D

lay (ns)

ONDLY

OFFDLY

Propagation Delay vs. Input Voltage

= 5600 pF Vcc = 18V

Input Voltage (V)

opagat

i
on Del

a
y
(

n
s
)

ONDLY

OFFDLY

IXDN430 / IXDI430 / IXDD430 / IXDS430

N Channel Output Current vs. Temperature

Vcc = 18V

-60

-10

140

190

Temperature (C)

N Channel Out

put

Current

)

P Channel Output Current vs. Vcc

-80

-70

-60

-50

-40

-30

-20

-10

Vcc (V)

Channel Out

p
ut

Current

)

High State Output Resistance vs. Supply Voltage

0.05

0.1

0.15

0.2

0.25

0.3

0.35

Supply Voltage (V)

i
gh St

e O

t
put

sist

ance (

hms)

P Channel Output Current vs. Temperature

Vcc = 18V

-60

-10

140

190

Temperature (C)

P C

hannel O

t
put

r
r
ent

(

)

Fig. 21

Fig. 22

Fig. 23

Fig. 24

N Channel Output Current vs. Vcc

Vcc (V)

hannel

t
put

r
r
ent

(

)

Fig. 25

Fig. 26

Low State Output Resistance vs. Supply Voltage

0.05

0.1

0.15

0.2

0.25

Supply Voltage (V)

Low S

t
at

e Out

put

Resist

ance (Ohm

IXDN430 / IXDI430 / IXDD430 / IXDS430

Short Circuit di/dt Limit

A short circuit in a high-power MOSFET module such as the
VM0580-02F, (580A, 200V), as shown in Figure 27, can cause
the current through the module to flow in excess of 1500A for
10

µs or more prior to self-destruction due to thermal runaway.

For this reason, some protection circuitry is needed to turn off
the MOSFET module. However, if the module is switched off
too fast, there is a danger of voltage transients occuring on the
drain due to Ldi/dt, (where L represents total inductance in
series with drain). If these voltage transients exceed the
MOSFET's voltage rating, this can cause an avalanche break-
down.

The IXDD430 has the unique capability to softly switch off the
high-power MOSFET module, significantly reducing these
Ldi/dt transients.

Thus, the IXDD430 helps to prevent device destruction from
both dangers; over-current, and avalanche breakdown due to
di/dt induced over-voltage transients.

The IXDD430 is designed to not only provide ±30A under
normal conditions, but also to allow it's output to go into a high
impedance state. This permits the IXDD430 output to control
a separate weak pull-down circuit during detected overcurrent
shutdown conditions to limit and separately control d

VGS

/dt gate

turnoff. This circuit is shown in Figure 28.

Referring to Figure 28, the protection circuitry should include
a comparator, whose positive input is connected to the source
of the VM0580-02. A low pass filter should be added to the input
of the comparator to eliminate any glitches in voltage caused
by the inductance of the wire connecting the source resistor to
ground. (Those glitches might cause false triggering of the
comparator).

The comparator's output should be connected to a SRFF(Set
Reset Flip Flop). The flip-flop controls both the Enable signal,
and the low power MOSFET gate. Please note that CMOS
4000-series devices operate with a V

range from 3 to 15 VDC,

(with 18 VDC being the maximum allowable limit).

A low power MOSFET, such as the 2N7000, in series with a
resistor, will enable the VMO580-02F gate voltage to drop
gradually. The resistor should be chosen so that the RC time
constant will be 100us, where "C" is the Miller capacitance of
the VMO580-02F.

For resuming normal operation, a Reset signal is needed at
the SRFF's input to enable the IXDD430 again. This Reset can
be generated by connecting a One Shot circuit between the
IXDD430 Input signal and the SRFF restart input. The One Shot
will create a pulse on the rise of the IXDD430 input, and this
pulse will reset the SRFF outputs to normal operation.

When a short circuit occurs, the voltage drop across the low-
value, current-sensing resistor, (Rs=0.005 Ohm), connected
between the MOSFET Source and ground, increases. This
triggers the comparator at a preset level. The SRFF drives a
low input into the Enable pin disabling the IXDD430 output. The
SRFF also turns on the low power MOSFET, (2N7000).

In this way, the high-power MOSFET module is softly turned off
by the IXDD430, preventing its destruction.

APPLICATIONS INFORMATION

Supply Bypassing and Grounding Practices,
Output Lead inductance

When designing a circuit to drive a high speed MOSFET
utilizing the IXDD430/IXDI430/IXDN430, it is very important to
keep certain design criteria in mind, in order to optimize
performance of the driver. Particular attention needs to be paid
to Supply Bypassing, Grounding, and minimizing the Output
Lead Inductance.

Say, for example, we are using the IXDD430 to charge a 15nF
capacitive load from 0 to 25 volts in 25ns.

Using the formula: I= C

V / t, where V=25V C=15nF &

t=25ns we can determine that to charge 15nF to 25 volts in

25ns will take a constant current of 15A. (In reality, the charging
current won't be constant, and will peak somewhere around
30A).

SUPPLY BYPASSING
In order for our design to turn the load on properly, the IXDD430
must be able to draw this 5A of current from the power supply
in the 25ns. This means that there must be very low impedance
between the driver and the power supply. The most common
method of achieving this low impedance is to bypass the power
supply at the driver with a capacitance value that is a magnitude
larger than the load capacitance. Usually, this would be
achieved by placing two different types of bypassing capacitors,
with complementary impedance curves, very close to the driver
itself. (These capacitors should be carefully selected, low
inductance, low resistance, high-pulse current-service
capacitors). Lead lengths may radiate at high frequency due
to inductance, so care should be taken to keep the lengths of
the leads between these bypass capacitors and the IXDD430
to an absolute minimum.

GROUNDING
In order for the design to turn the load off properly, the IXDD430
must be able to drain this 5A of current into an adequate
grounding system. There are three paths for returning current
that need to be considered: Path #1 is between the IXDD430
and it's load. Path #2 is between the IXDD430 and it's power
supply. Path #3 is between the IXDD430 and whatever logic is
driving it. All three of these paths should be as low in resistance
and inductance as possible, and thus as short as practical. In
addition, every effort should be made to keep these three
ground paths distinctly separate. Otherwise, (for instance), the
returning ground current from the load may develop a voltage
that would have a detrimental effect on the logic line driving the
IXDD430.

IXDN430 / IXDI430 / IXDD430 / IXDS430

IXYS Semiconductor GmbH
Edisonstrasse15 ; D-68623; Lampertheim
Tel: +49-6206-503-0; Fax: +49-6206-503627
e-mail: marcom@ixys.de

IXYS Corporation
3540 Bassett St; Santa Clara, CA 95054
Tel: 408-982-0700; Fax: 408-496-0670
www.ixys.com
e-mail: sales@ixys.net

OUTPUT LEAD INDUCTANCE
Of equal importance to Supply Bypassing and Grounding are
issues related to the Output Lead Inductance. Every effort
should be made to keep the leads between the driver and it's
load as short and wide as possible. If the driver must be placed
farther than 2" from the load, then the output leads should be
treated as transmission lines. In this case, a twisted-pair
should be considered, and the return line of each twisted pair
should be placed as close as possible to the ground pin of the
driver, and connect directly to the ground terminal of the load.

A TTL high, V

TTLHIGH

=>~2.4V, or a 5V CMOS high,

5VCMOSHIGH

=~>3.5V, applied to the EN input of the circuit in

Figure 29 will cause Q1 to be biased off. This results in Q1
collector being pulled up by R3 to V

=15V, and provides a

high voltage CMOS logic high output. The high voltage CMOS
logical EN output applied to the IXDD430 EN input will enable
it, allowing the gate driver to fully function as an 30

Amp

output driver.

The total component cost of the circuit in Figure 29 is less
than $0.10 if purchased in quantities >1K pieces. It is
recommended that the physical placement of the level
translator circuit be placed close to the source of the TTL or
CMOS logic circuits to maximize noise rejection.

Figure 29 - TTL to High Voltage CMOS Level Translator

TTL to High Voltage CMOS Level Translation
(IXDD430 Only)

The enable (EN) input to the IXDD430 is a high voltage
CMOS logic level input where the EN input threshold is ½
V

, and may not be compatible with 5V CMOS or TTL input

levels. The IXDD430 EN input was intentionally designed
for enhanced noise immunity with the high voltage CMOS
logic levels. In a typical gate driver application, V

=15V

and the EN input threshold at 7.5V, a 5V CMOS logical high
input applied to this typical IXDD430 application's EN input
will be misinterpreted as a logical low, and may cause
undesirable or unexpected results. The note below is for
optional adaptation of TTL or 5V CMOS levels.

A TTL or 5V CMOS logic low, V

TTLLOW

=~<0.8V, input applied to the

Q1 emitter will drive it on. This causes the level translator
output, the Q1 collector output to settle to V

CESATQ1

TTLLOW

=<~2V, which is sufficiently low to be correctly interpreted

as a high voltage CMOS logic low (<1/3V

=5V for V

=15V given

in the IXDD430 data sheet.)

The circuit in Figure 29 alleviates this potential logic level
misinterpretation by translating a TTL or 5V CMOS logic
input to high voltage CMOS logic levels needed by the
IXDD430 EN input. From the figure, V

is the gate driver

power supply, typically set between 8V to 20V, and V

the logic power supply, typically between 3.3V to 5.5V.
Resistors R1 and R2 form a voltage divider network so
that the Q1 base is positioned at the midpoint of the
expected TTL logic transition levels.

2N3904

10K

Vdd

Vcc

(From gate driver

power supply)

5V CMOS or TTL input

(From logic

(To IXDD430 EN input)

CMOS EN output

High Voltage

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IXDI430

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IXDI430