Document Outline
- Features
- Description
- VTERM
- Terminal Voltage with Respect to VSS
- 0.5 to +4.6
- 0.5 to +4.6
- V
- TBIAS
- Temperature Under Bias
- 55 to +125
- 65 to +135
- C
- TSTG
- Storage Temperature
- 55 to +125
- 65 to +150
- C
- PT
- Power Dissipation
- 1.0
- 1.0
- W
- IOUT
- DC Output Current
- 50
- 50
- mA
- Tj
- Maximum Junction Temperature (2)
- 125
- 145
- C
- VCC
- Supply Voltage
- 3.0
- 3.3
- 3.6
- V
- VSS
- Supply Voltage
- 0
- 0
- 0
- V
- Industrial
- Ambient Temperature
- 40
- 25
- 85
- C
- Commercial
- Ambient Temperature
- 0
- 25
- 70
- C
- Functional Block Diagram
- ILI
- Input Leakage Current
- VCC = Max., VIN = VSS to VCC
- 5
- 5
- mA
- ILO
- Output Leakage Current
- VCC = Max.,
- CE = VIH
- VOUT = VSS to VCC
- 5
- 5
- mA
- VIL
- Input Low Voltage
- 0.3(1)
- 0.8
- V
- VIH
- Input High Voltage
- 2.2
- Vcc+0.3
- V
- VOL
- Output Low Voltage
- IOL = 8 mA, VCC = Min.
-
- 0.4
- V
- VOH
- Output High Voltage
- IOH = 4 mA, VCC = Min.
- 2.4
-
- V
- ICC
- Operating Current
- CE = VIL
- 190
- 175
- 165
- 175
- 155
- 165
- 145
- 155
- mA
- f = fMAX = 1/tRC
- VCC = Max.
- IOUT = 0 mA
- ISB
- Standby Current
- CE = VIH
- 50
- 45
- 40
- 45
- 35
- 40
- 30
- 35
- mA
- f = fMAX = 1/tRC
- VCC = Max.
- ISB1
- Full Standby Current
- CE VCC 0.2V
- 10
- 10
- 10
- 10
- 10
- 15
- 10
- 15
- mA
- f = 0
- VCC = Max.,
- VIN VCC 0.2V or 0.2V
- CIN
- Input Capacitance
- 8
- pF
- COUT
- Output Capacitance
- 8
- pF
- X
- X
- H
- Hi-Z
- Standby
- X
- X
- X
- Hi-Z
- Standby
- L
- H
- L
- DOUT
- Read
- X
- L
- L
- DIN
- Write
- H
- H
- L
- Hi-Z
- Output Disable
- Pin Configuration
- WRITE cycle time
- tWC
- 8
-
- 10
-
- 12
-
- 15
-
- 20
-
- ns
- Chip enable to end of write
- tCW
- 7
-
- 8
-
- 10
-
- 11
-
- 13
-
- ns
- Address valid to end of write
- tAW
- 7
-
- 8
-
- 10
-
- 11
-
- 13
-
- ns
- Address setup time
- tAS
- 0
-
- 0
-
- 0
-
- 0
-
- 0
-
- ns
- Address hold from end of write
- tAH
- 0
-
- 0
-
- 0
-
- 0
-
- 0
-
- ns
- Write pulse width
- tWP
- 7
-
- 8
-
- 8
-
- 9
-
- 10
-
- ns
- Data setup time
- tDS
- 5
-
- 6
-
- 7
-
- 8
-
- 9
-
- ns
- Data hold time
- tDH
- 0
-
- 0
-
- 0
-
- 0
-
- 0
-
- ns
- Write disable to output in low Z(1,3)
- tLZWE
- 0
-
- 0
-
- 0
-
- 0
-
- 0
-
- ns
- Write enable to output in high Z(1,3)
- tHZWE
-
- 4
-
- 5
-
- 6
-
- 7
-
- 9
- ns
- A19-A0
- Address Inputs
- I/O3-I/O0
- Data Inputs/Outputs
- OE
- Output Enable Input
- WE
- Write Enable Input
- CE
- Chip Enable Inputs
- NC
- No Connect
- VCC
- Power (+3.3V)
- VSS
- Ground
- Input pulse levels
- VSS to 3.0V
- Input rise and fall times
- 2.5 ns
- Input timing reference levels
- 1.5V
- Output reference levels
- 1.5V
- Output load
- See Figures 1 and 2
- READ cycle time
- tRC
- 8
-
- 10
-
- 12
-
- 15
-
- 20
-
- ns
- Address access time
- tAA
-
- 8
-
- 10
-
- 12
-
- 15
-
- 20
- ns
- Chip enable access time
- tACE
-
- 8
-
- 10
-
- 12
-
- 15
-
- 20
- ns
- Output hold from address change
- tOH
- 3
-
- 3
-
- 3
-
- 3
-
- 3
-
- ns
- Chip enable to output in low Z(1,3)
- tLZCE
- 3
-
- 3
-
- 3
-
- 3
-
- 3
-
- ns
- Chip disable to output in high Z(1,2,3)
- tHZCE
-
- 4
-
- 5
-
- 6
-
- 7
-
- 7
- ns
- Output enable access time
- tAOE
-
- 4
-
- 5
-
- 6
-
- 7
-
- 8
- ns
- Output Enable to output in low Z (1,3)
- tLZOE
- 0
-
- 0
-
- 0
-
- 0
-
- 0
-
- ns
- Output disable to output in high Z(1,3)
- tHZOE
-
- 4
-
- 4
-
- 5
-
- 6
-
- 7
- ns
- PDM31098
- 4 Megabit 3.3V Static RAM
- 1Mx 4-Bit
Rev. 1.3 - 5/27/98
1
PRELIMINARY
1
2
3
4
5
6
7
8
9
10
11
12
4 Megabit 3.3V Static RAM
1Mx 4-Bit
Features
n
High-speed access times
Com'l: 8, 10 12, 15, and 20 ns
Ind'l.: 12, 15, 20 ns
n
Low power operation (typical)
- PDM31098SA
Active: 300 mW
Standby: 25 mW
n
Single +3.3V (
0.3V) power supply
n
TTL-compatible inputs and outputs
n
Packages
Plastic SOJ (400 mil) - SO
Description
The PDM31098 is a high-performance CMOS static
RAMs organized as 1,048,576 x 4 bits. Writing is
accomplished when the write enable (WE) and chip
enable CE inputs are both LOW. Reading is
accomplished when WE remains HIGH and OE and
CE are both LOW.
The PDM31098 operates from a single +3.3V power
supply and all the inputs and outputs are fully TTL-
compatible.
The PDM31098 is available in a 32-pin 400-mil plas-
tic SOJ package.
PDM31098
A
A
0
19
I/O
I/O
0
7
Addresses
Decoder
Memory
Matrix
Input
Data
Control
Column I/O
CE
WE
OE
Functional Block Diagram
PRELIMINARY
PDM31098
2
Rev. 1.3 -5/27/98
Absolute Maximum Ratings
(1)
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Appropriate thermal calculations should be performed in all cases and specifically for
those where the chosen package has a large thermal resistance (e.g., TSOP). The cal-
culation should be of the form
: T
j
= T
a
+ P *
ja
where T
a
is the ambient temperature, P
is average operating power and
ja
the thermal resistance of the package. For this
product, use the following
ja
value:
SOJ: 59
o
C/W
TSOP : 90
o
C/W
Symbol
Rating
Com'l.
Ind.
Unit
V
TERM
Terminal Voltage with Respect to V
SS
0.5 to +4.6
0.5 to +4.6
V
T
BIAS
Temperature Under Bias
55 to +125
65 to +135
C
T
STG
Storage Temperature
55 to +125
65 to +150
C
P
T
Power Dissipation
1.0
1.0
W
I
OUT
DC Output Current
50
50
mA
T
j
Maximum Junction Temperature
(2)
125
145
C
Pin Configuration
Truth Table
(1)
NOTE: 1. H = V
IH
, L = V
IL
, X = DON'T CARE
OE
WE
CE
I/O
MODE
X
X
H
Hi-Z
Standby
X
X
X
Hi-Z
Standby
L
H
L
D
OUT
Read
X
L
L
D
IN
Write
H
H
L
Hi-Z
Output Disable
Name
Description
A19-A0
Address Inputs
I/O3-I/O0
Data Inputs/Outputs
OE
Output Enable Input
WE
Write Enable Input
CE
Chip Enable Inputs
NC
No Connect
V
CC
Power (+3.3V)
V
SS
Ground
1
2
3
4
5
6
7
8
9
10
11
12
15
16
22
23
24
25
26
27
A0
A1
A2
A3
A4
CE
I/O0
Vcc
Vss
I/O1
WE
A5
A6
A7
A8
A9
A19
A18
A17
A16
A15
OE
I/O3
Vss
Vcc
I/O2
A14
A13
A12
A11
A10
NC
13
14
28
29
30
31
32
17
18
19
21
20
SOJ
PRELIMINARY
PDM31098
Rev. 1.3 - 5/27/98
3
1
2
3
4
5
6
7
8
9
10
11
12
DC Electrical Characteristics
(V
CC
= 3.3V,
0.3V)
NOTE:1.V
IL
(min) = 3.0V for pulse width less than 20 ns
Power Supply Characteristics
SHADED AREA = PRELIMINARY DATA
NOTES: All values are maximum guaranteed values.
Capacitance
(1)
(T
A
= +25
C, f = 1.0 MHz)
NOTE:1. This parameter is determined by device characterization but is not production tested.
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
I
LI
Input Leakage Current
V
CC
= Max., V
IN
= V
SS
to V
CC
5
5
A
I
LO
Output Leakage Current
V
CC
= Max.,
CE = V
IH
V
OUT
= V
SS
to V
CC
5
5
A
V
IL
Input Low Voltage
0.3
(1)
0.8
V
V
IH
Input High Voltage
2.2
Vcc+0.3
V
V
OL
Output Low Voltage
I
OL
= 8 mA, V
CC
= Min.
--
0.4
V
V
OH
Output High Voltage
I
OH
= 4 mA, V
CC
= Min.
2.4
--
V
-8
-10
-12
-15
-20
Symbol Parameter
Com'l
Com'l Com'l
Ind.
Com'l
Ind.
Com'l
Ind.
Unit
I
CC
Operating Current
CE = V
IL
190
175
165
175
155
165
145
155
mA
f = f
MAX
= 1/t
RC
V
CC
= Max.
I
OUT
= 0 mA
I
SB
Standby Current
CE = V
IH
50
45
40
45
35
40
30
35
mA
f = f
MAX
= 1/t
RC
V
CC
= Max.
I
SB1
Full Standby Current
CE
V
CC
0.2V
10
10
10
10
10
15
10
15
mA
f = 0
V
CC
= Max.,
V
IN
V
CC
0.2V or
0.2V
Symbol
Parameter
Max.
Unit
C
IN
Input Capacitance
8
pF
C
OUT
Output Capacitance
8
pF
PRELIMINARY
PDM31098
4
Rev. 1.3 -5/27/98
AC Test Conditions
Read Cycle No. 1
(4, 5)
Input pulse levels
V
SS
to 3.0V
Input rise and fall times
2.5 ns
Input timing reference levels
1.5V
Output reference levels
1.5V
Output load
See Figures 1 and 2
t
RC
t
AA
t
OH
PREVIOUS DATA VALID
DOUT
ADDR
DATA VALID
+3.3V
317
351
D
OUT
30 pF
+3.3V
317
351
D
OUT
5 pF
Figure 1. Output Load Equivalent
Figure 2. Output Load Equivalent
(for TLZCE, tHZCE, tLZWE, tLZOE, tHZOE)
PRELIMINARY
PDM31098
Rev. 1.3 - 5/27/98
5
1
2
3
4
5
6
7
8
9
10
11
12
Read Cycle No. 2
(2, 4, 6)
AC Electrical Characteristics
SHADED AREA = PRELIMINARY DATA
* V
CC
= 3.3V + 5%
Description
-8*
-10*
12
15
20
READ Cycle
Sym
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Units
READ cycle time
t
RC
8
--
10
--
12
--
15
--
20
--
ns
Address access time
t
AA
--
8
--
10
--
12
--
15
--
20
ns
Chip enable access time
t
ACE
--
8
--
10
--
12
--
15
--
20
ns
Output hold from address change
t
OH
3
--
3
--
3
--
3
--
3
--
ns
Chip enable to output in low Z
(1,3)
t
LZCE
3
--
3
--
3
--
3
--
3
--
ns
Chip disable to output in high Z
(1,2,3)
t
HZCE
--
4
--
5
--
6
--
7
--
7
ns
Output enable access time
t
AOE
--
4
--
5
--
6
--
7
--
8
ns
Output Enable to output in low Z
(1,3)
t
LZOE
0
--
0
--
0
--
0
--
0
--
ns
Output disable to output in high Z
(1,3)
t
HZOE
--
4
--
4
--
5
--
6
--
7
ns
t
RC
t
ACE
t
AA
t
LZCE
t
HZCE
t
LZOE
t
HZOE
t
AOE
ADDR
CE1
OE
D
OUT
DATA VALID
PRELIMINARY
PDM31098
6
Rev. 1.3 -5/27/98
Write Cycle No. 1 (Write Enable Controlled)
Write Cycle No. 2 (Write Enable Controlled)
t
WC
t
AW
t
WP2
t
AH
t
AS
t
DH
t
DS
t
LZWE
t
HZWE
ADDR
CE1
WE
D
OUT
HIGH-Z
D
IN
DATA VALID
NOTE: Output Enable (OE) is inactive (high)
t
WC
t
AW
t
WP1
t
CW
t
AH
t
AS
t
DH
t
DS
ADDR
CE1
WE
D
OUT
HIGH-Z
D
IN
DATA VALID
PRELIMINARY
PDM31098
Rev. 1.3 - 5/27/98
7
1
2
3
4
5
6
7
8
9
10
11
12
Write Cycle No. 3 (Chip Enable Controlled)
AC Electrical Characteristics
SHADED AREA = PRELIMINARY DATA
* V
CC
= 3.3V + 5%
NOTES: (For two previous Electrical Characteristics tables)
1.The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured
200 mV from steady state
voltage.
2.At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
.
3.This parameter is sampled.
4.WE is high for a READ cycle.
5.The device is continuously selected. All the Chip Enables are held in their active state.
6.The address is valid prior to or coincident with the latest occuring Chip Enable.
Description
-8*
-10*
-12
-15
-20
WRITE Cycle
Sym
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Units
WRITE cycle time
t
WC
8
--
10
--
12
--
15
--
20
--
ns
Chip enable to end of write
t
CW
7
--
8
--
10
--
11
--
13
--
ns
Address valid to end of write
t
AW
7
--
8
--
10
--
11
--
13
--
ns
Address setup time
t
AS
0
--
0
--
0
--
0
--
0
--
ns
Address hold from end of write
t
AH
0
--
0
--
0
--
0
--
0
--
ns
Write pulse width
t
WP
7
--
8
--
8
--
9
--
10
--
ns
Data setup time
t
DS
5
--
6
--
7
--
8
--
9
--
ns
Data hold time
t
DH
0
--
0
--
0
--
0
--
0
--
ns
Write disable to output in low Z
(1,3)
t
LZWE
0
--
0
--
0
--
0
--
0
--
ns
Write enable to output in high Z
(1,3)
t
HZWE
--
4
--
5
--
6
--
7
--
9
ns
NOTE: Output Enable (OE) is inactive (high)
t
WC
t
AW
t
WP1
t
AH
t
AS
t
DH
t
DS
ADDR
CE1
WE
D
OUT
HIGH-Z
D
IN
DATA VALID
PRELIMINARY
PDM31098
8
Rev. 1.3 -5/27/98
Device Type
Power
Speed
Package
Type
Process
Temp. Range
Preferred
Shipping
Container
Commercial (0
to +70
C)
Industrial (40
C to +85
C)
8/10
Commercial Only
12
15
20
SA
Standard Power
Blank
I
A
Automotive ( 40
C to +105
C)
Blank Tubes
TR Tape & Reel
TY Tray
PDM31098 - (1Mx4) Static RAM
XXXXX
X
XX
X
X
X
SO
32-pin 400-mil Plastic SOJ
Ordering Information
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TM
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